m66592-udc.c 42 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/err.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include "m66592-udc.h"
  31. MODULE_DESCRIPTION("M66592 USB gadget driver");
  32. MODULE_LICENSE("GPL");
  33. MODULE_AUTHOR("Yoshihiro Shimoda");
  34. MODULE_ALIAS("platform:m66592_udc");
  35. #define DRIVER_VERSION "21 July 2009"
  36. static const char udc_name[] = "m66592_udc";
  37. static const char *m66592_ep_name[] = {
  38. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  39. };
  40. static void disable_controller(struct m66592 *m66592);
  41. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  42. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  43. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  44. gfp_t gfp_flags);
  45. static void transfer_complete(struct m66592_ep *ep,
  46. struct m66592_request *req, int status);
  47. /*-------------------------------------------------------------------------*/
  48. static inline u16 get_usb_speed(struct m66592 *m66592)
  49. {
  50. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  51. }
  52. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  53. unsigned long reg)
  54. {
  55. u16 tmp;
  56. tmp = m66592_read(m66592, M66592_INTENB0);
  57. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  58. M66592_INTENB0);
  59. m66592_bset(m66592, (1 << pipenum), reg);
  60. m66592_write(m66592, tmp, M66592_INTENB0);
  61. }
  62. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  63. unsigned long reg)
  64. {
  65. u16 tmp;
  66. tmp = m66592_read(m66592, M66592_INTENB0);
  67. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  68. M66592_INTENB0);
  69. m66592_bclr(m66592, (1 << pipenum), reg);
  70. m66592_write(m66592, tmp, M66592_INTENB0);
  71. }
  72. static void m66592_usb_connect(struct m66592 *m66592)
  73. {
  74. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  75. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  76. M66592_INTENB0);
  77. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  78. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  79. }
  80. static void m66592_usb_disconnect(struct m66592 *m66592)
  81. __releases(m66592->lock)
  82. __acquires(m66592->lock)
  83. {
  84. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  85. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  86. M66592_INTENB0);
  87. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  88. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  89. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  90. spin_unlock(&m66592->lock);
  91. m66592->driver->disconnect(&m66592->gadget);
  92. spin_lock(&m66592->lock);
  93. disable_controller(m66592);
  94. INIT_LIST_HEAD(&m66592->ep[0].queue);
  95. }
  96. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  97. {
  98. u16 pid = 0;
  99. unsigned long offset;
  100. if (pipenum == 0)
  101. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  102. else if (pipenum < M66592_MAX_NUM_PIPE) {
  103. offset = get_pipectr_addr(pipenum);
  104. pid = m66592_read(m66592, offset) & M66592_PID;
  105. } else
  106. pr_err("unexpect pipe num (%d)\n", pipenum);
  107. return pid;
  108. }
  109. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  110. u16 pid)
  111. {
  112. unsigned long offset;
  113. if (pipenum == 0)
  114. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  115. else if (pipenum < M66592_MAX_NUM_PIPE) {
  116. offset = get_pipectr_addr(pipenum);
  117. m66592_mdfy(m66592, pid, M66592_PID, offset);
  118. } else
  119. pr_err("unexpect pipe num (%d)\n", pipenum);
  120. }
  121. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  122. {
  123. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  124. }
  125. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  126. {
  127. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  128. }
  129. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  130. {
  131. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  132. }
  133. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  134. {
  135. u16 ret = 0;
  136. unsigned long offset;
  137. if (pipenum == 0)
  138. ret = m66592_read(m66592, M66592_DCPCTR);
  139. else if (pipenum < M66592_MAX_NUM_PIPE) {
  140. offset = get_pipectr_addr(pipenum);
  141. ret = m66592_read(m66592, offset);
  142. } else
  143. pr_err("unexpect pipe num (%d)\n", pipenum);
  144. return ret;
  145. }
  146. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  147. {
  148. unsigned long offset;
  149. pipe_stop(m66592, pipenum);
  150. if (pipenum == 0)
  151. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  152. else if (pipenum < M66592_MAX_NUM_PIPE) {
  153. offset = get_pipectr_addr(pipenum);
  154. m66592_bset(m66592, M66592_SQCLR, offset);
  155. } else
  156. pr_err("unexpect pipe num(%d)\n", pipenum);
  157. }
  158. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  159. {
  160. u16 tmp;
  161. int size;
  162. if (pipenum == 0) {
  163. tmp = m66592_read(m66592, M66592_DCPCFG);
  164. if ((tmp & M66592_CNTMD) != 0)
  165. size = 256;
  166. else {
  167. tmp = m66592_read(m66592, M66592_DCPMAXP);
  168. size = tmp & M66592_MAXP;
  169. }
  170. } else {
  171. m66592_write(m66592, pipenum, M66592_PIPESEL);
  172. tmp = m66592_read(m66592, M66592_PIPECFG);
  173. if ((tmp & M66592_CNTMD) != 0) {
  174. tmp = m66592_read(m66592, M66592_PIPEBUF);
  175. size = ((tmp >> 10) + 1) * 64;
  176. } else {
  177. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  178. size = tmp & M66592_MXPS;
  179. }
  180. }
  181. return size;
  182. }
  183. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  184. {
  185. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  186. unsigned short mbw;
  187. if (ep->use_dma)
  188. return;
  189. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  190. ndelay(450);
  191. if (m66592->pdata->on_chip)
  192. mbw = M66592_MBW_32;
  193. else
  194. mbw = M66592_MBW_16;
  195. m66592_bset(m66592, mbw, ep->fifosel);
  196. }
  197. static int pipe_buffer_setting(struct m66592 *m66592,
  198. struct m66592_pipe_info *info)
  199. {
  200. u16 bufnum = 0, buf_bsize = 0;
  201. u16 pipecfg = 0;
  202. if (info->pipe == 0)
  203. return -EINVAL;
  204. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  205. if (info->dir_in)
  206. pipecfg |= M66592_DIR;
  207. pipecfg |= info->type;
  208. pipecfg |= info->epnum;
  209. switch (info->type) {
  210. case M66592_INT:
  211. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  212. buf_bsize = 0;
  213. break;
  214. case M66592_BULK:
  215. /* isochronous pipes may be used as bulk pipes */
  216. if (info->pipe > M66592_BASE_PIPENUM_BULK)
  217. bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
  218. else
  219. bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
  220. bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
  221. buf_bsize = 7;
  222. pipecfg |= M66592_DBLB;
  223. if (!info->dir_in)
  224. pipecfg |= M66592_SHTNAK;
  225. break;
  226. case M66592_ISO:
  227. bufnum = M66592_BASE_BUFNUM +
  228. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  229. buf_bsize = 7;
  230. break;
  231. }
  232. if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
  233. pr_err("m66592 pipe memory is insufficient\n");
  234. return -ENOMEM;
  235. }
  236. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  237. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  238. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  239. if (info->interval)
  240. info->interval--;
  241. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  242. return 0;
  243. }
  244. static void pipe_buffer_release(struct m66592 *m66592,
  245. struct m66592_pipe_info *info)
  246. {
  247. if (info->pipe == 0)
  248. return;
  249. if (is_bulk_pipe(info->pipe)) {
  250. m66592->bulk--;
  251. } else if (is_interrupt_pipe(info->pipe))
  252. m66592->interrupt--;
  253. else if (is_isoc_pipe(info->pipe)) {
  254. m66592->isochronous--;
  255. if (info->type == M66592_BULK)
  256. m66592->bulk--;
  257. } else
  258. pr_err("ep_release: unexpect pipenum (%d)\n",
  259. info->pipe);
  260. }
  261. static void pipe_initialize(struct m66592_ep *ep)
  262. {
  263. struct m66592 *m66592 = ep->m66592;
  264. unsigned short mbw;
  265. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  266. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  267. m66592_write(m66592, 0, ep->pipectr);
  268. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  269. if (ep->use_dma) {
  270. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  271. ndelay(450);
  272. if (m66592->pdata->on_chip)
  273. mbw = M66592_MBW_32;
  274. else
  275. mbw = M66592_MBW_16;
  276. m66592_bset(m66592, mbw, ep->fifosel);
  277. }
  278. }
  279. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  280. const struct usb_endpoint_descriptor *desc,
  281. u16 pipenum, int dma)
  282. {
  283. if ((pipenum != 0) && dma) {
  284. if (m66592->num_dma == 0) {
  285. m66592->num_dma++;
  286. ep->use_dma = 1;
  287. ep->fifoaddr = M66592_D0FIFO;
  288. ep->fifosel = M66592_D0FIFOSEL;
  289. ep->fifoctr = M66592_D0FIFOCTR;
  290. ep->fifotrn = M66592_D0FIFOTRN;
  291. } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
  292. m66592->num_dma++;
  293. ep->use_dma = 1;
  294. ep->fifoaddr = M66592_D1FIFO;
  295. ep->fifosel = M66592_D1FIFOSEL;
  296. ep->fifoctr = M66592_D1FIFOCTR;
  297. ep->fifotrn = M66592_D1FIFOTRN;
  298. } else {
  299. ep->use_dma = 0;
  300. ep->fifoaddr = M66592_CFIFO;
  301. ep->fifosel = M66592_CFIFOSEL;
  302. ep->fifoctr = M66592_CFIFOCTR;
  303. ep->fifotrn = 0;
  304. }
  305. } else {
  306. ep->use_dma = 0;
  307. ep->fifoaddr = M66592_CFIFO;
  308. ep->fifosel = M66592_CFIFOSEL;
  309. ep->fifoctr = M66592_CFIFOCTR;
  310. ep->fifotrn = 0;
  311. }
  312. ep->pipectr = get_pipectr_addr(pipenum);
  313. ep->pipenum = pipenum;
  314. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  315. m66592->pipenum2ep[pipenum] = ep;
  316. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  317. INIT_LIST_HEAD(&ep->queue);
  318. }
  319. static void m66592_ep_release(struct m66592_ep *ep)
  320. {
  321. struct m66592 *m66592 = ep->m66592;
  322. u16 pipenum = ep->pipenum;
  323. if (pipenum == 0)
  324. return;
  325. if (ep->use_dma)
  326. m66592->num_dma--;
  327. ep->pipenum = 0;
  328. ep->busy = 0;
  329. ep->use_dma = 0;
  330. }
  331. static int alloc_pipe_config(struct m66592_ep *ep,
  332. const struct usb_endpoint_descriptor *desc)
  333. {
  334. struct m66592 *m66592 = ep->m66592;
  335. struct m66592_pipe_info info;
  336. int dma = 0;
  337. int *counter;
  338. int ret;
  339. ep->desc = desc;
  340. BUG_ON(ep->pipenum);
  341. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  342. case USB_ENDPOINT_XFER_BULK:
  343. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  344. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  345. pr_err("bulk pipe is insufficient\n");
  346. return -ENODEV;
  347. } else {
  348. info.pipe = M66592_BASE_PIPENUM_ISOC
  349. + m66592->isochronous;
  350. counter = &m66592->isochronous;
  351. }
  352. } else {
  353. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  354. counter = &m66592->bulk;
  355. }
  356. info.type = M66592_BULK;
  357. dma = 1;
  358. break;
  359. case USB_ENDPOINT_XFER_INT:
  360. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  361. pr_err("interrupt pipe is insufficient\n");
  362. return -ENODEV;
  363. }
  364. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  365. info.type = M66592_INT;
  366. counter = &m66592->interrupt;
  367. break;
  368. case USB_ENDPOINT_XFER_ISOC:
  369. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  370. pr_err("isochronous pipe is insufficient\n");
  371. return -ENODEV;
  372. }
  373. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  374. info.type = M66592_ISO;
  375. counter = &m66592->isochronous;
  376. break;
  377. default:
  378. pr_err("unexpect xfer type\n");
  379. return -EINVAL;
  380. }
  381. ep->type = info.type;
  382. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  383. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  384. info.interval = desc->bInterval;
  385. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  386. info.dir_in = 1;
  387. else
  388. info.dir_in = 0;
  389. ret = pipe_buffer_setting(m66592, &info);
  390. if (ret < 0) {
  391. pr_err("pipe_buffer_setting fail\n");
  392. return ret;
  393. }
  394. (*counter)++;
  395. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  396. m66592->bulk++;
  397. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  398. pipe_initialize(ep);
  399. return 0;
  400. }
  401. static int free_pipe_config(struct m66592_ep *ep)
  402. {
  403. struct m66592 *m66592 = ep->m66592;
  404. struct m66592_pipe_info info;
  405. info.pipe = ep->pipenum;
  406. info.type = ep->type;
  407. pipe_buffer_release(m66592, &info);
  408. m66592_ep_release(ep);
  409. return 0;
  410. }
  411. /*-------------------------------------------------------------------------*/
  412. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  413. {
  414. enable_irq_ready(m66592, pipenum);
  415. enable_irq_nrdy(m66592, pipenum);
  416. }
  417. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  418. {
  419. disable_irq_ready(m66592, pipenum);
  420. disable_irq_nrdy(m66592, pipenum);
  421. }
  422. /* if complete is true, gadget driver complete function is not call */
  423. static void control_end(struct m66592 *m66592, unsigned ccpl)
  424. {
  425. m66592->ep[0].internal_ccpl = ccpl;
  426. pipe_start(m66592, 0);
  427. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  428. }
  429. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  430. {
  431. struct m66592 *m66592 = ep->m66592;
  432. pipe_change(m66592, ep->pipenum);
  433. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  434. (M66592_ISEL | M66592_CURPIPE),
  435. M66592_CFIFOSEL);
  436. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  437. if (req->req.length == 0) {
  438. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  439. pipe_start(m66592, 0);
  440. transfer_complete(ep, req, 0);
  441. } else {
  442. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  443. irq_ep0_write(ep, req);
  444. }
  445. }
  446. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  447. {
  448. struct m66592 *m66592 = ep->m66592;
  449. u16 tmp;
  450. pipe_change(m66592, ep->pipenum);
  451. disable_irq_empty(m66592, ep->pipenum);
  452. pipe_start(m66592, ep->pipenum);
  453. tmp = m66592_read(m66592, ep->fifoctr);
  454. if (unlikely((tmp & M66592_FRDY) == 0))
  455. pipe_irq_enable(m66592, ep->pipenum);
  456. else
  457. irq_packet_write(ep, req);
  458. }
  459. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  460. {
  461. struct m66592 *m66592 = ep->m66592;
  462. u16 pipenum = ep->pipenum;
  463. if (ep->pipenum == 0) {
  464. m66592_mdfy(m66592, M66592_PIPE0,
  465. (M66592_ISEL | M66592_CURPIPE),
  466. M66592_CFIFOSEL);
  467. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  468. pipe_start(m66592, pipenum);
  469. pipe_irq_enable(m66592, pipenum);
  470. } else {
  471. if (ep->use_dma) {
  472. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  473. pipe_change(m66592, pipenum);
  474. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  475. m66592_write(m66592,
  476. (req->req.length + ep->ep.maxpacket - 1)
  477. / ep->ep.maxpacket,
  478. ep->fifotrn);
  479. }
  480. pipe_start(m66592, pipenum); /* trigger once */
  481. pipe_irq_enable(m66592, pipenum);
  482. }
  483. }
  484. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  485. {
  486. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  487. start_packet_write(ep, req);
  488. else
  489. start_packet_read(ep, req);
  490. }
  491. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  492. {
  493. u16 ctsq;
  494. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  495. switch (ctsq) {
  496. case M66592_CS_RDDS:
  497. start_ep0_write(ep, req);
  498. break;
  499. case M66592_CS_WRDS:
  500. start_packet_read(ep, req);
  501. break;
  502. case M66592_CS_WRND:
  503. control_end(ep->m66592, 0);
  504. break;
  505. default:
  506. pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
  507. break;
  508. }
  509. }
  510. static void init_controller(struct m66592 *m66592)
  511. {
  512. unsigned int endian;
  513. if (m66592->pdata->on_chip) {
  514. if (m66592->pdata->endian)
  515. endian = 0; /* big endian */
  516. else
  517. endian = M66592_LITTLE; /* little endian */
  518. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  519. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  520. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  521. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  522. /* This is a workaound for SH7722 2nd cut */
  523. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  524. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  525. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  526. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  527. m66592_write(m66592, 0, M66592_CFBCFG);
  528. m66592_write(m66592, 0, M66592_D0FBCFG);
  529. m66592_bset(m66592, endian, M66592_CFBCFG);
  530. m66592_bset(m66592, endian, M66592_D0FBCFG);
  531. } else {
  532. unsigned int clock, vif, irq_sense;
  533. if (m66592->pdata->endian)
  534. endian = M66592_BIGEND; /* big endian */
  535. else
  536. endian = 0; /* little endian */
  537. if (m66592->pdata->vif)
  538. vif = M66592_LDRV; /* 3.3v */
  539. else
  540. vif = 0; /* 1.5v */
  541. switch (m66592->pdata->xtal) {
  542. case M66592_PLATDATA_XTAL_12MHZ:
  543. clock = M66592_XTAL12;
  544. break;
  545. case M66592_PLATDATA_XTAL_24MHZ:
  546. clock = M66592_XTAL24;
  547. break;
  548. case M66592_PLATDATA_XTAL_48MHZ:
  549. clock = M66592_XTAL48;
  550. break;
  551. default:
  552. pr_warning("m66592-udc: xtal configuration error\n");
  553. clock = 0;
  554. }
  555. switch (m66592->irq_trigger) {
  556. case IRQF_TRIGGER_LOW:
  557. irq_sense = M66592_INTL;
  558. break;
  559. case IRQF_TRIGGER_FALLING:
  560. irq_sense = 0;
  561. break;
  562. default:
  563. pr_warning("m66592-udc: irq trigger config error\n");
  564. irq_sense = 0;
  565. }
  566. m66592_bset(m66592,
  567. (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  568. M66592_PINCFG);
  569. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  570. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
  571. M66592_SYSCFG);
  572. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  573. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  574. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  575. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  576. msleep(3);
  577. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  578. msleep(1);
  579. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  580. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  581. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  582. M66592_DMA0CFG);
  583. }
  584. }
  585. static void disable_controller(struct m66592 *m66592)
  586. {
  587. if (!m66592->pdata->on_chip) {
  588. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  589. udelay(1);
  590. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  591. udelay(1);
  592. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  593. udelay(1);
  594. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  595. }
  596. }
  597. static void m66592_start_xclock(struct m66592 *m66592)
  598. {
  599. u16 tmp;
  600. if (!m66592->pdata->on_chip) {
  601. tmp = m66592_read(m66592, M66592_SYSCFG);
  602. if (!(tmp & M66592_XCKE))
  603. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  604. }
  605. }
  606. /*-------------------------------------------------------------------------*/
  607. static void transfer_complete(struct m66592_ep *ep,
  608. struct m66592_request *req, int status)
  609. __releases(m66592->lock)
  610. __acquires(m66592->lock)
  611. {
  612. int restart = 0;
  613. if (unlikely(ep->pipenum == 0)) {
  614. if (ep->internal_ccpl) {
  615. ep->internal_ccpl = 0;
  616. return;
  617. }
  618. }
  619. list_del_init(&req->queue);
  620. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  621. req->req.status = -ESHUTDOWN;
  622. else
  623. req->req.status = status;
  624. if (!list_empty(&ep->queue))
  625. restart = 1;
  626. spin_unlock(&ep->m66592->lock);
  627. req->req.complete(&ep->ep, &req->req);
  628. spin_lock(&ep->m66592->lock);
  629. if (restart) {
  630. req = list_entry(ep->queue.next, struct m66592_request, queue);
  631. if (ep->desc)
  632. start_packet(ep, req);
  633. }
  634. }
  635. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  636. {
  637. int i;
  638. u16 tmp;
  639. unsigned bufsize;
  640. size_t size;
  641. void *buf;
  642. u16 pipenum = ep->pipenum;
  643. struct m66592 *m66592 = ep->m66592;
  644. pipe_change(m66592, pipenum);
  645. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  646. i = 0;
  647. do {
  648. tmp = m66592_read(m66592, ep->fifoctr);
  649. if (i++ > 100000) {
  650. pr_err("pipe0 is busy. maybe cpu i/o bus "
  651. "conflict. please power off this controller.");
  652. return;
  653. }
  654. ndelay(1);
  655. } while ((tmp & M66592_FRDY) == 0);
  656. /* prepare parameters */
  657. bufsize = get_buffer_size(m66592, pipenum);
  658. buf = req->req.buf + req->req.actual;
  659. size = min(bufsize, req->req.length - req->req.actual);
  660. /* write fifo */
  661. if (req->req.buf) {
  662. if (size > 0)
  663. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  664. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  665. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  666. }
  667. /* update parameters */
  668. req->req.actual += size;
  669. /* check transfer finish */
  670. if ((!req->req.zero && (req->req.actual == req->req.length))
  671. || (size % ep->ep.maxpacket)
  672. || (size == 0)) {
  673. disable_irq_ready(m66592, pipenum);
  674. disable_irq_empty(m66592, pipenum);
  675. } else {
  676. disable_irq_ready(m66592, pipenum);
  677. enable_irq_empty(m66592, pipenum);
  678. }
  679. pipe_start(m66592, pipenum);
  680. }
  681. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  682. {
  683. u16 tmp;
  684. unsigned bufsize;
  685. size_t size;
  686. void *buf;
  687. u16 pipenum = ep->pipenum;
  688. struct m66592 *m66592 = ep->m66592;
  689. pipe_change(m66592, pipenum);
  690. tmp = m66592_read(m66592, ep->fifoctr);
  691. if (unlikely((tmp & M66592_FRDY) == 0)) {
  692. pipe_stop(m66592, pipenum);
  693. pipe_irq_disable(m66592, pipenum);
  694. pr_err("write fifo not ready. pipnum=%d\n", pipenum);
  695. return;
  696. }
  697. /* prepare parameters */
  698. bufsize = get_buffer_size(m66592, pipenum);
  699. buf = req->req.buf + req->req.actual;
  700. size = min(bufsize, req->req.length - req->req.actual);
  701. /* write fifo */
  702. if (req->req.buf) {
  703. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  704. if ((size == 0)
  705. || ((size % ep->ep.maxpacket) != 0)
  706. || ((bufsize != ep->ep.maxpacket)
  707. && (bufsize > size)))
  708. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  709. }
  710. /* update parameters */
  711. req->req.actual += size;
  712. /* check transfer finish */
  713. if ((!req->req.zero && (req->req.actual == req->req.length))
  714. || (size % ep->ep.maxpacket)
  715. || (size == 0)) {
  716. disable_irq_ready(m66592, pipenum);
  717. enable_irq_empty(m66592, pipenum);
  718. } else {
  719. disable_irq_empty(m66592, pipenum);
  720. pipe_irq_enable(m66592, pipenum);
  721. }
  722. }
  723. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  724. {
  725. u16 tmp;
  726. int rcv_len, bufsize, req_len;
  727. int size;
  728. void *buf;
  729. u16 pipenum = ep->pipenum;
  730. struct m66592 *m66592 = ep->m66592;
  731. int finish = 0;
  732. pipe_change(m66592, pipenum);
  733. tmp = m66592_read(m66592, ep->fifoctr);
  734. if (unlikely((tmp & M66592_FRDY) == 0)) {
  735. req->req.status = -EPIPE;
  736. pipe_stop(m66592, pipenum);
  737. pipe_irq_disable(m66592, pipenum);
  738. pr_err("read fifo not ready");
  739. return;
  740. }
  741. /* prepare parameters */
  742. rcv_len = tmp & M66592_DTLN;
  743. bufsize = get_buffer_size(m66592, pipenum);
  744. buf = req->req.buf + req->req.actual;
  745. req_len = req->req.length - req->req.actual;
  746. if (rcv_len < bufsize)
  747. size = min(rcv_len, req_len);
  748. else
  749. size = min(bufsize, req_len);
  750. /* update parameters */
  751. req->req.actual += size;
  752. /* check transfer finish */
  753. if ((!req->req.zero && (req->req.actual == req->req.length))
  754. || (size % ep->ep.maxpacket)
  755. || (size == 0)) {
  756. pipe_stop(m66592, pipenum);
  757. pipe_irq_disable(m66592, pipenum);
  758. finish = 1;
  759. }
  760. /* read fifo */
  761. if (req->req.buf) {
  762. if (size == 0)
  763. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  764. else
  765. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  766. }
  767. if ((ep->pipenum != 0) && finish)
  768. transfer_complete(ep, req, 0);
  769. }
  770. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  771. {
  772. u16 check;
  773. u16 pipenum;
  774. struct m66592_ep *ep;
  775. struct m66592_request *req;
  776. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  777. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  778. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  779. M66592_CFIFOSEL);
  780. ep = &m66592->ep[0];
  781. req = list_entry(ep->queue.next, struct m66592_request, queue);
  782. irq_packet_read(ep, req);
  783. } else {
  784. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  785. check = 1 << pipenum;
  786. if ((status & check) && (enb & check)) {
  787. m66592_write(m66592, ~check, M66592_BRDYSTS);
  788. ep = m66592->pipenum2ep[pipenum];
  789. req = list_entry(ep->queue.next,
  790. struct m66592_request, queue);
  791. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  792. irq_packet_write(ep, req);
  793. else
  794. irq_packet_read(ep, req);
  795. }
  796. }
  797. }
  798. }
  799. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  800. {
  801. u16 tmp;
  802. u16 check;
  803. u16 pipenum;
  804. struct m66592_ep *ep;
  805. struct m66592_request *req;
  806. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  807. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  808. ep = &m66592->ep[0];
  809. req = list_entry(ep->queue.next, struct m66592_request, queue);
  810. irq_ep0_write(ep, req);
  811. } else {
  812. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  813. check = 1 << pipenum;
  814. if ((status & check) && (enb & check)) {
  815. m66592_write(m66592, ~check, M66592_BEMPSTS);
  816. tmp = control_reg_get(m66592, pipenum);
  817. if ((tmp & M66592_INBUFM) == 0) {
  818. disable_irq_empty(m66592, pipenum);
  819. pipe_irq_disable(m66592, pipenum);
  820. pipe_stop(m66592, pipenum);
  821. ep = m66592->pipenum2ep[pipenum];
  822. req = list_entry(ep->queue.next,
  823. struct m66592_request,
  824. queue);
  825. if (!list_empty(&ep->queue))
  826. transfer_complete(ep, req, 0);
  827. }
  828. }
  829. }
  830. }
  831. }
  832. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  833. __releases(m66592->lock)
  834. __acquires(m66592->lock)
  835. {
  836. struct m66592_ep *ep;
  837. u16 pid;
  838. u16 status = 0;
  839. u16 w_index = le16_to_cpu(ctrl->wIndex);
  840. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  841. case USB_RECIP_DEVICE:
  842. status = 1 << USB_DEVICE_SELF_POWERED;
  843. break;
  844. case USB_RECIP_INTERFACE:
  845. status = 0;
  846. break;
  847. case USB_RECIP_ENDPOINT:
  848. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  849. pid = control_reg_get_pid(m66592, ep->pipenum);
  850. if (pid == M66592_PID_STALL)
  851. status = 1 << USB_ENDPOINT_HALT;
  852. else
  853. status = 0;
  854. break;
  855. default:
  856. pipe_stall(m66592, 0);
  857. return; /* exit */
  858. }
  859. m66592->ep0_data = cpu_to_le16(status);
  860. m66592->ep0_req->buf = &m66592->ep0_data;
  861. m66592->ep0_req->length = 2;
  862. /* AV: what happens if we get called again before that gets through? */
  863. spin_unlock(&m66592->lock);
  864. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  865. spin_lock(&m66592->lock);
  866. }
  867. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  868. {
  869. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  870. case USB_RECIP_DEVICE:
  871. control_end(m66592, 1);
  872. break;
  873. case USB_RECIP_INTERFACE:
  874. control_end(m66592, 1);
  875. break;
  876. case USB_RECIP_ENDPOINT: {
  877. struct m66592_ep *ep;
  878. struct m66592_request *req;
  879. u16 w_index = le16_to_cpu(ctrl->wIndex);
  880. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  881. pipe_stop(m66592, ep->pipenum);
  882. control_reg_sqclr(m66592, ep->pipenum);
  883. control_end(m66592, 1);
  884. req = list_entry(ep->queue.next,
  885. struct m66592_request, queue);
  886. if (ep->busy) {
  887. ep->busy = 0;
  888. if (list_empty(&ep->queue))
  889. break;
  890. start_packet(ep, req);
  891. } else if (!list_empty(&ep->queue))
  892. pipe_start(m66592, ep->pipenum);
  893. }
  894. break;
  895. default:
  896. pipe_stall(m66592, 0);
  897. break;
  898. }
  899. }
  900. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  901. {
  902. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  903. case USB_RECIP_DEVICE:
  904. control_end(m66592, 1);
  905. break;
  906. case USB_RECIP_INTERFACE:
  907. control_end(m66592, 1);
  908. break;
  909. case USB_RECIP_ENDPOINT: {
  910. struct m66592_ep *ep;
  911. u16 w_index = le16_to_cpu(ctrl->wIndex);
  912. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  913. pipe_stall(m66592, ep->pipenum);
  914. control_end(m66592, 1);
  915. }
  916. break;
  917. default:
  918. pipe_stall(m66592, 0);
  919. break;
  920. }
  921. }
  922. /* if return value is true, call class driver's setup() */
  923. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  924. {
  925. u16 *p = (u16 *)ctrl;
  926. unsigned long offset = M66592_USBREQ;
  927. int i, ret = 0;
  928. /* read fifo */
  929. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  930. for (i = 0; i < 4; i++)
  931. p[i] = m66592_read(m66592, offset + i*2);
  932. /* check request */
  933. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  934. switch (ctrl->bRequest) {
  935. case USB_REQ_GET_STATUS:
  936. get_status(m66592, ctrl);
  937. break;
  938. case USB_REQ_CLEAR_FEATURE:
  939. clear_feature(m66592, ctrl);
  940. break;
  941. case USB_REQ_SET_FEATURE:
  942. set_feature(m66592, ctrl);
  943. break;
  944. default:
  945. ret = 1;
  946. break;
  947. }
  948. } else
  949. ret = 1;
  950. return ret;
  951. }
  952. static void m66592_update_usb_speed(struct m66592 *m66592)
  953. {
  954. u16 speed = get_usb_speed(m66592);
  955. switch (speed) {
  956. case M66592_HSMODE:
  957. m66592->gadget.speed = USB_SPEED_HIGH;
  958. break;
  959. case M66592_FSMODE:
  960. m66592->gadget.speed = USB_SPEED_FULL;
  961. break;
  962. default:
  963. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  964. pr_err("USB speed unknown\n");
  965. }
  966. }
  967. static void irq_device_state(struct m66592 *m66592)
  968. {
  969. u16 dvsq;
  970. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  971. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  972. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  973. m66592->driver->disconnect(&m66592->gadget);
  974. m66592_update_usb_speed(m66592);
  975. }
  976. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  977. m66592_update_usb_speed(m66592);
  978. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  979. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  980. m66592_update_usb_speed(m66592);
  981. m66592->old_dvsq = dvsq;
  982. }
  983. static void irq_control_stage(struct m66592 *m66592)
  984. __releases(m66592->lock)
  985. __acquires(m66592->lock)
  986. {
  987. struct usb_ctrlrequest ctrl;
  988. u16 ctsq;
  989. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  990. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  991. switch (ctsq) {
  992. case M66592_CS_IDST: {
  993. struct m66592_ep *ep;
  994. struct m66592_request *req;
  995. ep = &m66592->ep[0];
  996. req = list_entry(ep->queue.next, struct m66592_request, queue);
  997. transfer_complete(ep, req, 0);
  998. }
  999. break;
  1000. case M66592_CS_RDDS:
  1001. case M66592_CS_WRDS:
  1002. case M66592_CS_WRND:
  1003. if (setup_packet(m66592, &ctrl)) {
  1004. spin_unlock(&m66592->lock);
  1005. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  1006. pipe_stall(m66592, 0);
  1007. spin_lock(&m66592->lock);
  1008. }
  1009. break;
  1010. case M66592_CS_RDSS:
  1011. case M66592_CS_WRSS:
  1012. control_end(m66592, 0);
  1013. break;
  1014. default:
  1015. pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1016. break;
  1017. }
  1018. }
  1019. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1020. {
  1021. struct m66592 *m66592 = _m66592;
  1022. u16 intsts0;
  1023. u16 intenb0;
  1024. u16 brdysts, nrdysts, bempsts;
  1025. u16 brdyenb, nrdyenb, bempenb;
  1026. u16 savepipe;
  1027. u16 mask0;
  1028. spin_lock(&m66592->lock);
  1029. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1030. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1031. if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
  1032. /*
  1033. * When USB clock stops, it cannot read register. Even if a
  1034. * clock stops, the interrupt occurs. So this driver turn on
  1035. * a clock by this timing and do re-reading of register.
  1036. */
  1037. m66592_start_xclock(m66592);
  1038. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1039. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1040. }
  1041. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1042. mask0 = intsts0 & intenb0;
  1043. if (mask0) {
  1044. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1045. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  1046. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1047. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1048. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  1049. bempenb = m66592_read(m66592, M66592_BEMPENB);
  1050. if (mask0 & M66592_VBINT) {
  1051. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1052. M66592_INTSTS0);
  1053. m66592_start_xclock(m66592);
  1054. /* start vbus sampling */
  1055. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1056. & M66592_VBSTS;
  1057. m66592->scount = M66592_MAX_SAMPLING;
  1058. mod_timer(&m66592->timer,
  1059. jiffies + msecs_to_jiffies(50));
  1060. }
  1061. if (intsts0 & M66592_DVSQ)
  1062. irq_device_state(m66592);
  1063. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1064. && (brdysts & brdyenb)) {
  1065. irq_pipe_ready(m66592, brdysts, brdyenb);
  1066. }
  1067. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1068. && (bempsts & bempenb)) {
  1069. irq_pipe_empty(m66592, bempsts, bempenb);
  1070. }
  1071. if (intsts0 & M66592_CTRT)
  1072. irq_control_stage(m66592);
  1073. }
  1074. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1075. spin_unlock(&m66592->lock);
  1076. return IRQ_HANDLED;
  1077. }
  1078. static void m66592_timer(unsigned long _m66592)
  1079. {
  1080. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1081. unsigned long flags;
  1082. u16 tmp;
  1083. spin_lock_irqsave(&m66592->lock, flags);
  1084. tmp = m66592_read(m66592, M66592_SYSCFG);
  1085. if (!(tmp & M66592_RCKE)) {
  1086. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1087. udelay(10);
  1088. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1089. }
  1090. if (m66592->scount > 0) {
  1091. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1092. if (tmp == m66592->old_vbus) {
  1093. m66592->scount--;
  1094. if (m66592->scount == 0) {
  1095. if (tmp == M66592_VBSTS)
  1096. m66592_usb_connect(m66592);
  1097. else
  1098. m66592_usb_disconnect(m66592);
  1099. } else {
  1100. mod_timer(&m66592->timer,
  1101. jiffies + msecs_to_jiffies(50));
  1102. }
  1103. } else {
  1104. m66592->scount = M66592_MAX_SAMPLING;
  1105. m66592->old_vbus = tmp;
  1106. mod_timer(&m66592->timer,
  1107. jiffies + msecs_to_jiffies(50));
  1108. }
  1109. }
  1110. spin_unlock_irqrestore(&m66592->lock, flags);
  1111. }
  1112. /*-------------------------------------------------------------------------*/
  1113. static int m66592_enable(struct usb_ep *_ep,
  1114. const struct usb_endpoint_descriptor *desc)
  1115. {
  1116. struct m66592_ep *ep;
  1117. ep = container_of(_ep, struct m66592_ep, ep);
  1118. return alloc_pipe_config(ep, desc);
  1119. }
  1120. static int m66592_disable(struct usb_ep *_ep)
  1121. {
  1122. struct m66592_ep *ep;
  1123. struct m66592_request *req;
  1124. unsigned long flags;
  1125. ep = container_of(_ep, struct m66592_ep, ep);
  1126. BUG_ON(!ep);
  1127. while (!list_empty(&ep->queue)) {
  1128. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1129. spin_lock_irqsave(&ep->m66592->lock, flags);
  1130. transfer_complete(ep, req, -ECONNRESET);
  1131. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1132. }
  1133. pipe_irq_disable(ep->m66592, ep->pipenum);
  1134. return free_pipe_config(ep);
  1135. }
  1136. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1137. gfp_t gfp_flags)
  1138. {
  1139. struct m66592_request *req;
  1140. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1141. if (!req)
  1142. return NULL;
  1143. INIT_LIST_HEAD(&req->queue);
  1144. return &req->req;
  1145. }
  1146. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1147. {
  1148. struct m66592_request *req;
  1149. req = container_of(_req, struct m66592_request, req);
  1150. kfree(req);
  1151. }
  1152. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1153. gfp_t gfp_flags)
  1154. {
  1155. struct m66592_ep *ep;
  1156. struct m66592_request *req;
  1157. unsigned long flags;
  1158. int request = 0;
  1159. ep = container_of(_ep, struct m66592_ep, ep);
  1160. req = container_of(_req, struct m66592_request, req);
  1161. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1162. return -ESHUTDOWN;
  1163. spin_lock_irqsave(&ep->m66592->lock, flags);
  1164. if (list_empty(&ep->queue))
  1165. request = 1;
  1166. list_add_tail(&req->queue, &ep->queue);
  1167. req->req.actual = 0;
  1168. req->req.status = -EINPROGRESS;
  1169. if (ep->desc == NULL) /* control */
  1170. start_ep0(ep, req);
  1171. else {
  1172. if (request && !ep->busy)
  1173. start_packet(ep, req);
  1174. }
  1175. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1176. return 0;
  1177. }
  1178. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1179. {
  1180. struct m66592_ep *ep;
  1181. struct m66592_request *req;
  1182. unsigned long flags;
  1183. ep = container_of(_ep, struct m66592_ep, ep);
  1184. req = container_of(_req, struct m66592_request, req);
  1185. spin_lock_irqsave(&ep->m66592->lock, flags);
  1186. if (!list_empty(&ep->queue))
  1187. transfer_complete(ep, req, -ECONNRESET);
  1188. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1189. return 0;
  1190. }
  1191. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1192. {
  1193. struct m66592_ep *ep;
  1194. struct m66592_request *req;
  1195. unsigned long flags;
  1196. int ret = 0;
  1197. ep = container_of(_ep, struct m66592_ep, ep);
  1198. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1199. spin_lock_irqsave(&ep->m66592->lock, flags);
  1200. if (!list_empty(&ep->queue)) {
  1201. ret = -EAGAIN;
  1202. goto out;
  1203. }
  1204. if (value) {
  1205. ep->busy = 1;
  1206. pipe_stall(ep->m66592, ep->pipenum);
  1207. } else {
  1208. ep->busy = 0;
  1209. pipe_stop(ep->m66592, ep->pipenum);
  1210. }
  1211. out:
  1212. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1213. return ret;
  1214. }
  1215. static void m66592_fifo_flush(struct usb_ep *_ep)
  1216. {
  1217. struct m66592_ep *ep;
  1218. unsigned long flags;
  1219. ep = container_of(_ep, struct m66592_ep, ep);
  1220. spin_lock_irqsave(&ep->m66592->lock, flags);
  1221. if (list_empty(&ep->queue) && !ep->busy) {
  1222. pipe_stop(ep->m66592, ep->pipenum);
  1223. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1224. }
  1225. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1226. }
  1227. static struct usb_ep_ops m66592_ep_ops = {
  1228. .enable = m66592_enable,
  1229. .disable = m66592_disable,
  1230. .alloc_request = m66592_alloc_request,
  1231. .free_request = m66592_free_request,
  1232. .queue = m66592_queue,
  1233. .dequeue = m66592_dequeue,
  1234. .set_halt = m66592_set_halt,
  1235. .fifo_flush = m66592_fifo_flush,
  1236. };
  1237. /*-------------------------------------------------------------------------*/
  1238. static struct m66592 *the_controller;
  1239. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1240. {
  1241. struct m66592 *m66592 = the_controller;
  1242. int retval;
  1243. if (!driver
  1244. || driver->speed != USB_SPEED_HIGH
  1245. || !driver->bind
  1246. || !driver->setup)
  1247. return -EINVAL;
  1248. if (!m66592)
  1249. return -ENODEV;
  1250. if (m66592->driver)
  1251. return -EBUSY;
  1252. /* hook up the driver */
  1253. driver->driver.bus = NULL;
  1254. m66592->driver = driver;
  1255. m66592->gadget.dev.driver = &driver->driver;
  1256. retval = device_add(&m66592->gadget.dev);
  1257. if (retval) {
  1258. pr_err("device_add error (%d)\n", retval);
  1259. goto error;
  1260. }
  1261. retval = driver->bind (&m66592->gadget);
  1262. if (retval) {
  1263. pr_err("bind to driver error (%d)\n", retval);
  1264. device_del(&m66592->gadget.dev);
  1265. goto error;
  1266. }
  1267. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1268. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1269. m66592_start_xclock(m66592);
  1270. /* start vbus sampling */
  1271. m66592->old_vbus = m66592_read(m66592,
  1272. M66592_INTSTS0) & M66592_VBSTS;
  1273. m66592->scount = M66592_MAX_SAMPLING;
  1274. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1275. }
  1276. return 0;
  1277. error:
  1278. m66592->driver = NULL;
  1279. m66592->gadget.dev.driver = NULL;
  1280. return retval;
  1281. }
  1282. EXPORT_SYMBOL(usb_gadget_register_driver);
  1283. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1284. {
  1285. struct m66592 *m66592 = the_controller;
  1286. unsigned long flags;
  1287. if (driver != m66592->driver || !driver->unbind)
  1288. return -EINVAL;
  1289. spin_lock_irqsave(&m66592->lock, flags);
  1290. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1291. m66592_usb_disconnect(m66592);
  1292. spin_unlock_irqrestore(&m66592->lock, flags);
  1293. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1294. driver->unbind(&m66592->gadget);
  1295. m66592->gadget.dev.driver = NULL;
  1296. init_controller(m66592);
  1297. disable_controller(m66592);
  1298. device_del(&m66592->gadget.dev);
  1299. m66592->driver = NULL;
  1300. return 0;
  1301. }
  1302. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1303. /*-------------------------------------------------------------------------*/
  1304. static int m66592_get_frame(struct usb_gadget *_gadget)
  1305. {
  1306. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1307. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1308. }
  1309. static struct usb_gadget_ops m66592_gadget_ops = {
  1310. .get_frame = m66592_get_frame,
  1311. };
  1312. static int __exit m66592_remove(struct platform_device *pdev)
  1313. {
  1314. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1315. del_timer_sync(&m66592->timer);
  1316. iounmap(m66592->reg);
  1317. free_irq(platform_get_irq(pdev, 0), m66592);
  1318. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1319. #ifdef CONFIG_HAVE_CLK
  1320. if (m66592->pdata->on_chip) {
  1321. clk_disable(m66592->clk);
  1322. clk_put(m66592->clk);
  1323. }
  1324. #endif
  1325. kfree(m66592);
  1326. return 0;
  1327. }
  1328. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1329. {
  1330. }
  1331. static int __init m66592_probe(struct platform_device *pdev)
  1332. {
  1333. struct resource *res, *ires;
  1334. void __iomem *reg = NULL;
  1335. struct m66592 *m66592 = NULL;
  1336. #ifdef CONFIG_HAVE_CLK
  1337. char clk_name[8];
  1338. #endif
  1339. int ret = 0;
  1340. int i;
  1341. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1342. if (!res) {
  1343. ret = -ENODEV;
  1344. pr_err("platform_get_resource error.\n");
  1345. goto clean_up;
  1346. }
  1347. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1348. if (!ires) {
  1349. ret = -ENODEV;
  1350. dev_err(&pdev->dev,
  1351. "platform_get_resource IORESOURCE_IRQ error.\n");
  1352. goto clean_up;
  1353. }
  1354. reg = ioremap(res->start, resource_size(res));
  1355. if (reg == NULL) {
  1356. ret = -ENOMEM;
  1357. pr_err("ioremap error.\n");
  1358. goto clean_up;
  1359. }
  1360. if (pdev->dev.platform_data == NULL) {
  1361. dev_err(&pdev->dev, "no platform data\n");
  1362. ret = -ENODEV;
  1363. goto clean_up;
  1364. }
  1365. /* initialize ucd */
  1366. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1367. if (m66592 == NULL) {
  1368. pr_err("kzalloc error\n");
  1369. goto clean_up;
  1370. }
  1371. m66592->pdata = pdev->dev.platform_data;
  1372. m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1373. spin_lock_init(&m66592->lock);
  1374. dev_set_drvdata(&pdev->dev, m66592);
  1375. m66592->gadget.ops = &m66592_gadget_ops;
  1376. device_initialize(&m66592->gadget.dev);
  1377. dev_set_name(&m66592->gadget.dev, "gadget");
  1378. m66592->gadget.is_dualspeed = 1;
  1379. m66592->gadget.dev.parent = &pdev->dev;
  1380. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1381. m66592->gadget.dev.release = pdev->dev.release;
  1382. m66592->gadget.name = udc_name;
  1383. init_timer(&m66592->timer);
  1384. m66592->timer.function = m66592_timer;
  1385. m66592->timer.data = (unsigned long)m66592;
  1386. m66592->reg = reg;
  1387. ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1388. udc_name, m66592);
  1389. if (ret < 0) {
  1390. pr_err("request_irq error (%d)\n", ret);
  1391. goto clean_up;
  1392. }
  1393. #ifdef CONFIG_HAVE_CLK
  1394. if (m66592->pdata->on_chip) {
  1395. snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
  1396. m66592->clk = clk_get(&pdev->dev, clk_name);
  1397. if (IS_ERR(m66592->clk)) {
  1398. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1399. clk_name);
  1400. ret = PTR_ERR(m66592->clk);
  1401. goto clean_up2;
  1402. }
  1403. clk_enable(m66592->clk);
  1404. }
  1405. #endif
  1406. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1407. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1408. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1409. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1410. struct m66592_ep *ep = &m66592->ep[i];
  1411. if (i != 0) {
  1412. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1413. list_add_tail(&m66592->ep[i].ep.ep_list,
  1414. &m66592->gadget.ep_list);
  1415. }
  1416. ep->m66592 = m66592;
  1417. INIT_LIST_HEAD(&ep->queue);
  1418. ep->ep.name = m66592_ep_name[i];
  1419. ep->ep.ops = &m66592_ep_ops;
  1420. ep->ep.maxpacket = 512;
  1421. }
  1422. m66592->ep[0].ep.maxpacket = 64;
  1423. m66592->ep[0].pipenum = 0;
  1424. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1425. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1426. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1427. m66592->ep[0].fifotrn = 0;
  1428. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1429. m66592->pipenum2ep[0] = &m66592->ep[0];
  1430. m66592->epaddr2ep[0] = &m66592->ep[0];
  1431. the_controller = m66592;
  1432. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1433. if (m66592->ep0_req == NULL)
  1434. goto clean_up3;
  1435. m66592->ep0_req->complete = nop_completion;
  1436. init_controller(m66592);
  1437. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1438. return 0;
  1439. clean_up3:
  1440. #ifdef CONFIG_HAVE_CLK
  1441. if (m66592->pdata->on_chip) {
  1442. clk_disable(m66592->clk);
  1443. clk_put(m66592->clk);
  1444. }
  1445. clean_up2:
  1446. #endif
  1447. free_irq(ires->start, m66592);
  1448. clean_up:
  1449. if (m66592) {
  1450. if (m66592->ep0_req)
  1451. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1452. kfree(m66592);
  1453. }
  1454. if (reg)
  1455. iounmap(reg);
  1456. return ret;
  1457. }
  1458. /*-------------------------------------------------------------------------*/
  1459. static struct platform_driver m66592_driver = {
  1460. .remove = __exit_p(m66592_remove),
  1461. .driver = {
  1462. .name = (char *) udc_name,
  1463. .owner = THIS_MODULE,
  1464. },
  1465. };
  1466. static int __init m66592_udc_init(void)
  1467. {
  1468. return platform_driver_probe(&m66592_driver, m66592_probe);
  1469. }
  1470. module_init(m66592_udc_init);
  1471. static void __exit m66592_udc_cleanup(void)
  1472. {
  1473. platform_driver_unregister(&m66592_driver);
  1474. }
  1475. module_exit(m66592_udc_cleanup);