sh-sci.c 32 KB

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  1. /*
  2. * drivers/serial/sh-sci.c
  3. *
  4. * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
  5. *
  6. * Copyright (C) 2002 - 2008 Paul Mundt
  7. * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
  8. *
  9. * based off of the old drivers/char/sh-sci.c by:
  10. *
  11. * Copyright (C) 1999, 2000 Niibe Yutaka
  12. * Copyright (C) 2000 Sugioka Toshinobu
  13. * Modified to support multiple serial ports. Stuart Menefy (May 2000).
  14. * Modified to support SecureEdge. David McCullough (2002)
  15. * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
  16. * Removed SH7300 support (Jul 2007).
  17. *
  18. * This file is subject to the terms and conditions of the GNU General Public
  19. * License. See the file "COPYING" in the main directory of this archive
  20. * for more details.
  21. */
  22. #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  23. #define SUPPORT_SYSRQ
  24. #endif
  25. #undef DEBUG
  26. #include <linux/module.h>
  27. #include <linux/errno.h>
  28. #include <linux/timer.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/tty.h>
  31. #include <linux/tty_flip.h>
  32. #include <linux/serial.h>
  33. #include <linux/major.h>
  34. #include <linux/string.h>
  35. #include <linux/sysrq.h>
  36. #include <linux/ioport.h>
  37. #include <linux/mm.h>
  38. #include <linux/init.h>
  39. #include <linux/delay.h>
  40. #include <linux/console.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/serial_sci.h>
  43. #include <linux/notifier.h>
  44. #include <linux/cpufreq.h>
  45. #include <linux/clk.h>
  46. #include <linux/ctype.h>
  47. #include <linux/err.h>
  48. #include <linux/list.h>
  49. #ifdef CONFIG_SUPERH
  50. #include <asm/sh_bios.h>
  51. #endif
  52. #ifdef CONFIG_H8300
  53. #include <asm/gpio.h>
  54. #endif
  55. #include "sh-sci.h"
  56. struct sci_port {
  57. struct uart_port port;
  58. /* Port type */
  59. unsigned int type;
  60. /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
  61. unsigned int irqs[SCIx_NR_IRQS];
  62. /* Port enable callback */
  63. void (*enable)(struct uart_port *port);
  64. /* Port disable callback */
  65. void (*disable)(struct uart_port *port);
  66. /* Break timer */
  67. struct timer_list break_timer;
  68. int break_flag;
  69. /* Interface clock */
  70. struct clk *iclk;
  71. /* Data clock */
  72. struct clk *dclk;
  73. struct list_head node;
  74. };
  75. struct sh_sci_priv {
  76. spinlock_t lock;
  77. struct list_head ports;
  78. struct notifier_block clk_nb;
  79. };
  80. /* Function prototypes */
  81. static void sci_stop_tx(struct uart_port *port);
  82. #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
  83. static struct sci_port sci_ports[SCI_NPORTS];
  84. static struct uart_driver sci_uart_driver;
  85. static inline struct sci_port *
  86. to_sci_port(struct uart_port *uart)
  87. {
  88. return container_of(uart, struct sci_port, port);
  89. }
  90. #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
  91. #ifdef CONFIG_CONSOLE_POLL
  92. static inline void handle_error(struct uart_port *port)
  93. {
  94. /* Clear error flags */
  95. sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  96. }
  97. static int sci_poll_get_char(struct uart_port *port)
  98. {
  99. unsigned short status;
  100. int c;
  101. do {
  102. status = sci_in(port, SCxSR);
  103. if (status & SCxSR_ERRORS(port)) {
  104. handle_error(port);
  105. continue;
  106. }
  107. } while (!(status & SCxSR_RDxF(port)));
  108. c = sci_in(port, SCxRDR);
  109. /* Dummy read */
  110. sci_in(port, SCxSR);
  111. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  112. return c;
  113. }
  114. #endif
  115. static void sci_poll_put_char(struct uart_port *port, unsigned char c)
  116. {
  117. unsigned short status;
  118. do {
  119. status = sci_in(port, SCxSR);
  120. } while (!(status & SCxSR_TDxE(port)));
  121. sci_out(port, SCxTDR, c);
  122. sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
  123. }
  124. #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
  125. #if defined(__H8300H__) || defined(__H8300S__)
  126. static void sci_init_pins(struct uart_port *port, unsigned int cflag)
  127. {
  128. int ch = (port->mapbase - SMR0) >> 3;
  129. /* set DDR regs */
  130. H8300_GPIO_DDR(h8300_sci_pins[ch].port,
  131. h8300_sci_pins[ch].rx,
  132. H8300_GPIO_INPUT);
  133. H8300_GPIO_DDR(h8300_sci_pins[ch].port,
  134. h8300_sci_pins[ch].tx,
  135. H8300_GPIO_OUTPUT);
  136. /* tx mark output*/
  137. H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
  138. }
  139. #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  140. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  141. {
  142. if (port->mapbase == 0xA4400000) {
  143. __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
  144. __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
  145. } else if (port->mapbase == 0xA4410000)
  146. __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
  147. }
  148. #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
  149. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  150. {
  151. unsigned short data;
  152. if (cflag & CRTSCTS) {
  153. /* enable RTS/CTS */
  154. if (port->mapbase == 0xa4430000) { /* SCIF0 */
  155. /* Clear PTCR bit 9-2; enable all scif pins but sck */
  156. data = __raw_readw(PORT_PTCR);
  157. __raw_writew((data & 0xfc03), PORT_PTCR);
  158. } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
  159. /* Clear PVCR bit 9-2 */
  160. data = __raw_readw(PORT_PVCR);
  161. __raw_writew((data & 0xfc03), PORT_PVCR);
  162. }
  163. } else {
  164. if (port->mapbase == 0xa4430000) { /* SCIF0 */
  165. /* Clear PTCR bit 5-2; enable only tx and rx */
  166. data = __raw_readw(PORT_PTCR);
  167. __raw_writew((data & 0xffc3), PORT_PTCR);
  168. } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
  169. /* Clear PVCR bit 5-2 */
  170. data = __raw_readw(PORT_PVCR);
  171. __raw_writew((data & 0xffc3), PORT_PVCR);
  172. }
  173. }
  174. }
  175. #elif defined(CONFIG_CPU_SH3)
  176. /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
  177. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  178. {
  179. unsigned short data;
  180. /* We need to set SCPCR to enable RTS/CTS */
  181. data = __raw_readw(SCPCR);
  182. /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
  183. __raw_writew(data & 0x0fcf, SCPCR);
  184. if (!(cflag & CRTSCTS)) {
  185. /* We need to set SCPCR to enable RTS/CTS */
  186. data = __raw_readw(SCPCR);
  187. /* Clear out SCP7MD1,0, SCP4MD1,0,
  188. Set SCP6MD1,0 = {01} (output) */
  189. __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
  190. data = ctrl_inb(SCPDR);
  191. /* Set /RTS2 (bit6) = 0 */
  192. ctrl_outb(data & 0xbf, SCPDR);
  193. }
  194. }
  195. #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  196. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  197. {
  198. unsigned short data;
  199. if (port->mapbase == 0xffe00000) {
  200. data = __raw_readw(PSCR);
  201. data &= ~0x03cf;
  202. if (!(cflag & CRTSCTS))
  203. data |= 0x0340;
  204. __raw_writew(data, PSCR);
  205. }
  206. }
  207. #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
  208. defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  209. defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  210. defined(CONFIG_CPU_SUBTYPE_SH7785) || \
  211. defined(CONFIG_CPU_SUBTYPE_SH7786) || \
  212. defined(CONFIG_CPU_SUBTYPE_SHX3)
  213. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  214. {
  215. if (!(cflag & CRTSCTS))
  216. __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
  217. }
  218. #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
  219. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  220. {
  221. if (!(cflag & CRTSCTS))
  222. __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
  223. }
  224. #else
  225. static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
  226. {
  227. /* Nothing to do */
  228. }
  229. #endif
  230. #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
  231. defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  232. defined(CONFIG_CPU_SUBTYPE_SH7785) || \
  233. defined(CONFIG_CPU_SUBTYPE_SH7786)
  234. static inline int scif_txroom(struct uart_port *port)
  235. {
  236. return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
  237. }
  238. static inline int scif_rxroom(struct uart_port *port)
  239. {
  240. return sci_in(port, SCRFDR) & 0xff;
  241. }
  242. #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
  243. static inline int scif_txroom(struct uart_port *port)
  244. {
  245. if ((port->mapbase == 0xffe00000) ||
  246. (port->mapbase == 0xffe08000)) {
  247. /* SCIF0/1*/
  248. return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
  249. } else {
  250. /* SCIF2 */
  251. return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
  252. }
  253. }
  254. static inline int scif_rxroom(struct uart_port *port)
  255. {
  256. if ((port->mapbase == 0xffe00000) ||
  257. (port->mapbase == 0xffe08000)) {
  258. /* SCIF0/1*/
  259. return sci_in(port, SCRFDR) & 0xff;
  260. } else {
  261. /* SCIF2 */
  262. return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
  263. }
  264. }
  265. #else
  266. static inline int scif_txroom(struct uart_port *port)
  267. {
  268. return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
  269. }
  270. static inline int scif_rxroom(struct uart_port *port)
  271. {
  272. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  273. }
  274. #endif
  275. static inline int sci_txroom(struct uart_port *port)
  276. {
  277. return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
  278. }
  279. static inline int sci_rxroom(struct uart_port *port)
  280. {
  281. return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
  282. }
  283. /* ********************************************************************** *
  284. * the interrupt related routines *
  285. * ********************************************************************** */
  286. static void sci_transmit_chars(struct uart_port *port)
  287. {
  288. struct circ_buf *xmit = &port->state->xmit;
  289. unsigned int stopped = uart_tx_stopped(port);
  290. unsigned short status;
  291. unsigned short ctrl;
  292. int count;
  293. status = sci_in(port, SCxSR);
  294. if (!(status & SCxSR_TDxE(port))) {
  295. ctrl = sci_in(port, SCSCR);
  296. if (uart_circ_empty(xmit))
  297. ctrl &= ~SCI_CTRL_FLAGS_TIE;
  298. else
  299. ctrl |= SCI_CTRL_FLAGS_TIE;
  300. sci_out(port, SCSCR, ctrl);
  301. return;
  302. }
  303. if (port->type == PORT_SCI)
  304. count = sci_txroom(port);
  305. else
  306. count = scif_txroom(port);
  307. do {
  308. unsigned char c;
  309. if (port->x_char) {
  310. c = port->x_char;
  311. port->x_char = 0;
  312. } else if (!uart_circ_empty(xmit) && !stopped) {
  313. c = xmit->buf[xmit->tail];
  314. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  315. } else {
  316. break;
  317. }
  318. sci_out(port, SCxTDR, c);
  319. port->icount.tx++;
  320. } while (--count > 0);
  321. sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
  322. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  323. uart_write_wakeup(port);
  324. if (uart_circ_empty(xmit)) {
  325. sci_stop_tx(port);
  326. } else {
  327. ctrl = sci_in(port, SCSCR);
  328. if (port->type != PORT_SCI) {
  329. sci_in(port, SCxSR); /* Dummy read */
  330. sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
  331. }
  332. ctrl |= SCI_CTRL_FLAGS_TIE;
  333. sci_out(port, SCSCR, ctrl);
  334. }
  335. }
  336. /* On SH3, SCIF may read end-of-break as a space->mark char */
  337. #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
  338. static inline void sci_receive_chars(struct uart_port *port)
  339. {
  340. struct sci_port *sci_port = to_sci_port(port);
  341. struct tty_struct *tty = port->state->port.tty;
  342. int i, count, copied = 0;
  343. unsigned short status;
  344. unsigned char flag;
  345. status = sci_in(port, SCxSR);
  346. if (!(status & SCxSR_RDxF(port)))
  347. return;
  348. while (1) {
  349. if (port->type == PORT_SCI)
  350. count = sci_rxroom(port);
  351. else
  352. count = scif_rxroom(port);
  353. /* Don't copy more bytes than there is room for in the buffer */
  354. count = tty_buffer_request_room(tty, count);
  355. /* If for any reason we can't copy more data, we're done! */
  356. if (count == 0)
  357. break;
  358. if (port->type == PORT_SCI) {
  359. char c = sci_in(port, SCxRDR);
  360. if (uart_handle_sysrq_char(port, c) ||
  361. sci_port->break_flag)
  362. count = 0;
  363. else
  364. tty_insert_flip_char(tty, c, TTY_NORMAL);
  365. } else {
  366. for (i = 0; i < count; i++) {
  367. char c = sci_in(port, SCxRDR);
  368. status = sci_in(port, SCxSR);
  369. #if defined(CONFIG_CPU_SH3)
  370. /* Skip "chars" during break */
  371. if (sci_port->break_flag) {
  372. if ((c == 0) &&
  373. (status & SCxSR_FER(port))) {
  374. count--; i--;
  375. continue;
  376. }
  377. /* Nonzero => end-of-break */
  378. dev_dbg(port->dev, "debounce<%02x>\n", c);
  379. sci_port->break_flag = 0;
  380. if (STEPFN(c)) {
  381. count--; i--;
  382. continue;
  383. }
  384. }
  385. #endif /* CONFIG_CPU_SH3 */
  386. if (uart_handle_sysrq_char(port, c)) {
  387. count--; i--;
  388. continue;
  389. }
  390. /* Store data and status */
  391. if (status&SCxSR_FER(port)) {
  392. flag = TTY_FRAME;
  393. dev_notice(port->dev, "frame error\n");
  394. } else if (status&SCxSR_PER(port)) {
  395. flag = TTY_PARITY;
  396. dev_notice(port->dev, "parity error\n");
  397. } else
  398. flag = TTY_NORMAL;
  399. tty_insert_flip_char(tty, c, flag);
  400. }
  401. }
  402. sci_in(port, SCxSR); /* dummy read */
  403. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  404. copied += count;
  405. port->icount.rx += count;
  406. }
  407. if (copied) {
  408. /* Tell the rest of the system the news. New characters! */
  409. tty_flip_buffer_push(tty);
  410. } else {
  411. sci_in(port, SCxSR); /* dummy read */
  412. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  413. }
  414. }
  415. #define SCI_BREAK_JIFFIES (HZ/20)
  416. /* The sci generates interrupts during the break,
  417. * 1 per millisecond or so during the break period, for 9600 baud.
  418. * So dont bother disabling interrupts.
  419. * But dont want more than 1 break event.
  420. * Use a kernel timer to periodically poll the rx line until
  421. * the break is finished.
  422. */
  423. static void sci_schedule_break_timer(struct sci_port *port)
  424. {
  425. port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
  426. add_timer(&port->break_timer);
  427. }
  428. /* Ensure that two consecutive samples find the break over. */
  429. static void sci_break_timer(unsigned long data)
  430. {
  431. struct sci_port *port = (struct sci_port *)data;
  432. if (sci_rxd_in(&port->port) == 0) {
  433. port->break_flag = 1;
  434. sci_schedule_break_timer(port);
  435. } else if (port->break_flag == 1) {
  436. /* break is over. */
  437. port->break_flag = 2;
  438. sci_schedule_break_timer(port);
  439. } else
  440. port->break_flag = 0;
  441. }
  442. static inline int sci_handle_errors(struct uart_port *port)
  443. {
  444. int copied = 0;
  445. unsigned short status = sci_in(port, SCxSR);
  446. struct tty_struct *tty = port->state->port.tty;
  447. if (status & SCxSR_ORER(port)) {
  448. /* overrun error */
  449. if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
  450. copied++;
  451. dev_notice(port->dev, "overrun error");
  452. }
  453. if (status & SCxSR_FER(port)) {
  454. if (sci_rxd_in(port) == 0) {
  455. /* Notify of BREAK */
  456. struct sci_port *sci_port = to_sci_port(port);
  457. if (!sci_port->break_flag) {
  458. sci_port->break_flag = 1;
  459. sci_schedule_break_timer(sci_port);
  460. /* Do sysrq handling. */
  461. if (uart_handle_break(port))
  462. return 0;
  463. dev_dbg(port->dev, "BREAK detected\n");
  464. if (tty_insert_flip_char(tty, 0, TTY_BREAK))
  465. copied++;
  466. }
  467. } else {
  468. /* frame error */
  469. if (tty_insert_flip_char(tty, 0, TTY_FRAME))
  470. copied++;
  471. dev_notice(port->dev, "frame error\n");
  472. }
  473. }
  474. if (status & SCxSR_PER(port)) {
  475. /* parity error */
  476. if (tty_insert_flip_char(tty, 0, TTY_PARITY))
  477. copied++;
  478. dev_notice(port->dev, "parity error");
  479. }
  480. if (copied)
  481. tty_flip_buffer_push(tty);
  482. return copied;
  483. }
  484. static inline int sci_handle_fifo_overrun(struct uart_port *port)
  485. {
  486. struct tty_struct *tty = port->state->port.tty;
  487. int copied = 0;
  488. if (port->type != PORT_SCIF)
  489. return 0;
  490. if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
  491. sci_out(port, SCLSR, 0);
  492. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  493. tty_flip_buffer_push(tty);
  494. dev_notice(port->dev, "overrun error\n");
  495. copied++;
  496. }
  497. return copied;
  498. }
  499. static inline int sci_handle_breaks(struct uart_port *port)
  500. {
  501. int copied = 0;
  502. unsigned short status = sci_in(port, SCxSR);
  503. struct tty_struct *tty = port->state->port.tty;
  504. struct sci_port *s = to_sci_port(port);
  505. if (uart_handle_break(port))
  506. return 0;
  507. if (!s->break_flag && status & SCxSR_BRK(port)) {
  508. #if defined(CONFIG_CPU_SH3)
  509. /* Debounce break */
  510. s->break_flag = 1;
  511. #endif
  512. /* Notify of BREAK */
  513. if (tty_insert_flip_char(tty, 0, TTY_BREAK))
  514. copied++;
  515. dev_dbg(port->dev, "BREAK detected\n");
  516. }
  517. if (copied)
  518. tty_flip_buffer_push(tty);
  519. copied += sci_handle_fifo_overrun(port);
  520. return copied;
  521. }
  522. static irqreturn_t sci_rx_interrupt(int irq, void *port)
  523. {
  524. /* I think sci_receive_chars has to be called irrespective
  525. * of whether the I_IXOFF is set, otherwise, how is the interrupt
  526. * to be disabled?
  527. */
  528. sci_receive_chars(port);
  529. return IRQ_HANDLED;
  530. }
  531. static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
  532. {
  533. struct uart_port *port = ptr;
  534. unsigned long flags;
  535. spin_lock_irqsave(&port->lock, flags);
  536. sci_transmit_chars(port);
  537. spin_unlock_irqrestore(&port->lock, flags);
  538. return IRQ_HANDLED;
  539. }
  540. static irqreturn_t sci_er_interrupt(int irq, void *ptr)
  541. {
  542. struct uart_port *port = ptr;
  543. /* Handle errors */
  544. if (port->type == PORT_SCI) {
  545. if (sci_handle_errors(port)) {
  546. /* discard character in rx buffer */
  547. sci_in(port, SCxSR);
  548. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  549. }
  550. } else {
  551. sci_handle_fifo_overrun(port);
  552. sci_rx_interrupt(irq, ptr);
  553. }
  554. sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  555. /* Kick the transmission */
  556. sci_tx_interrupt(irq, ptr);
  557. return IRQ_HANDLED;
  558. }
  559. static irqreturn_t sci_br_interrupt(int irq, void *ptr)
  560. {
  561. struct uart_port *port = ptr;
  562. /* Handle BREAKs */
  563. sci_handle_breaks(port);
  564. sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
  565. return IRQ_HANDLED;
  566. }
  567. static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
  568. {
  569. unsigned short ssr_status, scr_status, err_enabled;
  570. struct uart_port *port = ptr;
  571. irqreturn_t ret = IRQ_NONE;
  572. ssr_status = sci_in(port, SCxSR);
  573. scr_status = sci_in(port, SCSCR);
  574. err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
  575. /* Tx Interrupt */
  576. if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE))
  577. ret = sci_tx_interrupt(irq, ptr);
  578. /* Rx Interrupt */
  579. if ((ssr_status & SCxSR_RDxF(port)) && (scr_status & SCI_CTRL_FLAGS_RIE))
  580. ret = sci_rx_interrupt(irq, ptr);
  581. /* Error Interrupt */
  582. if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
  583. ret = sci_er_interrupt(irq, ptr);
  584. /* Break Interrupt */
  585. if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
  586. ret = sci_br_interrupt(irq, ptr);
  587. return ret;
  588. }
  589. /*
  590. * Here we define a transistion notifier so that we can update all of our
  591. * ports' baud rate when the peripheral clock changes.
  592. */
  593. static int sci_notifier(struct notifier_block *self,
  594. unsigned long phase, void *p)
  595. {
  596. struct sh_sci_priv *priv = container_of(self,
  597. struct sh_sci_priv, clk_nb);
  598. struct sci_port *sci_port;
  599. unsigned long flags;
  600. if ((phase == CPUFREQ_POSTCHANGE) ||
  601. (phase == CPUFREQ_RESUMECHANGE)) {
  602. spin_lock_irqsave(&priv->lock, flags);
  603. list_for_each_entry(sci_port, &priv->ports, node)
  604. sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
  605. spin_unlock_irqrestore(&priv->lock, flags);
  606. }
  607. return NOTIFY_OK;
  608. }
  609. static void sci_clk_enable(struct uart_port *port)
  610. {
  611. struct sci_port *sci_port = to_sci_port(port);
  612. clk_enable(sci_port->dclk);
  613. sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
  614. if (sci_port->iclk)
  615. clk_enable(sci_port->iclk);
  616. }
  617. static void sci_clk_disable(struct uart_port *port)
  618. {
  619. struct sci_port *sci_port = to_sci_port(port);
  620. if (sci_port->iclk)
  621. clk_disable(sci_port->iclk);
  622. clk_disable(sci_port->dclk);
  623. }
  624. static int sci_request_irq(struct sci_port *port)
  625. {
  626. int i;
  627. irqreturn_t (*handlers[4])(int irq, void *ptr) = {
  628. sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
  629. sci_br_interrupt,
  630. };
  631. const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
  632. "SCI Transmit Data Empty", "SCI Break" };
  633. if (port->irqs[0] == port->irqs[1]) {
  634. if (unlikely(!port->irqs[0]))
  635. return -ENODEV;
  636. if (request_irq(port->irqs[0], sci_mpxed_interrupt,
  637. IRQF_DISABLED, "sci", port)) {
  638. dev_err(port->port.dev, "Can't allocate IRQ\n");
  639. return -ENODEV;
  640. }
  641. } else {
  642. for (i = 0; i < ARRAY_SIZE(handlers); i++) {
  643. if (unlikely(!port->irqs[i]))
  644. continue;
  645. if (request_irq(port->irqs[i], handlers[i],
  646. IRQF_DISABLED, desc[i], port)) {
  647. dev_err(port->port.dev, "Can't allocate IRQ\n");
  648. return -ENODEV;
  649. }
  650. }
  651. }
  652. return 0;
  653. }
  654. static void sci_free_irq(struct sci_port *port)
  655. {
  656. int i;
  657. if (port->irqs[0] == port->irqs[1])
  658. free_irq(port->irqs[0], port);
  659. else {
  660. for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
  661. if (!port->irqs[i])
  662. continue;
  663. free_irq(port->irqs[i], port);
  664. }
  665. }
  666. }
  667. static unsigned int sci_tx_empty(struct uart_port *port)
  668. {
  669. unsigned short status = sci_in(port, SCxSR);
  670. return status & SCxSR_TEND(port) ? TIOCSER_TEMT : 0;
  671. }
  672. static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
  673. {
  674. /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
  675. /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
  676. /* If you have signals for DTR and DCD, please implement here. */
  677. }
  678. static unsigned int sci_get_mctrl(struct uart_port *port)
  679. {
  680. /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
  681. and CTS/RTS */
  682. return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
  683. }
  684. static void sci_start_tx(struct uart_port *port)
  685. {
  686. unsigned short ctrl;
  687. /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
  688. ctrl = sci_in(port, SCSCR);
  689. ctrl |= SCI_CTRL_FLAGS_TIE;
  690. sci_out(port, SCSCR, ctrl);
  691. }
  692. static void sci_stop_tx(struct uart_port *port)
  693. {
  694. unsigned short ctrl;
  695. /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
  696. ctrl = sci_in(port, SCSCR);
  697. ctrl &= ~SCI_CTRL_FLAGS_TIE;
  698. sci_out(port, SCSCR, ctrl);
  699. }
  700. static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
  701. {
  702. unsigned short ctrl;
  703. /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
  704. ctrl = sci_in(port, SCSCR);
  705. ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
  706. sci_out(port, SCSCR, ctrl);
  707. }
  708. static void sci_stop_rx(struct uart_port *port)
  709. {
  710. unsigned short ctrl;
  711. /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
  712. ctrl = sci_in(port, SCSCR);
  713. ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
  714. sci_out(port, SCSCR, ctrl);
  715. }
  716. static void sci_enable_ms(struct uart_port *port)
  717. {
  718. /* Nothing here yet .. */
  719. }
  720. static void sci_break_ctl(struct uart_port *port, int break_state)
  721. {
  722. /* Nothing here yet .. */
  723. }
  724. static int sci_startup(struct uart_port *port)
  725. {
  726. struct sci_port *s = to_sci_port(port);
  727. if (s->enable)
  728. s->enable(port);
  729. sci_request_irq(s);
  730. sci_start_tx(port);
  731. sci_start_rx(port, 1);
  732. return 0;
  733. }
  734. static void sci_shutdown(struct uart_port *port)
  735. {
  736. struct sci_port *s = to_sci_port(port);
  737. sci_stop_rx(port);
  738. sci_stop_tx(port);
  739. sci_free_irq(s);
  740. if (s->disable)
  741. s->disable(port);
  742. }
  743. static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
  744. struct ktermios *old)
  745. {
  746. unsigned int status, baud, smr_val;
  747. int t = -1;
  748. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  749. if (likely(baud))
  750. t = SCBRR_VALUE(baud, port->uartclk);
  751. do {
  752. status = sci_in(port, SCxSR);
  753. } while (!(status & SCxSR_TEND(port)));
  754. sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
  755. if (port->type != PORT_SCI)
  756. sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
  757. smr_val = sci_in(port, SCSMR) & 3;
  758. if ((termios->c_cflag & CSIZE) == CS7)
  759. smr_val |= 0x40;
  760. if (termios->c_cflag & PARENB)
  761. smr_val |= 0x20;
  762. if (termios->c_cflag & PARODD)
  763. smr_val |= 0x30;
  764. if (termios->c_cflag & CSTOPB)
  765. smr_val |= 0x08;
  766. uart_update_timeout(port, termios->c_cflag, baud);
  767. sci_out(port, SCSMR, smr_val);
  768. if (t > 0) {
  769. if (t >= 256) {
  770. sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
  771. t >>= 2;
  772. } else
  773. sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
  774. sci_out(port, SCBRR, t);
  775. udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
  776. }
  777. sci_init_pins(port, termios->c_cflag);
  778. sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
  779. sci_out(port, SCSCR, SCSCR_INIT(port));
  780. if ((termios->c_cflag & CREAD) != 0)
  781. sci_start_rx(port, 0);
  782. }
  783. static const char *sci_type(struct uart_port *port)
  784. {
  785. switch (port->type) {
  786. case PORT_IRDA:
  787. return "irda";
  788. case PORT_SCI:
  789. return "sci";
  790. case PORT_SCIF:
  791. return "scif";
  792. case PORT_SCIFA:
  793. return "scifa";
  794. }
  795. return NULL;
  796. }
  797. static void sci_release_port(struct uart_port *port)
  798. {
  799. /* Nothing here yet .. */
  800. }
  801. static int sci_request_port(struct uart_port *port)
  802. {
  803. /* Nothing here yet .. */
  804. return 0;
  805. }
  806. static void sci_config_port(struct uart_port *port, int flags)
  807. {
  808. struct sci_port *s = to_sci_port(port);
  809. port->type = s->type;
  810. if (port->membase)
  811. return;
  812. if (port->flags & UPF_IOREMAP) {
  813. port->membase = ioremap_nocache(port->mapbase, 0x40);
  814. if (IS_ERR(port->membase))
  815. dev_err(port->dev, "can't remap port#%d\n", port->line);
  816. } else {
  817. /*
  818. * For the simple (and majority of) cases where we don't
  819. * need to do any remapping, just cast the cookie
  820. * directly.
  821. */
  822. port->membase = (void __iomem *)port->mapbase;
  823. }
  824. }
  825. static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
  826. {
  827. struct sci_port *s = to_sci_port(port);
  828. if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
  829. return -EINVAL;
  830. if (ser->baud_base < 2400)
  831. /* No paper tape reader for Mitch.. */
  832. return -EINVAL;
  833. return 0;
  834. }
  835. static struct uart_ops sci_uart_ops = {
  836. .tx_empty = sci_tx_empty,
  837. .set_mctrl = sci_set_mctrl,
  838. .get_mctrl = sci_get_mctrl,
  839. .start_tx = sci_start_tx,
  840. .stop_tx = sci_stop_tx,
  841. .stop_rx = sci_stop_rx,
  842. .enable_ms = sci_enable_ms,
  843. .break_ctl = sci_break_ctl,
  844. .startup = sci_startup,
  845. .shutdown = sci_shutdown,
  846. .set_termios = sci_set_termios,
  847. .type = sci_type,
  848. .release_port = sci_release_port,
  849. .request_port = sci_request_port,
  850. .config_port = sci_config_port,
  851. .verify_port = sci_verify_port,
  852. #ifdef CONFIG_CONSOLE_POLL
  853. .poll_get_char = sci_poll_get_char,
  854. .poll_put_char = sci_poll_put_char,
  855. #endif
  856. };
  857. static void __devinit sci_init_single(struct platform_device *dev,
  858. struct sci_port *sci_port,
  859. unsigned int index,
  860. struct plat_sci_port *p)
  861. {
  862. sci_port->port.ops = &sci_uart_ops;
  863. sci_port->port.iotype = UPIO_MEM;
  864. sci_port->port.line = index;
  865. sci_port->port.fifosize = 1;
  866. sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
  867. sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
  868. sci_port->enable = sci_clk_enable;
  869. sci_port->disable = sci_clk_disable;
  870. sci_port->break_timer.data = (unsigned long)sci_port;
  871. sci_port->break_timer.function = sci_break_timer;
  872. init_timer(&sci_port->break_timer);
  873. sci_port->port.mapbase = p->mapbase;
  874. sci_port->port.membase = p->membase;
  875. sci_port->port.irq = p->irqs[SCIx_TXI_IRQ];
  876. sci_port->port.flags = p->flags;
  877. sci_port->port.dev = &dev->dev;
  878. sci_port->type = sci_port->port.type = p->type;
  879. memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
  880. }
  881. #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
  882. static struct tty_driver *serial_console_device(struct console *co, int *index)
  883. {
  884. struct uart_driver *p = &sci_uart_driver;
  885. *index = co->index;
  886. return p->tty_driver;
  887. }
  888. static void serial_console_putchar(struct uart_port *port, int ch)
  889. {
  890. sci_poll_put_char(port, ch);
  891. }
  892. /*
  893. * Print a string to the serial port trying not to disturb
  894. * any possible real use of the port...
  895. */
  896. static void serial_console_write(struct console *co, const char *s,
  897. unsigned count)
  898. {
  899. struct uart_port *port = co->data;
  900. struct sci_port *sci_port = to_sci_port(port);
  901. unsigned short bits;
  902. if (sci_port->enable)
  903. sci_port->enable(port);
  904. uart_console_write(port, s, count, serial_console_putchar);
  905. /* wait until fifo is empty and last bit has been transmitted */
  906. bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
  907. while ((sci_in(port, SCxSR) & bits) != bits)
  908. cpu_relax();
  909. if (sci_port->disable)
  910. sci_port->disable(port);
  911. }
  912. static int __init serial_console_setup(struct console *co, char *options)
  913. {
  914. struct sci_port *sci_port;
  915. struct uart_port *port;
  916. int baud = 115200;
  917. int bits = 8;
  918. int parity = 'n';
  919. int flow = 'n';
  920. int ret;
  921. /*
  922. * Check whether an invalid uart number has been specified, and
  923. * if so, search for the first available port that does have
  924. * console support.
  925. */
  926. if (co->index >= SCI_NPORTS)
  927. co->index = 0;
  928. sci_port = &sci_ports[co->index];
  929. port = &sci_port->port;
  930. co->data = port;
  931. /*
  932. * Also need to check port->type, we don't actually have any
  933. * UPIO_PORT ports, but uart_report_port() handily misreports
  934. * it anyways if we don't have a port available by the time this is
  935. * called.
  936. */
  937. if (!port->type)
  938. return -ENODEV;
  939. sci_config_port(port, 0);
  940. if (sci_port->enable)
  941. sci_port->enable(port);
  942. if (options)
  943. uart_parse_options(options, &baud, &parity, &bits, &flow);
  944. ret = uart_set_options(port, co, baud, parity, bits, flow);
  945. #if defined(__H8300H__) || defined(__H8300S__)
  946. /* disable rx interrupt */
  947. if (ret == 0)
  948. sci_stop_rx(port);
  949. #endif
  950. /* TODO: disable clock */
  951. return ret;
  952. }
  953. static struct console serial_console = {
  954. .name = "ttySC",
  955. .device = serial_console_device,
  956. .write = serial_console_write,
  957. .setup = serial_console_setup,
  958. .flags = CON_PRINTBUFFER,
  959. .index = -1,
  960. };
  961. static int __init sci_console_init(void)
  962. {
  963. register_console(&serial_console);
  964. return 0;
  965. }
  966. console_initcall(sci_console_init);
  967. #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
  968. #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
  969. #define SCI_CONSOLE (&serial_console)
  970. #else
  971. #define SCI_CONSOLE 0
  972. #endif
  973. static char banner[] __initdata =
  974. KERN_INFO "SuperH SCI(F) driver initialized\n";
  975. static struct uart_driver sci_uart_driver = {
  976. .owner = THIS_MODULE,
  977. .driver_name = "sci",
  978. .dev_name = "ttySC",
  979. .major = SCI_MAJOR,
  980. .minor = SCI_MINOR_START,
  981. .nr = SCI_NPORTS,
  982. .cons = SCI_CONSOLE,
  983. };
  984. static int sci_remove(struct platform_device *dev)
  985. {
  986. struct sh_sci_priv *priv = platform_get_drvdata(dev);
  987. struct sci_port *p;
  988. unsigned long flags;
  989. cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
  990. spin_lock_irqsave(&priv->lock, flags);
  991. list_for_each_entry(p, &priv->ports, node)
  992. uart_remove_one_port(&sci_uart_driver, &p->port);
  993. spin_unlock_irqrestore(&priv->lock, flags);
  994. kfree(priv);
  995. return 0;
  996. }
  997. static int __devinit sci_probe_single(struct platform_device *dev,
  998. unsigned int index,
  999. struct plat_sci_port *p,
  1000. struct sci_port *sciport)
  1001. {
  1002. struct sh_sci_priv *priv = platform_get_drvdata(dev);
  1003. unsigned long flags;
  1004. int ret;
  1005. /* Sanity check */
  1006. if (unlikely(index >= SCI_NPORTS)) {
  1007. dev_notice(&dev->dev, "Attempting to register port "
  1008. "%d when only %d are available.\n",
  1009. index+1, SCI_NPORTS);
  1010. dev_notice(&dev->dev, "Consider bumping "
  1011. "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
  1012. return 0;
  1013. }
  1014. sci_init_single(dev, sciport, index, p);
  1015. ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
  1016. if (ret)
  1017. return ret;
  1018. INIT_LIST_HEAD(&sciport->node);
  1019. spin_lock_irqsave(&priv->lock, flags);
  1020. list_add(&sciport->node, &priv->ports);
  1021. spin_unlock_irqrestore(&priv->lock, flags);
  1022. return 0;
  1023. }
  1024. /*
  1025. * Register a set of serial devices attached to a platform device. The
  1026. * list is terminated with a zero flags entry, which means we expect
  1027. * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
  1028. * remapping (such as sh64) should also set UPF_IOREMAP.
  1029. */
  1030. static int __devinit sci_probe(struct platform_device *dev)
  1031. {
  1032. struct plat_sci_port *p = dev->dev.platform_data;
  1033. struct sh_sci_priv *priv;
  1034. int i, ret = -EINVAL;
  1035. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  1036. if (!priv)
  1037. return -ENOMEM;
  1038. INIT_LIST_HEAD(&priv->ports);
  1039. spin_lock_init(&priv->lock);
  1040. platform_set_drvdata(dev, priv);
  1041. priv->clk_nb.notifier_call = sci_notifier;
  1042. cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
  1043. if (dev->id != -1) {
  1044. ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
  1045. if (ret)
  1046. goto err_unreg;
  1047. } else {
  1048. for (i = 0; p && p->flags != 0; p++, i++) {
  1049. ret = sci_probe_single(dev, i, p, &sci_ports[i]);
  1050. if (ret)
  1051. goto err_unreg;
  1052. }
  1053. }
  1054. #ifdef CONFIG_SH_STANDARD_BIOS
  1055. sh_bios_gdb_detach();
  1056. #endif
  1057. return 0;
  1058. err_unreg:
  1059. sci_remove(dev);
  1060. return ret;
  1061. }
  1062. static int sci_suspend(struct device *dev)
  1063. {
  1064. struct sh_sci_priv *priv = dev_get_drvdata(dev);
  1065. struct sci_port *p;
  1066. unsigned long flags;
  1067. spin_lock_irqsave(&priv->lock, flags);
  1068. list_for_each_entry(p, &priv->ports, node)
  1069. uart_suspend_port(&sci_uart_driver, &p->port);
  1070. spin_unlock_irqrestore(&priv->lock, flags);
  1071. return 0;
  1072. }
  1073. static int sci_resume(struct device *dev)
  1074. {
  1075. struct sh_sci_priv *priv = dev_get_drvdata(dev);
  1076. struct sci_port *p;
  1077. unsigned long flags;
  1078. spin_lock_irqsave(&priv->lock, flags);
  1079. list_for_each_entry(p, &priv->ports, node)
  1080. uart_resume_port(&sci_uart_driver, &p->port);
  1081. spin_unlock_irqrestore(&priv->lock, flags);
  1082. return 0;
  1083. }
  1084. static struct dev_pm_ops sci_dev_pm_ops = {
  1085. .suspend = sci_suspend,
  1086. .resume = sci_resume,
  1087. };
  1088. static struct platform_driver sci_driver = {
  1089. .probe = sci_probe,
  1090. .remove = sci_remove,
  1091. .driver = {
  1092. .name = "sh-sci",
  1093. .owner = THIS_MODULE,
  1094. .pm = &sci_dev_pm_ops,
  1095. },
  1096. };
  1097. static int __init sci_init(void)
  1098. {
  1099. int ret;
  1100. printk(banner);
  1101. ret = uart_register_driver(&sci_uart_driver);
  1102. if (likely(ret == 0)) {
  1103. ret = platform_driver_register(&sci_driver);
  1104. if (unlikely(ret))
  1105. uart_unregister_driver(&sci_uart_driver);
  1106. }
  1107. return ret;
  1108. }
  1109. static void __exit sci_exit(void)
  1110. {
  1111. platform_driver_unregister(&sci_driver);
  1112. uart_unregister_driver(&sci_uart_driver);
  1113. }
  1114. module_init(sci_init);
  1115. module_exit(sci_exit);
  1116. MODULE_LICENSE("GPL");
  1117. MODULE_ALIAS("platform:sh-sci");