pio.c 20 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. PIO data transfer
  4. Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; see the file COPYING. If not, write to
  15. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  16. Boston, MA 02110-1301, USA.
  17. */
  18. #include "b43.h"
  19. #include "pio.h"
  20. #include "dma.h"
  21. #include "main.h"
  22. #include "xmit.h"
  23. #include <linux/delay.h>
  24. #include <linux/sched.h>
  25. static u16 generate_cookie(struct b43_pio_txqueue *q,
  26. struct b43_pio_txpacket *pack)
  27. {
  28. u16 cookie;
  29. /* Use the upper 4 bits of the cookie as
  30. * PIO controller ID and store the packet index number
  31. * in the lower 12 bits.
  32. * Note that the cookie must never be 0, as this
  33. * is a special value used in RX path.
  34. * It can also not be 0xFFFF because that is special
  35. * for multicast frames.
  36. */
  37. cookie = (((u16)q->index + 1) << 12);
  38. cookie |= pack->index;
  39. return cookie;
  40. }
  41. static
  42. struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev,
  43. u16 cookie,
  44. struct b43_pio_txpacket **pack)
  45. {
  46. struct b43_pio *pio = &dev->pio;
  47. struct b43_pio_txqueue *q = NULL;
  48. unsigned int pack_index;
  49. switch (cookie & 0xF000) {
  50. case 0x1000:
  51. q = pio->tx_queue_AC_BK;
  52. break;
  53. case 0x2000:
  54. q = pio->tx_queue_AC_BE;
  55. break;
  56. case 0x3000:
  57. q = pio->tx_queue_AC_VI;
  58. break;
  59. case 0x4000:
  60. q = pio->tx_queue_AC_VO;
  61. break;
  62. case 0x5000:
  63. q = pio->tx_queue_mcast;
  64. break;
  65. }
  66. if (B43_WARN_ON(!q))
  67. return NULL;
  68. pack_index = (cookie & 0x0FFF);
  69. if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
  70. return NULL;
  71. *pack = &q->packets[pack_index];
  72. return q;
  73. }
  74. static u16 index_to_pioqueue_base(struct b43_wldev *dev,
  75. unsigned int index)
  76. {
  77. static const u16 bases[] = {
  78. B43_MMIO_PIO_BASE0,
  79. B43_MMIO_PIO_BASE1,
  80. B43_MMIO_PIO_BASE2,
  81. B43_MMIO_PIO_BASE3,
  82. B43_MMIO_PIO_BASE4,
  83. B43_MMIO_PIO_BASE5,
  84. B43_MMIO_PIO_BASE6,
  85. B43_MMIO_PIO_BASE7,
  86. };
  87. static const u16 bases_rev11[] = {
  88. B43_MMIO_PIO11_BASE0,
  89. B43_MMIO_PIO11_BASE1,
  90. B43_MMIO_PIO11_BASE2,
  91. B43_MMIO_PIO11_BASE3,
  92. B43_MMIO_PIO11_BASE4,
  93. B43_MMIO_PIO11_BASE5,
  94. };
  95. if (dev->dev->id.revision >= 11) {
  96. B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
  97. return bases_rev11[index];
  98. }
  99. B43_WARN_ON(index >= ARRAY_SIZE(bases));
  100. return bases[index];
  101. }
  102. static u16 pio_txqueue_offset(struct b43_wldev *dev)
  103. {
  104. if (dev->dev->id.revision >= 11)
  105. return 0x18;
  106. return 0;
  107. }
  108. static u16 pio_rxqueue_offset(struct b43_wldev *dev)
  109. {
  110. if (dev->dev->id.revision >= 11)
  111. return 0x38;
  112. return 8;
  113. }
  114. static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
  115. unsigned int index)
  116. {
  117. struct b43_pio_txqueue *q;
  118. struct b43_pio_txpacket *p;
  119. unsigned int i;
  120. q = kzalloc(sizeof(*q), GFP_KERNEL);
  121. if (!q)
  122. return NULL;
  123. q->dev = dev;
  124. q->rev = dev->dev->id.revision;
  125. q->mmio_base = index_to_pioqueue_base(dev, index) +
  126. pio_txqueue_offset(dev);
  127. q->index = index;
  128. q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
  129. if (q->rev >= 8) {
  130. q->buffer_size = 1920; //FIXME this constant is wrong.
  131. } else {
  132. q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
  133. q->buffer_size -= 80;
  134. }
  135. INIT_LIST_HEAD(&q->packets_list);
  136. for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
  137. p = &(q->packets[i]);
  138. INIT_LIST_HEAD(&p->list);
  139. p->index = i;
  140. p->queue = q;
  141. list_add(&p->list, &q->packets_list);
  142. }
  143. return q;
  144. }
  145. static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
  146. unsigned int index)
  147. {
  148. struct b43_pio_rxqueue *q;
  149. q = kzalloc(sizeof(*q), GFP_KERNEL);
  150. if (!q)
  151. return NULL;
  152. q->dev = dev;
  153. q->rev = dev->dev->id.revision;
  154. q->mmio_base = index_to_pioqueue_base(dev, index) +
  155. pio_rxqueue_offset(dev);
  156. /* Enable Direct FIFO RX (PIO) on the engine. */
  157. b43_dma_direct_fifo_rx(dev, index, 1);
  158. return q;
  159. }
  160. static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
  161. {
  162. struct b43_pio_txpacket *pack;
  163. unsigned int i;
  164. for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
  165. pack = &(q->packets[i]);
  166. if (pack->skb) {
  167. dev_kfree_skb_any(pack->skb);
  168. pack->skb = NULL;
  169. }
  170. }
  171. }
  172. static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
  173. const char *name)
  174. {
  175. if (!q)
  176. return;
  177. b43_pio_cancel_tx_packets(q);
  178. kfree(q);
  179. }
  180. static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
  181. const char *name)
  182. {
  183. if (!q)
  184. return;
  185. kfree(q);
  186. }
  187. #define destroy_queue_tx(pio, queue) do { \
  188. b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
  189. (pio)->queue = NULL; \
  190. } while (0)
  191. #define destroy_queue_rx(pio, queue) do { \
  192. b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
  193. (pio)->queue = NULL; \
  194. } while (0)
  195. void b43_pio_free(struct b43_wldev *dev)
  196. {
  197. struct b43_pio *pio;
  198. if (!b43_using_pio_transfers(dev))
  199. return;
  200. pio = &dev->pio;
  201. destroy_queue_rx(pio, rx_queue);
  202. destroy_queue_tx(pio, tx_queue_mcast);
  203. destroy_queue_tx(pio, tx_queue_AC_VO);
  204. destroy_queue_tx(pio, tx_queue_AC_VI);
  205. destroy_queue_tx(pio, tx_queue_AC_BE);
  206. destroy_queue_tx(pio, tx_queue_AC_BK);
  207. }
  208. int b43_pio_init(struct b43_wldev *dev)
  209. {
  210. struct b43_pio *pio = &dev->pio;
  211. int err = -ENOMEM;
  212. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  213. & ~B43_MACCTL_BE);
  214. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
  215. pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
  216. if (!pio->tx_queue_AC_BK)
  217. goto out;
  218. pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
  219. if (!pio->tx_queue_AC_BE)
  220. goto err_destroy_bk;
  221. pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
  222. if (!pio->tx_queue_AC_VI)
  223. goto err_destroy_be;
  224. pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
  225. if (!pio->tx_queue_AC_VO)
  226. goto err_destroy_vi;
  227. pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
  228. if (!pio->tx_queue_mcast)
  229. goto err_destroy_vo;
  230. pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
  231. if (!pio->rx_queue)
  232. goto err_destroy_mcast;
  233. b43dbg(dev->wl, "PIO initialized\n");
  234. err = 0;
  235. out:
  236. return err;
  237. err_destroy_mcast:
  238. destroy_queue_tx(pio, tx_queue_mcast);
  239. err_destroy_vo:
  240. destroy_queue_tx(pio, tx_queue_AC_VO);
  241. err_destroy_vi:
  242. destroy_queue_tx(pio, tx_queue_AC_VI);
  243. err_destroy_be:
  244. destroy_queue_tx(pio, tx_queue_AC_BE);
  245. err_destroy_bk:
  246. destroy_queue_tx(pio, tx_queue_AC_BK);
  247. return err;
  248. }
  249. /* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
  250. static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev,
  251. u8 queue_prio)
  252. {
  253. struct b43_pio_txqueue *q;
  254. if (dev->qos_enabled) {
  255. /* 0 = highest priority */
  256. switch (queue_prio) {
  257. default:
  258. B43_WARN_ON(1);
  259. /* fallthrough */
  260. case 0:
  261. q = dev->pio.tx_queue_AC_VO;
  262. break;
  263. case 1:
  264. q = dev->pio.tx_queue_AC_VI;
  265. break;
  266. case 2:
  267. q = dev->pio.tx_queue_AC_BE;
  268. break;
  269. case 3:
  270. q = dev->pio.tx_queue_AC_BK;
  271. break;
  272. }
  273. } else
  274. q = dev->pio.tx_queue_AC_BE;
  275. return q;
  276. }
  277. static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
  278. u16 ctl,
  279. const void *_data,
  280. unsigned int data_len)
  281. {
  282. struct b43_wldev *dev = q->dev;
  283. struct b43_wl *wl = dev->wl;
  284. const u8 *data = _data;
  285. ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
  286. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  287. ssb_block_write(dev->dev, data, (data_len & ~1),
  288. q->mmio_base + B43_PIO_TXDATA,
  289. sizeof(u16));
  290. if (data_len & 1) {
  291. u8 *tail = wl->pio_tailspace;
  292. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2);
  293. /* Write the last byte. */
  294. ctl &= ~B43_PIO_TXCTL_WRITEHI;
  295. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  296. tail[0] = data[data_len - 1];
  297. tail[1] = 0;
  298. ssb_block_write(dev->dev, tail, 2,
  299. q->mmio_base + B43_PIO_TXDATA,
  300. sizeof(u16));
  301. }
  302. return ctl;
  303. }
  304. static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
  305. const u8 *hdr, unsigned int hdrlen)
  306. {
  307. struct b43_pio_txqueue *q = pack->queue;
  308. const char *frame = pack->skb->data;
  309. unsigned int frame_len = pack->skb->len;
  310. u16 ctl;
  311. ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
  312. ctl |= B43_PIO_TXCTL_FREADY;
  313. ctl &= ~B43_PIO_TXCTL_EOF;
  314. /* Transfer the header data. */
  315. ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
  316. /* Transfer the frame data. */
  317. ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
  318. ctl |= B43_PIO_TXCTL_EOF;
  319. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  320. }
  321. static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
  322. u32 ctl,
  323. const void *_data,
  324. unsigned int data_len)
  325. {
  326. struct b43_wldev *dev = q->dev;
  327. struct b43_wl *wl = dev->wl;
  328. const u8 *data = _data;
  329. ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
  330. B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
  331. b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
  332. ssb_block_write(dev->dev, data, (data_len & ~3),
  333. q->mmio_base + B43_PIO8_TXDATA,
  334. sizeof(u32));
  335. if (data_len & 3) {
  336. u8 *tail = wl->pio_tailspace;
  337. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4);
  338. memset(tail, 0, 4);
  339. /* Write the last few bytes. */
  340. ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
  341. B43_PIO8_TXCTL_24_31);
  342. switch (data_len & 3) {
  343. case 3:
  344. ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15;
  345. tail[0] = data[data_len - 3];
  346. tail[1] = data[data_len - 2];
  347. tail[2] = data[data_len - 1];
  348. break;
  349. case 2:
  350. ctl |= B43_PIO8_TXCTL_8_15;
  351. tail[0] = data[data_len - 2];
  352. tail[1] = data[data_len - 1];
  353. break;
  354. case 1:
  355. tail[0] = data[data_len - 1];
  356. break;
  357. }
  358. b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
  359. ssb_block_write(dev->dev, tail, 4,
  360. q->mmio_base + B43_PIO8_TXDATA,
  361. sizeof(u32));
  362. }
  363. return ctl;
  364. }
  365. static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
  366. const u8 *hdr, unsigned int hdrlen)
  367. {
  368. struct b43_pio_txqueue *q = pack->queue;
  369. const char *frame = pack->skb->data;
  370. unsigned int frame_len = pack->skb->len;
  371. u32 ctl;
  372. ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
  373. ctl |= B43_PIO8_TXCTL_FREADY;
  374. ctl &= ~B43_PIO8_TXCTL_EOF;
  375. /* Transfer the header data. */
  376. ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
  377. /* Transfer the frame data. */
  378. ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
  379. ctl |= B43_PIO8_TXCTL_EOF;
  380. b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
  381. }
  382. static int pio_tx_frame(struct b43_pio_txqueue *q,
  383. struct sk_buff *skb)
  384. {
  385. struct b43_wldev *dev = q->dev;
  386. struct b43_wl *wl = dev->wl;
  387. struct b43_pio_txpacket *pack;
  388. u16 cookie;
  389. int err;
  390. unsigned int hdrlen;
  391. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  392. struct b43_txhdr *txhdr = (struct b43_txhdr *)wl->pio_scratchspace;
  393. B43_WARN_ON(list_empty(&q->packets_list));
  394. pack = list_entry(q->packets_list.next,
  395. struct b43_pio_txpacket, list);
  396. cookie = generate_cookie(q, pack);
  397. hdrlen = b43_txhdr_size(dev);
  398. BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(struct b43_txhdr));
  399. B43_WARN_ON(sizeof(wl->pio_scratchspace) < hdrlen);
  400. err = b43_generate_txhdr(dev, (u8 *)txhdr, skb,
  401. info, cookie);
  402. if (err)
  403. return err;
  404. if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
  405. /* Tell the firmware about the cookie of the last
  406. * mcast frame, so it can clear the more-data bit in it. */
  407. b43_shm_write16(dev, B43_SHM_SHARED,
  408. B43_SHM_SH_MCASTCOOKIE, cookie);
  409. }
  410. pack->skb = skb;
  411. if (q->rev >= 8)
  412. pio_tx_frame_4byte_queue(pack, (const u8 *)txhdr, hdrlen);
  413. else
  414. pio_tx_frame_2byte_queue(pack, (const u8 *)txhdr, hdrlen);
  415. /* Remove it from the list of available packet slots.
  416. * It will be put back when we receive the status report. */
  417. list_del(&pack->list);
  418. /* Update the queue statistics. */
  419. q->buffer_used += roundup(skb->len + hdrlen, 4);
  420. q->free_packet_slots -= 1;
  421. return 0;
  422. }
  423. int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
  424. {
  425. struct b43_pio_txqueue *q;
  426. struct ieee80211_hdr *hdr;
  427. unsigned int hdrlen, total_len;
  428. int err = 0;
  429. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  430. hdr = (struct ieee80211_hdr *)skb->data;
  431. if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
  432. /* The multicast queue will be sent after the DTIM. */
  433. q = dev->pio.tx_queue_mcast;
  434. /* Set the frame More-Data bit. Ucode will clear it
  435. * for us on the last frame. */
  436. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
  437. } else {
  438. /* Decide by priority where to put this frame. */
  439. q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
  440. }
  441. hdrlen = b43_txhdr_size(dev);
  442. total_len = roundup(skb->len + hdrlen, 4);
  443. if (unlikely(total_len > q->buffer_size)) {
  444. err = -ENOBUFS;
  445. b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
  446. goto out;
  447. }
  448. if (unlikely(q->free_packet_slots == 0)) {
  449. err = -ENOBUFS;
  450. b43warn(dev->wl, "PIO: TX packet overflow.\n");
  451. goto out;
  452. }
  453. B43_WARN_ON(q->buffer_used > q->buffer_size);
  454. if (total_len > (q->buffer_size - q->buffer_used)) {
  455. /* Not enough memory on the queue. */
  456. err = -EBUSY;
  457. ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
  458. q->stopped = 1;
  459. goto out;
  460. }
  461. /* Assign the queue number to the ring (if not already done before)
  462. * so TX status handling can use it. The mac80211-queue to b43-queue
  463. * mapping is static, so we don't need to store it per frame. */
  464. q->queue_prio = skb_get_queue_mapping(skb);
  465. err = pio_tx_frame(q, skb);
  466. if (unlikely(err == -ENOKEY)) {
  467. /* Drop this packet, as we don't have the encryption key
  468. * anymore and must not transmit it unencrypted. */
  469. dev_kfree_skb_any(skb);
  470. err = 0;
  471. goto out;
  472. }
  473. if (unlikely(err)) {
  474. b43err(dev->wl, "PIO transmission failure\n");
  475. goto out;
  476. }
  477. q->nr_tx_packets++;
  478. B43_WARN_ON(q->buffer_used > q->buffer_size);
  479. if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
  480. (q->free_packet_slots == 0)) {
  481. /* The queue is full. */
  482. ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
  483. q->stopped = 1;
  484. }
  485. out:
  486. return err;
  487. }
  488. void b43_pio_handle_txstatus(struct b43_wldev *dev,
  489. const struct b43_txstatus *status)
  490. {
  491. struct b43_pio_txqueue *q;
  492. struct b43_pio_txpacket *pack = NULL;
  493. unsigned int total_len;
  494. struct ieee80211_tx_info *info;
  495. q = parse_cookie(dev, status->cookie, &pack);
  496. if (unlikely(!q))
  497. return;
  498. B43_WARN_ON(!pack);
  499. info = IEEE80211_SKB_CB(pack->skb);
  500. b43_fill_txstatus_report(dev, info, status);
  501. total_len = pack->skb->len + b43_txhdr_size(dev);
  502. total_len = roundup(total_len, 4);
  503. q->buffer_used -= total_len;
  504. q->free_packet_slots += 1;
  505. ieee80211_tx_status(dev->wl->hw, pack->skb);
  506. pack->skb = NULL;
  507. list_add(&pack->list, &q->packets_list);
  508. if (q->stopped) {
  509. ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
  510. q->stopped = 0;
  511. }
  512. }
  513. void b43_pio_get_tx_stats(struct b43_wldev *dev,
  514. struct ieee80211_tx_queue_stats *stats)
  515. {
  516. const int nr_queues = dev->wl->hw->queues;
  517. struct b43_pio_txqueue *q;
  518. int i;
  519. for (i = 0; i < nr_queues; i++) {
  520. q = select_queue_by_priority(dev, i);
  521. stats[i].len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots;
  522. stats[i].limit = B43_PIO_MAX_NR_TXPACKETS;
  523. stats[i].count = q->nr_tx_packets;
  524. }
  525. }
  526. /* Returns whether we should fetch another frame. */
  527. static bool pio_rx_frame(struct b43_pio_rxqueue *q)
  528. {
  529. struct b43_wldev *dev = q->dev;
  530. struct b43_wl *wl = dev->wl;
  531. u16 len;
  532. u32 macstat;
  533. unsigned int i, padding;
  534. struct sk_buff *skb;
  535. const char *err_msg = NULL;
  536. struct b43_rxhdr_fw4 *rxhdr =
  537. (struct b43_rxhdr_fw4 *)wl->pio_scratchspace;
  538. BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(*rxhdr));
  539. memset(rxhdr, 0, sizeof(*rxhdr));
  540. /* Check if we have data and wait for it to get ready. */
  541. if (q->rev >= 8) {
  542. u32 ctl;
  543. ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
  544. if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
  545. return 0;
  546. b43_piorx_write32(q, B43_PIO8_RXCTL,
  547. B43_PIO8_RXCTL_FRAMERDY);
  548. for (i = 0; i < 10; i++) {
  549. ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
  550. if (ctl & B43_PIO8_RXCTL_DATARDY)
  551. goto data_ready;
  552. udelay(10);
  553. }
  554. } else {
  555. u16 ctl;
  556. ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
  557. if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
  558. return 0;
  559. b43_piorx_write16(q, B43_PIO_RXCTL,
  560. B43_PIO_RXCTL_FRAMERDY);
  561. for (i = 0; i < 10; i++) {
  562. ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
  563. if (ctl & B43_PIO_RXCTL_DATARDY)
  564. goto data_ready;
  565. udelay(10);
  566. }
  567. }
  568. b43dbg(q->dev->wl, "PIO RX timed out\n");
  569. return 1;
  570. data_ready:
  571. /* Get the preamble (RX header) */
  572. if (q->rev >= 8) {
  573. ssb_block_read(dev->dev, rxhdr, sizeof(*rxhdr),
  574. q->mmio_base + B43_PIO8_RXDATA,
  575. sizeof(u32));
  576. } else {
  577. ssb_block_read(dev->dev, rxhdr, sizeof(*rxhdr),
  578. q->mmio_base + B43_PIO_RXDATA,
  579. sizeof(u16));
  580. }
  581. /* Sanity checks. */
  582. len = le16_to_cpu(rxhdr->frame_len);
  583. if (unlikely(len > 0x700)) {
  584. err_msg = "len > 0x700";
  585. goto rx_error;
  586. }
  587. if (unlikely(len == 0)) {
  588. err_msg = "len == 0";
  589. goto rx_error;
  590. }
  591. macstat = le32_to_cpu(rxhdr->mac_status);
  592. if (macstat & B43_RX_MAC_FCSERR) {
  593. if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
  594. /* Drop frames with failed FCS. */
  595. err_msg = "Frame FCS error";
  596. goto rx_error;
  597. }
  598. }
  599. /* We always pad 2 bytes, as that's what upstream code expects
  600. * due to the RX-header being 30 bytes. In case the frame is
  601. * unaligned, we pad another 2 bytes. */
  602. padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
  603. skb = dev_alloc_skb(len + padding + 2);
  604. if (unlikely(!skb)) {
  605. err_msg = "Out of memory";
  606. goto rx_error;
  607. }
  608. skb_reserve(skb, 2);
  609. skb_put(skb, len + padding);
  610. if (q->rev >= 8) {
  611. ssb_block_read(dev->dev, skb->data + padding, (len & ~3),
  612. q->mmio_base + B43_PIO8_RXDATA,
  613. sizeof(u32));
  614. if (len & 3) {
  615. u8 *tail = wl->pio_tailspace;
  616. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4);
  617. /* Read the last few bytes. */
  618. ssb_block_read(dev->dev, tail, 4,
  619. q->mmio_base + B43_PIO8_RXDATA,
  620. sizeof(u32));
  621. switch (len & 3) {
  622. case 3:
  623. skb->data[len + padding - 3] = tail[0];
  624. skb->data[len + padding - 2] = tail[1];
  625. skb->data[len + padding - 1] = tail[2];
  626. break;
  627. case 2:
  628. skb->data[len + padding - 2] = tail[0];
  629. skb->data[len + padding - 1] = tail[1];
  630. break;
  631. case 1:
  632. skb->data[len + padding - 1] = tail[0];
  633. break;
  634. }
  635. }
  636. } else {
  637. ssb_block_read(dev->dev, skb->data + padding, (len & ~1),
  638. q->mmio_base + B43_PIO_RXDATA,
  639. sizeof(u16));
  640. if (len & 1) {
  641. u8 *tail = wl->pio_tailspace;
  642. BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2);
  643. /* Read the last byte. */
  644. ssb_block_read(dev->dev, tail, 2,
  645. q->mmio_base + B43_PIO_RXDATA,
  646. sizeof(u16));
  647. skb->data[len + padding - 1] = tail[0];
  648. }
  649. }
  650. b43_rx(q->dev, skb, rxhdr);
  651. return 1;
  652. rx_error:
  653. if (err_msg)
  654. b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
  655. if (q->rev >= 8)
  656. b43_piorx_write32(q, B43_PIO8_RXCTL, B43_PIO8_RXCTL_DATARDY);
  657. else
  658. b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
  659. return 1;
  660. }
  661. void b43_pio_rx(struct b43_pio_rxqueue *q)
  662. {
  663. unsigned int count = 0;
  664. bool stop;
  665. while (1) {
  666. stop = (pio_rx_frame(q) == 0);
  667. if (stop)
  668. break;
  669. cond_resched();
  670. if (WARN_ON_ONCE(++count > 10000))
  671. break;
  672. }
  673. }
  674. static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
  675. {
  676. if (q->rev >= 8) {
  677. b43_piotx_write32(q, B43_PIO8_TXCTL,
  678. b43_piotx_read32(q, B43_PIO8_TXCTL)
  679. | B43_PIO8_TXCTL_SUSPREQ);
  680. } else {
  681. b43_piotx_write16(q, B43_PIO_TXCTL,
  682. b43_piotx_read16(q, B43_PIO_TXCTL)
  683. | B43_PIO_TXCTL_SUSPREQ);
  684. }
  685. }
  686. static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
  687. {
  688. if (q->rev >= 8) {
  689. b43_piotx_write32(q, B43_PIO8_TXCTL,
  690. b43_piotx_read32(q, B43_PIO8_TXCTL)
  691. & ~B43_PIO8_TXCTL_SUSPREQ);
  692. } else {
  693. b43_piotx_write16(q, B43_PIO_TXCTL,
  694. b43_piotx_read16(q, B43_PIO_TXCTL)
  695. & ~B43_PIO_TXCTL_SUSPREQ);
  696. }
  697. }
  698. void b43_pio_tx_suspend(struct b43_wldev *dev)
  699. {
  700. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  701. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
  702. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
  703. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
  704. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
  705. b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
  706. }
  707. void b43_pio_tx_resume(struct b43_wldev *dev)
  708. {
  709. b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
  710. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
  711. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
  712. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
  713. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
  714. b43_power_saving_ctl_bits(dev, 0);
  715. }