pcf50633-core.c 16 KB

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  1. /* NXP PCF50633 Power Management Unit (PMU) driver
  2. *
  3. * (C) 2006-2008 by Openmoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * Balaji Rao <balajirrao@openmoko.org>
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/device.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/module.h>
  18. #include <linux/types.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/workqueue.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/i2c.h>
  23. #include <linux/irq.h>
  24. #include <linux/mfd/pcf50633/core.h>
  25. /* Two MBCS registers used during cold start */
  26. #define PCF50633_REG_MBCS1 0x4b
  27. #define PCF50633_REG_MBCS2 0x4c
  28. #define PCF50633_MBCS1_USBPRES 0x01
  29. #define PCF50633_MBCS1_ADAPTPRES 0x01
  30. static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data)
  31. {
  32. int ret;
  33. ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
  34. num, data);
  35. if (ret < 0)
  36. dev_err(pcf->dev, "Error reading %d regs at %d\n", num, reg);
  37. return ret;
  38. }
  39. static int __pcf50633_write(struct pcf50633 *pcf, u8 reg, int num, u8 *data)
  40. {
  41. int ret;
  42. ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
  43. num, data);
  44. if (ret < 0)
  45. dev_err(pcf->dev, "Error writing %d regs at %d\n", num, reg);
  46. return ret;
  47. }
  48. /* Read a block of upto 32 regs */
  49. int pcf50633_read_block(struct pcf50633 *pcf, u8 reg,
  50. int nr_regs, u8 *data)
  51. {
  52. int ret;
  53. mutex_lock(&pcf->lock);
  54. ret = __pcf50633_read(pcf, reg, nr_regs, data);
  55. mutex_unlock(&pcf->lock);
  56. return ret;
  57. }
  58. EXPORT_SYMBOL_GPL(pcf50633_read_block);
  59. /* Write a block of upto 32 regs */
  60. int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
  61. int nr_regs, u8 *data)
  62. {
  63. int ret;
  64. mutex_lock(&pcf->lock);
  65. ret = __pcf50633_write(pcf, reg, nr_regs, data);
  66. mutex_unlock(&pcf->lock);
  67. return ret;
  68. }
  69. EXPORT_SYMBOL_GPL(pcf50633_write_block);
  70. u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
  71. {
  72. u8 val;
  73. mutex_lock(&pcf->lock);
  74. __pcf50633_read(pcf, reg, 1, &val);
  75. mutex_unlock(&pcf->lock);
  76. return val;
  77. }
  78. EXPORT_SYMBOL_GPL(pcf50633_reg_read);
  79. int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
  80. {
  81. int ret;
  82. mutex_lock(&pcf->lock);
  83. ret = __pcf50633_write(pcf, reg, 1, &val);
  84. mutex_unlock(&pcf->lock);
  85. return ret;
  86. }
  87. EXPORT_SYMBOL_GPL(pcf50633_reg_write);
  88. int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
  89. {
  90. int ret;
  91. u8 tmp;
  92. val &= mask;
  93. mutex_lock(&pcf->lock);
  94. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  95. if (ret < 0)
  96. goto out;
  97. tmp &= ~mask;
  98. tmp |= val;
  99. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  100. out:
  101. mutex_unlock(&pcf->lock);
  102. return ret;
  103. }
  104. EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
  105. int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
  106. {
  107. int ret;
  108. u8 tmp;
  109. mutex_lock(&pcf->lock);
  110. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  111. if (ret < 0)
  112. goto out;
  113. tmp &= ~val;
  114. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  115. out:
  116. mutex_unlock(&pcf->lock);
  117. return ret;
  118. }
  119. EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
  120. /* sysfs attributes */
  121. static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
  122. char *buf)
  123. {
  124. struct pcf50633 *pcf = dev_get_drvdata(dev);
  125. u8 dump[16];
  126. int n, n1, idx = 0;
  127. char *buf1 = buf;
  128. static u8 address_no_read[] = { /* must be ascending */
  129. PCF50633_REG_INT1,
  130. PCF50633_REG_INT2,
  131. PCF50633_REG_INT3,
  132. PCF50633_REG_INT4,
  133. PCF50633_REG_INT5,
  134. 0 /* terminator */
  135. };
  136. for (n = 0; n < 256; n += sizeof(dump)) {
  137. for (n1 = 0; n1 < sizeof(dump); n1++)
  138. if (n == address_no_read[idx]) {
  139. idx++;
  140. dump[n1] = 0x00;
  141. } else
  142. dump[n1] = pcf50633_reg_read(pcf, n + n1);
  143. hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
  144. buf1 += strlen(buf1);
  145. *buf1++ = '\n';
  146. *buf1 = '\0';
  147. }
  148. return buf1 - buf;
  149. }
  150. static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
  151. static ssize_t show_resume_reason(struct device *dev,
  152. struct device_attribute *attr, char *buf)
  153. {
  154. struct pcf50633 *pcf = dev_get_drvdata(dev);
  155. int n;
  156. n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
  157. pcf->resume_reason[0],
  158. pcf->resume_reason[1],
  159. pcf->resume_reason[2],
  160. pcf->resume_reason[3],
  161. pcf->resume_reason[4]);
  162. return n;
  163. }
  164. static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
  165. static struct attribute *pcf_sysfs_entries[] = {
  166. &dev_attr_dump_regs.attr,
  167. &dev_attr_resume_reason.attr,
  168. NULL,
  169. };
  170. static struct attribute_group pcf_attr_group = {
  171. .name = NULL, /* put in device directory */
  172. .attrs = pcf_sysfs_entries,
  173. };
  174. int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
  175. void (*handler) (int, void *), void *data)
  176. {
  177. if (irq < 0 || irq > PCF50633_NUM_IRQ || !handler)
  178. return -EINVAL;
  179. if (WARN_ON(pcf->irq_handler[irq].handler))
  180. return -EBUSY;
  181. mutex_lock(&pcf->lock);
  182. pcf->irq_handler[irq].handler = handler;
  183. pcf->irq_handler[irq].data = data;
  184. mutex_unlock(&pcf->lock);
  185. return 0;
  186. }
  187. EXPORT_SYMBOL_GPL(pcf50633_register_irq);
  188. int pcf50633_free_irq(struct pcf50633 *pcf, int irq)
  189. {
  190. if (irq < 0 || irq > PCF50633_NUM_IRQ)
  191. return -EINVAL;
  192. mutex_lock(&pcf->lock);
  193. pcf->irq_handler[irq].handler = NULL;
  194. mutex_unlock(&pcf->lock);
  195. return 0;
  196. }
  197. EXPORT_SYMBOL_GPL(pcf50633_free_irq);
  198. static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask)
  199. {
  200. u8 reg, bits, tmp;
  201. int ret = 0, idx;
  202. idx = irq >> 3;
  203. reg = PCF50633_REG_INT1M + idx;
  204. bits = 1 << (irq & 0x07);
  205. mutex_lock(&pcf->lock);
  206. if (mask) {
  207. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  208. if (ret < 0)
  209. goto out;
  210. tmp |= bits;
  211. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  212. if (ret < 0)
  213. goto out;
  214. pcf->mask_regs[idx] &= ~bits;
  215. pcf->mask_regs[idx] |= bits;
  216. } else {
  217. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  218. if (ret < 0)
  219. goto out;
  220. tmp &= ~bits;
  221. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  222. if (ret < 0)
  223. goto out;
  224. pcf->mask_regs[idx] &= ~bits;
  225. }
  226. out:
  227. mutex_unlock(&pcf->lock);
  228. return ret;
  229. }
  230. int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
  231. {
  232. dev_info(pcf->dev, "Masking IRQ %d\n", irq);
  233. return __pcf50633_irq_mask_set(pcf, irq, 1);
  234. }
  235. EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
  236. int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
  237. {
  238. dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
  239. return __pcf50633_irq_mask_set(pcf, irq, 0);
  240. }
  241. EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
  242. int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
  243. {
  244. u8 reg, bits;
  245. reg = irq >> 3;
  246. bits = 1 << (irq & 0x07);
  247. return pcf->mask_regs[reg] & bits;
  248. }
  249. EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
  250. static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq)
  251. {
  252. if (pcf->irq_handler[irq].handler)
  253. pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data);
  254. }
  255. /* Maximum amount of time ONKEY is held before emergency action is taken */
  256. #define PCF50633_ONKEY1S_TIMEOUT 8
  257. static void pcf50633_irq_worker(struct work_struct *work)
  258. {
  259. struct pcf50633 *pcf;
  260. int ret, i, j;
  261. u8 pcf_int[5], chgstat;
  262. pcf = container_of(work, struct pcf50633, irq_work);
  263. /* Read the 5 INT regs in one transaction */
  264. ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
  265. ARRAY_SIZE(pcf_int), pcf_int);
  266. if (ret != ARRAY_SIZE(pcf_int)) {
  267. dev_err(pcf->dev, "Error reading INT registers\n");
  268. /*
  269. * If this doesn't ACK the interrupt to the chip, we'll be
  270. * called once again as we're level triggered.
  271. */
  272. goto out;
  273. }
  274. /* defeat 8s death from lowsys on A5 */
  275. pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04);
  276. /* We immediately read the usb and adapter status. We thus make sure
  277. * only of USBINS/USBREM IRQ handlers are called */
  278. if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
  279. chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
  280. if (chgstat & (0x3 << 4))
  281. pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM);
  282. else
  283. pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS);
  284. }
  285. /* Make sure only one of ADPINS or ADPREM is set */
  286. if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
  287. chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
  288. if (chgstat & (0x3 << 4))
  289. pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM);
  290. else
  291. pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS);
  292. }
  293. dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
  294. "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
  295. pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
  296. /* Some revisions of the chip don't have a 8s standby mode on
  297. * ONKEY1S press. We try to manually do it in such cases. */
  298. if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
  299. dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
  300. pcf->onkey1s_held);
  301. if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
  302. if (pcf->pdata->force_shutdown)
  303. pcf->pdata->force_shutdown(pcf);
  304. }
  305. if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
  306. dev_info(pcf->dev, "ONKEY1S held\n");
  307. pcf->onkey1s_held = 1 ;
  308. /* Unmask IRQ_SECOND */
  309. pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
  310. PCF50633_INT1_SECOND);
  311. /* Unmask IRQ_ONKEYR */
  312. pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
  313. PCF50633_INT2_ONKEYR);
  314. }
  315. if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
  316. pcf->onkey1s_held = 0;
  317. /* Mask SECOND and ONKEYR interrupts */
  318. if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
  319. pcf50633_reg_set_bit_mask(pcf,
  320. PCF50633_REG_INT1M,
  321. PCF50633_INT1_SECOND,
  322. PCF50633_INT1_SECOND);
  323. if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
  324. pcf50633_reg_set_bit_mask(pcf,
  325. PCF50633_REG_INT2M,
  326. PCF50633_INT2_ONKEYR,
  327. PCF50633_INT2_ONKEYR);
  328. }
  329. /* Have we just resumed ? */
  330. if (pcf->is_suspended) {
  331. pcf->is_suspended = 0;
  332. /* Set the resume reason filtering out non resumers */
  333. for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
  334. pcf->resume_reason[i] = pcf_int[i] &
  335. pcf->pdata->resumers[i];
  336. /* Make sure we don't pass on any ONKEY events to
  337. * userspace now */
  338. pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
  339. }
  340. for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
  341. /* Unset masked interrupts */
  342. pcf_int[i] &= ~pcf->mask_regs[i];
  343. for (j = 0; j < 8 ; j++)
  344. if (pcf_int[i] & (1 << j))
  345. pcf50633_irq_call_handler(pcf, (i * 8) + j);
  346. }
  347. out:
  348. put_device(pcf->dev);
  349. enable_irq(pcf->irq);
  350. }
  351. static irqreturn_t pcf50633_irq(int irq, void *data)
  352. {
  353. struct pcf50633 *pcf = data;
  354. dev_dbg(pcf->dev, "pcf50633_irq\n");
  355. get_device(pcf->dev);
  356. disable_irq_nosync(pcf->irq);
  357. queue_work(pcf->work_queue, &pcf->irq_work);
  358. return IRQ_HANDLED;
  359. }
  360. static void
  361. pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
  362. struct platform_device **pdev)
  363. {
  364. struct pcf50633_subdev_pdata *subdev_pdata;
  365. int ret;
  366. *pdev = platform_device_alloc(name, -1);
  367. if (!*pdev) {
  368. dev_err(pcf->dev, "Falied to allocate %s\n", name);
  369. return;
  370. }
  371. subdev_pdata = kmalloc(sizeof(*subdev_pdata), GFP_KERNEL);
  372. if (!subdev_pdata) {
  373. dev_err(pcf->dev, "Error allocating subdev pdata\n");
  374. platform_device_put(*pdev);
  375. }
  376. subdev_pdata->pcf = pcf;
  377. platform_device_add_data(*pdev, subdev_pdata, sizeof(*subdev_pdata));
  378. (*pdev)->dev.parent = pcf->dev;
  379. ret = platform_device_add(*pdev);
  380. if (ret) {
  381. dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
  382. platform_device_put(*pdev);
  383. *pdev = NULL;
  384. }
  385. }
  386. #ifdef CONFIG_PM
  387. static int pcf50633_suspend(struct i2c_client *client, pm_message_t state)
  388. {
  389. struct pcf50633 *pcf;
  390. int ret = 0, i;
  391. u8 res[5];
  392. pcf = i2c_get_clientdata(client);
  393. /* Make sure our interrupt handlers are not called
  394. * henceforth */
  395. disable_irq(pcf->irq);
  396. /* Make sure that any running IRQ worker has quit */
  397. cancel_work_sync(&pcf->irq_work);
  398. /* Save the masks */
  399. ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
  400. ARRAY_SIZE(pcf->suspend_irq_masks),
  401. pcf->suspend_irq_masks);
  402. if (ret < 0) {
  403. dev_err(pcf->dev, "error saving irq masks\n");
  404. goto out;
  405. }
  406. /* Write wakeup irq masks */
  407. for (i = 0; i < ARRAY_SIZE(res); i++)
  408. res[i] = ~pcf->pdata->resumers[i];
  409. ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
  410. ARRAY_SIZE(res), &res[0]);
  411. if (ret < 0) {
  412. dev_err(pcf->dev, "error writing wakeup irq masks\n");
  413. goto out;
  414. }
  415. pcf->is_suspended = 1;
  416. out:
  417. return ret;
  418. }
  419. static int pcf50633_resume(struct i2c_client *client)
  420. {
  421. struct pcf50633 *pcf;
  422. int ret;
  423. pcf = i2c_get_clientdata(client);
  424. /* Write the saved mask registers */
  425. ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
  426. ARRAY_SIZE(pcf->suspend_irq_masks),
  427. pcf->suspend_irq_masks);
  428. if (ret < 0)
  429. dev_err(pcf->dev, "Error restoring saved suspend masks\n");
  430. /* Restore regulators' state */
  431. get_device(pcf->dev);
  432. /*
  433. * Clear any pending interrupts and set resume reason if any.
  434. * This will leave with enable_irq()
  435. */
  436. pcf50633_irq_worker(&pcf->irq_work);
  437. return 0;
  438. }
  439. #else
  440. #define pcf50633_suspend NULL
  441. #define pcf50633_resume NULL
  442. #endif
  443. static int __devinit pcf50633_probe(struct i2c_client *client,
  444. const struct i2c_device_id *ids)
  445. {
  446. struct pcf50633 *pcf;
  447. struct pcf50633_platform_data *pdata = client->dev.platform_data;
  448. int i, ret = 0;
  449. int version, variant;
  450. pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
  451. if (!pcf)
  452. return -ENOMEM;
  453. pcf->pdata = pdata;
  454. mutex_init(&pcf->lock);
  455. i2c_set_clientdata(client, pcf);
  456. pcf->dev = &client->dev;
  457. pcf->i2c_client = client;
  458. pcf->irq = client->irq;
  459. pcf->work_queue = create_singlethread_workqueue("pcf50633");
  460. INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
  461. version = pcf50633_reg_read(pcf, 0);
  462. variant = pcf50633_reg_read(pcf, 1);
  463. if (version < 0 || variant < 0) {
  464. dev_err(pcf->dev, "Unable to probe pcf50633\n");
  465. ret = -ENODEV;
  466. goto err;
  467. }
  468. dev_info(pcf->dev, "Probed device version %d variant %d\n",
  469. version, variant);
  470. /* Enable all interrupts except RTC SECOND */
  471. pcf->mask_regs[0] = 0x80;
  472. pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]);
  473. pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
  474. pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
  475. pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
  476. pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
  477. /* Create sub devices */
  478. pcf50633_client_dev_register(pcf, "pcf50633-input",
  479. &pcf->input_pdev);
  480. pcf50633_client_dev_register(pcf, "pcf50633-rtc",
  481. &pcf->rtc_pdev);
  482. pcf50633_client_dev_register(pcf, "pcf50633-mbc",
  483. &pcf->mbc_pdev);
  484. pcf50633_client_dev_register(pcf, "pcf50633-adc",
  485. &pcf->adc_pdev);
  486. for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
  487. struct platform_device *pdev;
  488. pdev = platform_device_alloc("pcf50633-regltr", i);
  489. if (!pdev) {
  490. dev_err(pcf->dev, "Cannot create regulator\n");
  491. continue;
  492. }
  493. pdev->dev.parent = pcf->dev;
  494. pdev->dev.platform_data = &pdata->reg_init_data[i];
  495. dev_set_drvdata(&pdev->dev, pcf);
  496. pcf->regulator_pdev[i] = pdev;
  497. platform_device_add(pdev);
  498. }
  499. if (client->irq) {
  500. ret = request_irq(client->irq, pcf50633_irq,
  501. IRQF_TRIGGER_LOW, "pcf50633", pcf);
  502. if (ret) {
  503. dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
  504. goto err;
  505. }
  506. } else {
  507. dev_err(pcf->dev, "No IRQ configured\n");
  508. goto err;
  509. }
  510. if (enable_irq_wake(client->irq) < 0)
  511. dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
  512. "in this hardware revision", client->irq);
  513. ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
  514. if (ret)
  515. dev_err(pcf->dev, "error creating sysfs entries\n");
  516. if (pdata->probe_done)
  517. pdata->probe_done(pcf);
  518. return 0;
  519. err:
  520. destroy_workqueue(pcf->work_queue);
  521. kfree(pcf);
  522. return ret;
  523. }
  524. static int __devexit pcf50633_remove(struct i2c_client *client)
  525. {
  526. struct pcf50633 *pcf = i2c_get_clientdata(client);
  527. int i;
  528. free_irq(pcf->irq, pcf);
  529. destroy_workqueue(pcf->work_queue);
  530. platform_device_unregister(pcf->input_pdev);
  531. platform_device_unregister(pcf->rtc_pdev);
  532. platform_device_unregister(pcf->mbc_pdev);
  533. platform_device_unregister(pcf->adc_pdev);
  534. for (i = 0; i < PCF50633_NUM_REGULATORS; i++)
  535. platform_device_unregister(pcf->regulator_pdev[i]);
  536. kfree(pcf);
  537. return 0;
  538. }
  539. static struct i2c_device_id pcf50633_id_table[] = {
  540. {"pcf50633", 0x73},
  541. {/* end of list */}
  542. };
  543. static struct i2c_driver pcf50633_driver = {
  544. .driver = {
  545. .name = "pcf50633",
  546. },
  547. .id_table = pcf50633_id_table,
  548. .probe = pcf50633_probe,
  549. .remove = __devexit_p(pcf50633_remove),
  550. .suspend = pcf50633_suspend,
  551. .resume = pcf50633_resume,
  552. };
  553. static int __init pcf50633_init(void)
  554. {
  555. return i2c_add_driver(&pcf50633_driver);
  556. }
  557. static void __exit pcf50633_exit(void)
  558. {
  559. i2c_del_driver(&pcf50633_driver);
  560. }
  561. MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
  562. MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
  563. MODULE_LICENSE("GPL");
  564. subsys_initcall(pcf50633_init);
  565. module_exit(pcf50633_exit);