em28xx-core.c 31 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include <media/v4l2-common.h>
  25. #include "em28xx.h"
  26. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  27. static unsigned int core_debug;
  28. module_param(core_debug, int, 0644);
  29. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  30. #define em28xx_coredbg(fmt, arg...) do {\
  31. if (core_debug) \
  32. printk(KERN_INFO "%s %s :"fmt, \
  33. dev->name, __func__ , ##arg); } while (0)
  34. static unsigned int reg_debug;
  35. module_param(reg_debug, int, 0644);
  36. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  37. #define em28xx_regdbg(fmt, arg...) do {\
  38. if (reg_debug) \
  39. printk(KERN_INFO "%s %s :"fmt, \
  40. dev->name, __func__ , ##arg); } while (0)
  41. static int alt;
  42. module_param(alt, int, 0644);
  43. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  44. static unsigned int disable_vbi;
  45. module_param(disable_vbi, int, 0644);
  46. MODULE_PARM_DESC(disable_vbi, "disable vbi support");
  47. /* FIXME */
  48. #define em28xx_isocdbg(fmt, arg...) do {\
  49. if (core_debug) \
  50. printk(KERN_INFO "%s %s :"fmt, \
  51. dev->name, __func__ , ##arg); } while (0)
  52. /*
  53. * em28xx_read_reg_req()
  54. * reads data from the usb device specifying bRequest
  55. */
  56. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  57. char *buf, int len)
  58. {
  59. int ret;
  60. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  61. if (dev->state & DEV_DISCONNECTED)
  62. return -ENODEV;
  63. if (len > URB_MAX_CTRL_SIZE)
  64. return -EINVAL;
  65. if (reg_debug) {
  66. printk(KERN_DEBUG "(pipe 0x%08x): "
  67. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  68. pipe,
  69. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  70. req, 0, 0,
  71. reg & 0xff, reg >> 8,
  72. len & 0xff, len >> 8);
  73. }
  74. mutex_lock(&dev->ctrl_urb_lock);
  75. ret = usb_control_msg(dev->udev, pipe, req,
  76. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  77. 0x0000, reg, dev->urb_buf, len, HZ);
  78. if (ret < 0) {
  79. if (reg_debug)
  80. printk(" failed!\n");
  81. mutex_unlock(&dev->ctrl_urb_lock);
  82. return ret;
  83. }
  84. if (len)
  85. memcpy(buf, dev->urb_buf, len);
  86. mutex_unlock(&dev->ctrl_urb_lock);
  87. if (reg_debug) {
  88. int byte;
  89. printk("<<<");
  90. for (byte = 0; byte < len; byte++)
  91. printk(" %02x", (unsigned char)buf[byte]);
  92. printk("\n");
  93. }
  94. return ret;
  95. }
  96. /*
  97. * em28xx_read_reg_req()
  98. * reads data from the usb device specifying bRequest
  99. */
  100. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  101. {
  102. int ret;
  103. u8 val;
  104. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  105. if (ret < 0)
  106. return ret;
  107. return val;
  108. }
  109. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  110. {
  111. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  112. }
  113. /*
  114. * em28xx_write_regs_req()
  115. * sends data to the usb device, specifying bRequest
  116. */
  117. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  118. int len)
  119. {
  120. int ret;
  121. int pipe = usb_sndctrlpipe(dev->udev, 0);
  122. if (dev->state & DEV_DISCONNECTED)
  123. return -ENODEV;
  124. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  125. return -EINVAL;
  126. if (reg_debug) {
  127. int byte;
  128. printk(KERN_DEBUG "(pipe 0x%08x): "
  129. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  130. pipe,
  131. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  132. req, 0, 0,
  133. reg & 0xff, reg >> 8,
  134. len & 0xff, len >> 8);
  135. for (byte = 0; byte < len; byte++)
  136. printk(" %02x", (unsigned char)buf[byte]);
  137. printk("\n");
  138. }
  139. mutex_lock(&dev->ctrl_urb_lock);
  140. memcpy(dev->urb_buf, buf, len);
  141. ret = usb_control_msg(dev->udev, pipe, req,
  142. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  143. 0x0000, reg, dev->urb_buf, len, HZ);
  144. mutex_unlock(&dev->ctrl_urb_lock);
  145. if (dev->wait_after_write)
  146. msleep(dev->wait_after_write);
  147. return ret;
  148. }
  149. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  150. {
  151. int rc;
  152. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  153. /* Stores GPO/GPIO values at the cache, if changed
  154. Only write values should be stored, since input on a GPIO
  155. register will return the input bits.
  156. Not sure what happens on reading GPO register.
  157. */
  158. if (rc >= 0) {
  159. if (reg == dev->reg_gpo_num)
  160. dev->reg_gpo = buf[0];
  161. else if (reg == dev->reg_gpio_num)
  162. dev->reg_gpio = buf[0];
  163. }
  164. return rc;
  165. }
  166. /* Write a single register */
  167. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  168. {
  169. return em28xx_write_regs(dev, reg, &val, 1);
  170. }
  171. /*
  172. * em28xx_write_reg_bits()
  173. * sets only some bits (specified by bitmask) of a register, by first reading
  174. * the actual value
  175. */
  176. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  177. u8 bitmask)
  178. {
  179. int oldval;
  180. u8 newval;
  181. /* Uses cache for gpo/gpio registers */
  182. if (reg == dev->reg_gpo_num)
  183. oldval = dev->reg_gpo;
  184. else if (reg == dev->reg_gpio_num)
  185. oldval = dev->reg_gpio;
  186. else
  187. oldval = em28xx_read_reg(dev, reg);
  188. if (oldval < 0)
  189. return oldval;
  190. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  191. return em28xx_write_regs(dev, reg, &newval, 1);
  192. }
  193. /*
  194. * em28xx_is_ac97_ready()
  195. * Checks if ac97 is ready
  196. */
  197. static int em28xx_is_ac97_ready(struct em28xx *dev)
  198. {
  199. int ret, i;
  200. /* Wait up to 50 ms for AC97 command to complete */
  201. for (i = 0; i < 10; i++, msleep(5)) {
  202. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  203. if (ret < 0)
  204. return ret;
  205. if (!(ret & 0x01))
  206. return 0;
  207. }
  208. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  209. return -EBUSY;
  210. }
  211. /*
  212. * em28xx_read_ac97()
  213. * write a 16 bit value to the specified AC97 address (LSB first!)
  214. */
  215. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  216. {
  217. int ret;
  218. u8 addr = (reg & 0x7f) | 0x80;
  219. u16 val;
  220. ret = em28xx_is_ac97_ready(dev);
  221. if (ret < 0)
  222. return ret;
  223. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  224. if (ret < 0)
  225. return ret;
  226. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  227. (u8 *)&val, sizeof(val));
  228. if (ret < 0)
  229. return ret;
  230. return le16_to_cpu(val);
  231. }
  232. /*
  233. * em28xx_write_ac97()
  234. * write a 16 bit value to the specified AC97 address (LSB first!)
  235. */
  236. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  237. {
  238. int ret;
  239. u8 addr = reg & 0x7f;
  240. __le16 value;
  241. value = cpu_to_le16(val);
  242. ret = em28xx_is_ac97_ready(dev);
  243. if (ret < 0)
  244. return ret;
  245. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  246. if (ret < 0)
  247. return ret;
  248. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  249. if (ret < 0)
  250. return ret;
  251. return 0;
  252. }
  253. struct em28xx_vol_table {
  254. enum em28xx_amux mux;
  255. u8 reg;
  256. };
  257. static struct em28xx_vol_table inputs[] = {
  258. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  259. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  260. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  261. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  262. { EM28XX_AMUX_CD, AC97_CD_VOL },
  263. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  264. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  265. };
  266. static int set_ac97_input(struct em28xx *dev)
  267. {
  268. int ret, i;
  269. enum em28xx_amux amux = dev->ctl_ainput;
  270. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  271. em28xx should point to LINE IN, while AC97 should use VIDEO
  272. */
  273. if (amux == EM28XX_AMUX_VIDEO2)
  274. amux = EM28XX_AMUX_VIDEO;
  275. /* Mute all entres but the one that were selected */
  276. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  277. if (amux == inputs[i].mux)
  278. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  279. else
  280. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  281. if (ret < 0)
  282. em28xx_warn("couldn't setup AC97 register %d\n",
  283. inputs[i].reg);
  284. }
  285. return 0;
  286. }
  287. static int em28xx_set_audio_source(struct em28xx *dev)
  288. {
  289. int ret;
  290. u8 input;
  291. if (dev->board.is_em2800) {
  292. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  293. input = EM2800_AUDIO_SRC_TUNER;
  294. else
  295. input = EM2800_AUDIO_SRC_LINE;
  296. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  297. if (ret < 0)
  298. return ret;
  299. }
  300. if (dev->board.has_msp34xx)
  301. input = EM28XX_AUDIO_SRC_TUNER;
  302. else {
  303. switch (dev->ctl_ainput) {
  304. case EM28XX_AMUX_VIDEO:
  305. input = EM28XX_AUDIO_SRC_TUNER;
  306. break;
  307. default:
  308. input = EM28XX_AUDIO_SRC_LINE;
  309. break;
  310. }
  311. }
  312. if (dev->board.mute_gpio && dev->mute)
  313. em28xx_gpio_set(dev, dev->board.mute_gpio);
  314. else
  315. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  316. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  317. if (ret < 0)
  318. return ret;
  319. msleep(5);
  320. switch (dev->audio_mode.ac97) {
  321. case EM28XX_NO_AC97:
  322. break;
  323. default:
  324. ret = set_ac97_input(dev);
  325. }
  326. return ret;
  327. }
  328. static const struct em28xx_vol_table outputs[] = {
  329. { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
  330. { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
  331. { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
  332. { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
  333. { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
  334. };
  335. int em28xx_audio_analog_set(struct em28xx *dev)
  336. {
  337. int ret, i;
  338. u8 xclk;
  339. if (!dev->audio_mode.has_audio)
  340. return 0;
  341. /* It is assumed that all devices use master volume for output.
  342. It would be possible to use also line output.
  343. */
  344. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  345. /* Mute all outputs */
  346. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  347. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  348. if (ret < 0)
  349. em28xx_warn("couldn't setup AC97 register %d\n",
  350. outputs[i].reg);
  351. }
  352. }
  353. xclk = dev->board.xclk & 0x7f;
  354. if (!dev->mute)
  355. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  356. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  357. if (ret < 0)
  358. return ret;
  359. msleep(10);
  360. /* Selects the proper audio input */
  361. ret = em28xx_set_audio_source(dev);
  362. /* Sets volume */
  363. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  364. int vol;
  365. em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
  366. em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
  367. em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
  368. /* LSB: left channel - both channels with the same level */
  369. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  370. /* Mute device, if needed */
  371. if (dev->mute)
  372. vol |= 0x8000;
  373. /* Sets volume */
  374. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  375. if (dev->ctl_aoutput & outputs[i].mux)
  376. ret = em28xx_write_ac97(dev, outputs[i].reg,
  377. vol);
  378. if (ret < 0)
  379. em28xx_warn("couldn't setup AC97 register %d\n",
  380. outputs[i].reg);
  381. }
  382. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  383. int sel = ac97_return_record_select(dev->ctl_aoutput);
  384. /* Use the same input for both left and right
  385. channels */
  386. sel |= (sel << 8);
  387. em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
  388. }
  389. }
  390. return ret;
  391. }
  392. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  393. int em28xx_audio_setup(struct em28xx *dev)
  394. {
  395. int vid1, vid2, feat, cfg;
  396. u32 vid;
  397. if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
  398. /* Digital only device - don't load any alsa module */
  399. dev->audio_mode.has_audio = 0;
  400. dev->has_audio_class = 0;
  401. dev->has_alsa_audio = 0;
  402. return 0;
  403. }
  404. /* If device doesn't support Usb Audio Class, use vendor class */
  405. if (!dev->has_audio_class)
  406. dev->has_alsa_audio = 1;
  407. dev->audio_mode.has_audio = 1;
  408. /* See how this device is configured */
  409. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  410. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  411. if (cfg < 0) {
  412. /* Register read error? */
  413. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  414. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  415. /* The device doesn't have vendor audio at all */
  416. dev->has_alsa_audio = 0;
  417. dev->audio_mode.has_audio = 0;
  418. return 0;
  419. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  420. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  421. em28xx_info("I2S Audio (3 sample rates)\n");
  422. dev->audio_mode.i2s_3rates = 1;
  423. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  424. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  425. em28xx_info("I2S Audio (5 sample rates)\n");
  426. dev->audio_mode.i2s_5rates = 1;
  427. }
  428. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  429. /* Skip the code that does AC97 vendor detection */
  430. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  431. goto init_audio;
  432. }
  433. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  434. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  435. if (vid1 < 0) {
  436. /*
  437. * Device likely doesn't support AC97
  438. * Note: (some) em2800 devices without eeprom reports 0x91 on
  439. * CHIPCFG register, even not having an AC97 chip
  440. */
  441. em28xx_warn("AC97 chip type couldn't be determined\n");
  442. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  443. dev->has_alsa_audio = 0;
  444. dev->audio_mode.has_audio = 0;
  445. goto init_audio;
  446. }
  447. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  448. if (vid2 < 0)
  449. goto init_audio;
  450. vid = vid1 << 16 | vid2;
  451. dev->audio_mode.ac97_vendor_id = vid;
  452. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  453. feat = em28xx_read_ac97(dev, AC97_RESET);
  454. if (feat < 0)
  455. goto init_audio;
  456. dev->audio_mode.ac97_feat = feat;
  457. em28xx_warn("AC97 features = 0x%04x\n", feat);
  458. /* Try to identify what audio processor we have */
  459. if ((vid == 0xffffffff) && (feat == 0x6a90))
  460. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  461. else if ((vid >> 8) == 0x838476)
  462. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  463. init_audio:
  464. /* Reports detected AC97 processor */
  465. switch (dev->audio_mode.ac97) {
  466. case EM28XX_NO_AC97:
  467. em28xx_info("No AC97 audio processor\n");
  468. break;
  469. case EM28XX_AC97_EM202:
  470. em28xx_info("Empia 202 AC97 audio processor detected\n");
  471. break;
  472. case EM28XX_AC97_SIGMATEL:
  473. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  474. dev->audio_mode.ac97_vendor_id & 0xff);
  475. break;
  476. case EM28XX_AC97_OTHER:
  477. em28xx_warn("Unknown AC97 audio processor detected!\n");
  478. break;
  479. default:
  480. break;
  481. }
  482. return em28xx_audio_analog_set(dev);
  483. }
  484. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  485. int em28xx_colorlevels_set_default(struct em28xx *dev)
  486. {
  487. em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
  488. em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
  489. em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
  490. em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
  491. em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
  492. em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
  493. em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
  494. em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
  495. em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
  496. em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
  497. em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
  498. em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
  499. return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
  500. }
  501. int em28xx_capture_start(struct em28xx *dev, int start)
  502. {
  503. int rc;
  504. if (dev->chip_id == CHIP_ID_EM2874) {
  505. /* The Transport Stream Enable Register moved in em2874 */
  506. if (!start) {
  507. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  508. 0x00,
  509. EM2874_TS1_CAPTURE_ENABLE);
  510. return rc;
  511. }
  512. /* Enable Transport Stream */
  513. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  514. EM2874_TS1_CAPTURE_ENABLE,
  515. EM2874_TS1_CAPTURE_ENABLE);
  516. return rc;
  517. }
  518. /* FIXME: which is the best order? */
  519. /* video registers are sampled by VREF */
  520. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  521. start ? 0x10 : 0x00, 0x10);
  522. if (rc < 0)
  523. return rc;
  524. if (!start) {
  525. /* disable video capture */
  526. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  527. return rc;
  528. }
  529. if (dev->board.is_webcam)
  530. rc = em28xx_write_reg(dev, 0x13, 0x0c);
  531. /* enable video capture */
  532. rc = em28xx_write_reg(dev, 0x48, 0x00);
  533. if (dev->mode == EM28XX_ANALOG_MODE)
  534. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  535. else
  536. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  537. msleep(6);
  538. return rc;
  539. }
  540. int em28xx_vbi_supported(struct em28xx *dev)
  541. {
  542. /* Modprobe option to manually disable */
  543. if (disable_vbi == 1)
  544. return 0;
  545. if (dev->chip_id == CHIP_ID_EM2860 ||
  546. dev->chip_id == CHIP_ID_EM2883)
  547. return 1;
  548. /* Version of em28xx that does not support VBI */
  549. return 0;
  550. }
  551. int em28xx_set_outfmt(struct em28xx *dev)
  552. {
  553. int ret;
  554. u8 vinctrl;
  555. ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
  556. dev->format->reg | 0x20, 0xff);
  557. if (ret < 0)
  558. return ret;
  559. ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
  560. if (ret < 0)
  561. return ret;
  562. vinctrl = dev->vinctl;
  563. if (em28xx_vbi_supported(dev) == 1) {
  564. vinctrl |= EM28XX_VINCTRL_VBI_RAW;
  565. em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
  566. em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
  567. em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, 0xb4);
  568. em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, 0x0c);
  569. }
  570. return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
  571. }
  572. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  573. u8 ymin, u8 ymax)
  574. {
  575. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  576. xmin, ymin, xmax, ymax);
  577. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  578. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  579. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  580. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  581. }
  582. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  583. u16 width, u16 height)
  584. {
  585. u8 cwidth = width;
  586. u8 cheight = height;
  587. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  588. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  589. (width | (overflow & 2) << 7),
  590. (height | (overflow & 1) << 8));
  591. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  592. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  593. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  594. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  595. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  596. }
  597. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  598. {
  599. u8 mode;
  600. /* the em2800 scaler only supports scaling down to 50% */
  601. if (dev->board.is_em2800) {
  602. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  603. } else {
  604. u8 buf[2];
  605. buf[0] = h;
  606. buf[1] = h >> 8;
  607. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  608. buf[0] = v;
  609. buf[1] = v >> 8;
  610. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  611. /* it seems that both H and V scalers must be active
  612. to work correctly */
  613. mode = (h || v) ? 0x30 : 0x00;
  614. }
  615. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  616. }
  617. /* FIXME: this only function read values from dev */
  618. int em28xx_resolution_set(struct em28xx *dev)
  619. {
  620. int width, height;
  621. width = norm_maxw(dev);
  622. height = norm_maxh(dev);
  623. if (!dev->progressive)
  624. height >>= norm_maxh(dev);
  625. em28xx_set_outfmt(dev);
  626. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  627. /* If we don't set the start position to 4 in VBI mode, we end up
  628. with line 21 being YUYV encoded instead of being in 8-bit
  629. greyscale */
  630. if (em28xx_vbi_supported(dev) == 1)
  631. em28xx_capture_area_set(dev, 0, 4, width >> 2, height >> 2);
  632. else
  633. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  634. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  635. }
  636. int em28xx_set_alternate(struct em28xx *dev)
  637. {
  638. int errCode, prev_alt = dev->alt;
  639. int i;
  640. unsigned int min_pkt_size = dev->width * 2 + 4;
  641. /*
  642. * alt = 0 is used only for control messages, so, only values
  643. * greater than 0 can be used for streaming.
  644. */
  645. if (alt && alt < dev->num_alt) {
  646. em28xx_coredbg("alternate forced to %d\n", dev->alt);
  647. dev->alt = alt;
  648. goto set_alt;
  649. }
  650. /* When image size is bigger than a certain value,
  651. the frame size should be increased, otherwise, only
  652. green screen will be received.
  653. */
  654. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  655. min_pkt_size *= 2;
  656. for (i = 0; i < dev->num_alt; i++) {
  657. /* stop when the selected alt setting offers enough bandwidth */
  658. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  659. dev->alt = i;
  660. break;
  661. /* otherwise make sure that we end up with the maximum bandwidth
  662. because the min_pkt_size equation might be wrong...
  663. */
  664. } else if (dev->alt_max_pkt_size[i] >
  665. dev->alt_max_pkt_size[dev->alt])
  666. dev->alt = i;
  667. }
  668. set_alt:
  669. if (dev->alt != prev_alt) {
  670. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  671. min_pkt_size, dev->alt);
  672. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  673. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  674. dev->alt, dev->max_pkt_size);
  675. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  676. if (errCode < 0) {
  677. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  678. dev->alt, errCode);
  679. return errCode;
  680. }
  681. }
  682. return 0;
  683. }
  684. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  685. {
  686. int rc = 0;
  687. if (!gpio)
  688. return rc;
  689. if (dev->mode != EM28XX_SUSPEND) {
  690. em28xx_write_reg(dev, 0x48, 0x00);
  691. if (dev->mode == EM28XX_ANALOG_MODE)
  692. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  693. else
  694. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  695. msleep(6);
  696. }
  697. /* Send GPIO reset sequences specified at board entry */
  698. while (gpio->sleep >= 0) {
  699. if (gpio->reg >= 0) {
  700. rc = em28xx_write_reg_bits(dev,
  701. gpio->reg,
  702. gpio->val,
  703. gpio->mask);
  704. if (rc < 0)
  705. return rc;
  706. }
  707. if (gpio->sleep > 0)
  708. msleep(gpio->sleep);
  709. gpio++;
  710. }
  711. return rc;
  712. }
  713. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  714. {
  715. if (dev->mode == set_mode)
  716. return 0;
  717. if (set_mode == EM28XX_SUSPEND) {
  718. dev->mode = set_mode;
  719. /* FIXME: add suspend support for ac97 */
  720. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  721. }
  722. dev->mode = set_mode;
  723. if (dev->mode == EM28XX_DIGITAL_MODE)
  724. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  725. else
  726. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  727. }
  728. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  729. /* ------------------------------------------------------------------
  730. URB control
  731. ------------------------------------------------------------------*/
  732. /*
  733. * IRQ callback, called by URB callback
  734. */
  735. static void em28xx_irq_callback(struct urb *urb)
  736. {
  737. struct em28xx *dev = urb->context;
  738. int rc, i;
  739. switch (urb->status) {
  740. case 0: /* success */
  741. case -ETIMEDOUT: /* NAK */
  742. break;
  743. case -ECONNRESET: /* kill */
  744. case -ENOENT:
  745. case -ESHUTDOWN:
  746. return;
  747. default: /* error */
  748. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  749. break;
  750. }
  751. /* Copy data from URB */
  752. spin_lock(&dev->slock);
  753. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  754. spin_unlock(&dev->slock);
  755. /* Reset urb buffers */
  756. for (i = 0; i < urb->number_of_packets; i++) {
  757. urb->iso_frame_desc[i].status = 0;
  758. urb->iso_frame_desc[i].actual_length = 0;
  759. }
  760. urb->status = 0;
  761. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  762. if (urb->status) {
  763. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  764. urb->status);
  765. }
  766. }
  767. /*
  768. * Stop and Deallocate URBs
  769. */
  770. void em28xx_uninit_isoc(struct em28xx *dev)
  771. {
  772. struct urb *urb;
  773. int i;
  774. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  775. dev->isoc_ctl.nfields = -1;
  776. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  777. urb = dev->isoc_ctl.urb[i];
  778. if (urb) {
  779. if (!irqs_disabled())
  780. usb_kill_urb(urb);
  781. else
  782. usb_unlink_urb(urb);
  783. if (dev->isoc_ctl.transfer_buffer[i]) {
  784. usb_buffer_free(dev->udev,
  785. urb->transfer_buffer_length,
  786. dev->isoc_ctl.transfer_buffer[i],
  787. urb->transfer_dma);
  788. }
  789. usb_free_urb(urb);
  790. dev->isoc_ctl.urb[i] = NULL;
  791. }
  792. dev->isoc_ctl.transfer_buffer[i] = NULL;
  793. }
  794. kfree(dev->isoc_ctl.urb);
  795. kfree(dev->isoc_ctl.transfer_buffer);
  796. dev->isoc_ctl.urb = NULL;
  797. dev->isoc_ctl.transfer_buffer = NULL;
  798. dev->isoc_ctl.num_bufs = 0;
  799. em28xx_capture_start(dev, 0);
  800. }
  801. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  802. /*
  803. * Allocate URBs and start IRQ
  804. */
  805. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  806. int num_bufs, int max_pkt_size,
  807. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  808. {
  809. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  810. struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
  811. int i;
  812. int sb_size, pipe;
  813. struct urb *urb;
  814. int j, k;
  815. int rc;
  816. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  817. /* De-allocates all pending stuff */
  818. em28xx_uninit_isoc(dev);
  819. dev->isoc_ctl.isoc_copy = isoc_copy;
  820. dev->isoc_ctl.num_bufs = num_bufs;
  821. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  822. if (!dev->isoc_ctl.urb) {
  823. em28xx_errdev("cannot alloc memory for usb buffers\n");
  824. return -ENOMEM;
  825. }
  826. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  827. GFP_KERNEL);
  828. if (!dev->isoc_ctl.transfer_buffer) {
  829. em28xx_errdev("cannot allocate memory for usb transfer\n");
  830. kfree(dev->isoc_ctl.urb);
  831. return -ENOMEM;
  832. }
  833. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  834. dev->isoc_ctl.vid_buf = NULL;
  835. dev->isoc_ctl.vbi_buf = NULL;
  836. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  837. /* allocate urbs and transfer buffers */
  838. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  839. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  840. if (!urb) {
  841. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  842. em28xx_uninit_isoc(dev);
  843. return -ENOMEM;
  844. }
  845. dev->isoc_ctl.urb[i] = urb;
  846. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  847. sb_size, GFP_KERNEL, &urb->transfer_dma);
  848. if (!dev->isoc_ctl.transfer_buffer[i]) {
  849. em28xx_err("unable to allocate %i bytes for transfer"
  850. " buffer %i%s\n",
  851. sb_size, i,
  852. in_interrupt() ? " while in int" : "");
  853. em28xx_uninit_isoc(dev);
  854. return -ENOMEM;
  855. }
  856. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  857. /* FIXME: this is a hack - should be
  858. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  859. should also be using 'desc.bInterval'
  860. */
  861. pipe = usb_rcvisocpipe(dev->udev,
  862. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  863. usb_fill_int_urb(urb, dev->udev, pipe,
  864. dev->isoc_ctl.transfer_buffer[i], sb_size,
  865. em28xx_irq_callback, dev, 1);
  866. urb->number_of_packets = max_packets;
  867. urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
  868. k = 0;
  869. for (j = 0; j < max_packets; j++) {
  870. urb->iso_frame_desc[j].offset = k;
  871. urb->iso_frame_desc[j].length =
  872. dev->isoc_ctl.max_pkt_size;
  873. k += dev->isoc_ctl.max_pkt_size;
  874. }
  875. }
  876. init_waitqueue_head(&dma_q->wq);
  877. init_waitqueue_head(&vbi_dma_q->wq);
  878. em28xx_capture_start(dev, 1);
  879. /* submit urbs and enables IRQ */
  880. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  881. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  882. if (rc) {
  883. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  884. rc);
  885. em28xx_uninit_isoc(dev);
  886. return rc;
  887. }
  888. }
  889. return 0;
  890. }
  891. EXPORT_SYMBOL_GPL(em28xx_init_isoc);
  892. /* Determine the packet size for the DVB stream for the given device
  893. (underlying value programmed into the eeprom) */
  894. int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
  895. {
  896. unsigned int chip_cfg2;
  897. unsigned int packet_size = 564;
  898. if (dev->chip_id == CHIP_ID_EM2874) {
  899. /* FIXME - for now assume 564 like it was before, but the
  900. em2874 code should be added to return the proper value... */
  901. packet_size = 564;
  902. } else {
  903. /* TS max packet size stored in bits 1-0 of R01 */
  904. chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
  905. switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
  906. case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
  907. packet_size = 188;
  908. break;
  909. case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
  910. packet_size = 376;
  911. break;
  912. case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
  913. packet_size = 564;
  914. break;
  915. case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
  916. packet_size = 752;
  917. break;
  918. }
  919. }
  920. em28xx_coredbg("dvb max packet size=%d\n", packet_size);
  921. return packet_size;
  922. }
  923. EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
  924. /*
  925. * em28xx_wake_i2c()
  926. * configure i2c attached devices
  927. */
  928. void em28xx_wake_i2c(struct em28xx *dev)
  929. {
  930. v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
  931. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
  932. INPUT(dev->ctl_input)->vmux, 0, 0);
  933. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
  934. }
  935. /*
  936. * Device control list
  937. */
  938. static LIST_HEAD(em28xx_devlist);
  939. static DEFINE_MUTEX(em28xx_devlist_mutex);
  940. struct em28xx *em28xx_get_device(int minor,
  941. enum v4l2_buf_type *fh_type,
  942. int *has_radio)
  943. {
  944. struct em28xx *h, *dev = NULL;
  945. *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  946. *has_radio = 0;
  947. mutex_lock(&em28xx_devlist_mutex);
  948. list_for_each_entry(h, &em28xx_devlist, devlist) {
  949. if (h->vdev->minor == minor)
  950. dev = h;
  951. if (h->vbi_dev && h->vbi_dev->minor == minor) {
  952. dev = h;
  953. *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
  954. }
  955. if (h->radio_dev &&
  956. h->radio_dev->minor == minor) {
  957. dev = h;
  958. *has_radio = 1;
  959. }
  960. }
  961. mutex_unlock(&em28xx_devlist_mutex);
  962. return dev;
  963. }
  964. /*
  965. * em28xx_realease_resources()
  966. * unregisters the v4l2,i2c and usb devices
  967. * called when the device gets disconected or at module unload
  968. */
  969. void em28xx_remove_from_devlist(struct em28xx *dev)
  970. {
  971. mutex_lock(&em28xx_devlist_mutex);
  972. list_del(&dev->devlist);
  973. mutex_unlock(&em28xx_devlist_mutex);
  974. };
  975. void em28xx_add_into_devlist(struct em28xx *dev)
  976. {
  977. mutex_lock(&em28xx_devlist_mutex);
  978. list_add_tail(&dev->devlist, &em28xx_devlist);
  979. mutex_unlock(&em28xx_devlist_mutex);
  980. };
  981. /*
  982. * Extension interface
  983. */
  984. static LIST_HEAD(em28xx_extension_devlist);
  985. static DEFINE_MUTEX(em28xx_extension_devlist_lock);
  986. int em28xx_register_extension(struct em28xx_ops *ops)
  987. {
  988. struct em28xx *dev = NULL;
  989. mutex_lock(&em28xx_devlist_mutex);
  990. mutex_lock(&em28xx_extension_devlist_lock);
  991. list_add_tail(&ops->next, &em28xx_extension_devlist);
  992. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  993. if (dev)
  994. ops->init(dev);
  995. }
  996. printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
  997. mutex_unlock(&em28xx_extension_devlist_lock);
  998. mutex_unlock(&em28xx_devlist_mutex);
  999. return 0;
  1000. }
  1001. EXPORT_SYMBOL(em28xx_register_extension);
  1002. void em28xx_unregister_extension(struct em28xx_ops *ops)
  1003. {
  1004. struct em28xx *dev = NULL;
  1005. mutex_lock(&em28xx_devlist_mutex);
  1006. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  1007. if (dev)
  1008. ops->fini(dev);
  1009. }
  1010. mutex_lock(&em28xx_extension_devlist_lock);
  1011. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  1012. list_del(&ops->next);
  1013. mutex_unlock(&em28xx_extension_devlist_lock);
  1014. mutex_unlock(&em28xx_devlist_mutex);
  1015. }
  1016. EXPORT_SYMBOL(em28xx_unregister_extension);
  1017. void em28xx_init_extension(struct em28xx *dev)
  1018. {
  1019. struct em28xx_ops *ops = NULL;
  1020. mutex_lock(&em28xx_extension_devlist_lock);
  1021. if (!list_empty(&em28xx_extension_devlist)) {
  1022. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1023. if (ops->init)
  1024. ops->init(dev);
  1025. }
  1026. }
  1027. mutex_unlock(&em28xx_extension_devlist_lock);
  1028. }
  1029. void em28xx_close_extension(struct em28xx *dev)
  1030. {
  1031. struct em28xx_ops *ops = NULL;
  1032. mutex_lock(&em28xx_extension_devlist_lock);
  1033. if (!list_empty(&em28xx_extension_devlist)) {
  1034. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1035. if (ops->fini)
  1036. ops->fini(dev);
  1037. }
  1038. }
  1039. mutex_unlock(&em28xx_extension_devlist_lock);
  1040. }