vpif.c 8.2 KB

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  1. /*
  2. * vpif - DM646x Video Port Interface driver
  3. * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
  4. * that receiveing video byte stream and two channels(2, 3) for video output.
  5. * The hardware supports SDTV, HDTV formats, raw data capture.
  6. * Currently, the driver supports NTSC and PAL standards.
  7. *
  8. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation version 2.
  13. *
  14. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  15. * kind, whether express or implied; without even the implied warranty
  16. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/kernel.h>
  24. #include <linux/io.h>
  25. #include <mach/hardware.h>
  26. #include "vpif.h"
  27. MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
  28. MODULE_LICENSE("GPL");
  29. #define VPIF_CH0_MAX_MODES (22)
  30. #define VPIF_CH1_MAX_MODES (02)
  31. #define VPIF_CH2_MAX_MODES (15)
  32. #define VPIF_CH3_MAX_MODES (02)
  33. static resource_size_t res_len;
  34. static struct resource *res;
  35. spinlock_t vpif_lock;
  36. void __iomem *vpif_base;
  37. static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
  38. {
  39. if (val)
  40. vpif_set_bit(reg, bit);
  41. else
  42. vpif_clr_bit(reg, bit);
  43. }
  44. /* This structure is used to keep track of VPIF size register's offsets */
  45. struct vpif_registers {
  46. u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
  47. u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
  48. u32 vanc1_size, width_mask, len_mask;
  49. u8 max_modes;
  50. };
  51. static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
  52. /* Channel0 */
  53. {
  54. VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
  55. VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
  56. VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
  57. VPIF_CH0_MAX_MODES,
  58. },
  59. /* Channel1 */
  60. {
  61. VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
  62. VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
  63. VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
  64. VPIF_CH1_MAX_MODES,
  65. },
  66. /* Channel2 */
  67. {
  68. VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
  69. VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
  70. VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
  71. VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
  72. VPIF_CH2_MAX_MODES
  73. },
  74. /* Channel3 */
  75. {
  76. VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
  77. VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
  78. VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
  79. VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
  80. VPIF_CH3_MAX_MODES
  81. },
  82. };
  83. /* vpif_set_mode_info:
  84. * This function is used to set horizontal and vertical config parameters
  85. * As per the standard in the channel, configure the values of L1, L3,
  86. * L5, L7 L9, L11 in VPIF Register , also write width and height
  87. */
  88. static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
  89. u8 channel_id, u8 config_channel_id)
  90. {
  91. u32 value;
  92. value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
  93. value <<= VPIF_CH_LEN_SHIFT;
  94. value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
  95. regw(value, vpifregs[channel_id].h_cfg);
  96. value = (config->l1 & vpifregs[config_channel_id].len_mask);
  97. value <<= VPIF_CH_LEN_SHIFT;
  98. value |= (config->l3 & vpifregs[config_channel_id].len_mask);
  99. regw(value, vpifregs[channel_id].v_cfg_00);
  100. value = (config->l5 & vpifregs[config_channel_id].len_mask);
  101. value <<= VPIF_CH_LEN_SHIFT;
  102. value |= (config->l7 & vpifregs[config_channel_id].len_mask);
  103. regw(value, vpifregs[channel_id].v_cfg_01);
  104. value = (config->l9 & vpifregs[config_channel_id].len_mask);
  105. value <<= VPIF_CH_LEN_SHIFT;
  106. value |= (config->l11 & vpifregs[config_channel_id].len_mask);
  107. regw(value, vpifregs[channel_id].v_cfg_02);
  108. value = (config->vsize & vpifregs[config_channel_id].len_mask);
  109. regw(value, vpifregs[channel_id].v_cfg);
  110. }
  111. /* config_vpif_params
  112. * Function to set the parameters of a channel
  113. * Mainly modifies the channel ciontrol register
  114. * It sets frame format, yc mux mode
  115. */
  116. static void config_vpif_params(struct vpif_params *vpifparams,
  117. u8 channel_id, u8 found)
  118. {
  119. const struct vpif_channel_config_params *config = &vpifparams->std_info;
  120. u32 value, ch_nip, reg;
  121. u8 start, end;
  122. int i;
  123. start = channel_id;
  124. end = channel_id + found;
  125. for (i = start; i < end; i++) {
  126. reg = vpifregs[i].ch_ctrl;
  127. if (channel_id < 2)
  128. ch_nip = VPIF_CAPTURE_CH_NIP;
  129. else
  130. ch_nip = VPIF_DISPLAY_CH_NIP;
  131. vpif_wr_bit(reg, ch_nip, config->frm_fmt);
  132. vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
  133. vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
  134. vpifparams->video_params.storage_mode);
  135. /* Set raster scanning SDR Format */
  136. vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
  137. vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
  138. if (channel_id > 1) /* Set the Pixel enable bit */
  139. vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
  140. else if (config->capture_format) {
  141. /* Set the polarity of various pins */
  142. vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
  143. vpifparams->iface.fid_pol);
  144. vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
  145. vpifparams->iface.vd_pol);
  146. vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
  147. vpifparams->iface.hd_pol);
  148. value = regr(reg);
  149. /* Set data width */
  150. value &= ((~(unsigned int)(0x3)) <<
  151. VPIF_CH_DATA_WIDTH_BIT);
  152. value |= ((vpifparams->params.data_sz) <<
  153. VPIF_CH_DATA_WIDTH_BIT);
  154. regw(value, reg);
  155. }
  156. /* Write the pitch in the driver */
  157. regw((vpifparams->video_params.hpitch),
  158. vpifregs[i].line_offset);
  159. }
  160. }
  161. /* vpif_set_video_params
  162. * This function is used to set video parameters in VPIF register
  163. */
  164. int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
  165. {
  166. const struct vpif_channel_config_params *config = &vpifparams->std_info;
  167. int found = 1;
  168. vpif_set_mode_info(config, channel_id, channel_id);
  169. if (!config->ycmux_mode) {
  170. /* YC are on separate channels (HDTV formats) */
  171. vpif_set_mode_info(config, channel_id + 1, channel_id);
  172. found = 2;
  173. }
  174. config_vpif_params(vpifparams, channel_id, found);
  175. regw(0x80, VPIF_REQ_SIZE);
  176. regw(0x01, VPIF_EMULATION_CTRL);
  177. return found;
  178. }
  179. EXPORT_SYMBOL(vpif_set_video_params);
  180. void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
  181. u8 channel_id)
  182. {
  183. u32 value;
  184. value = 0x3F8 & (vbiparams->hstart0);
  185. value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
  186. regw(value, vpifregs[channel_id].vanc0_strt);
  187. value = 0x3F8 & (vbiparams->hstart1);
  188. value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
  189. regw(value, vpifregs[channel_id].vanc1_strt);
  190. value = 0x3F8 & (vbiparams->hsize0);
  191. value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
  192. regw(value, vpifregs[channel_id].vanc0_size);
  193. value = 0x3F8 & (vbiparams->hsize1);
  194. value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
  195. regw(value, vpifregs[channel_id].vanc1_size);
  196. }
  197. EXPORT_SYMBOL(vpif_set_vbi_display_params);
  198. int vpif_channel_getfid(u8 channel_id)
  199. {
  200. return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
  201. >> VPIF_CH_FID_SHIFT;
  202. }
  203. EXPORT_SYMBOL(vpif_channel_getfid);
  204. static int __init vpif_probe(struct platform_device *pdev)
  205. {
  206. int status = 0;
  207. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  208. if (!res)
  209. return -ENOENT;
  210. res_len = res->end - res->start + 1;
  211. res = request_mem_region(res->start, res_len, res->name);
  212. if (!res)
  213. return -EBUSY;
  214. vpif_base = ioremap(res->start, res_len);
  215. if (!vpif_base) {
  216. status = -EBUSY;
  217. goto fail;
  218. }
  219. spin_lock_init(&vpif_lock);
  220. dev_info(&pdev->dev, "vpif probe success\n");
  221. return 0;
  222. fail:
  223. release_mem_region(res->start, res_len);
  224. return status;
  225. }
  226. static int vpif_remove(struct platform_device *pdev)
  227. {
  228. iounmap(vpif_base);
  229. release_mem_region(res->start, res_len);
  230. return 0;
  231. }
  232. static struct platform_driver vpif_driver = {
  233. .driver = {
  234. .name = "vpif",
  235. .owner = THIS_MODULE,
  236. },
  237. .remove = __devexit_p(vpif_remove),
  238. .probe = vpif_probe,
  239. };
  240. static void vpif_exit(void)
  241. {
  242. platform_driver_unregister(&vpif_driver);
  243. }
  244. static int __init vpif_init(void)
  245. {
  246. return platform_driver_register(&vpif_driver);
  247. }
  248. subsys_initcall(vpif_init);
  249. module_exit(vpif_exit);