radeon_ring.c 10 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include "drmP.h"
  30. #include "radeon_drm.h"
  31. #include "radeon_reg.h"
  32. #include "radeon.h"
  33. #include "atom.h"
  34. int radeon_debugfs_ib_init(struct radeon_device *rdev);
  35. /*
  36. * IB.
  37. */
  38. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
  39. {
  40. struct radeon_fence *fence;
  41. struct radeon_ib *nib;
  42. unsigned long i;
  43. int r = 0;
  44. *ib = NULL;
  45. r = radeon_fence_create(rdev, &fence);
  46. if (r) {
  47. DRM_ERROR("failed to create fence for new IB\n");
  48. return r;
  49. }
  50. mutex_lock(&rdev->ib_pool.mutex);
  51. i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
  52. if (i < RADEON_IB_POOL_SIZE) {
  53. set_bit(i, rdev->ib_pool.alloc_bm);
  54. rdev->ib_pool.ibs[i].length_dw = 0;
  55. *ib = &rdev->ib_pool.ibs[i];
  56. mutex_unlock(&rdev->ib_pool.mutex);
  57. goto out;
  58. }
  59. if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
  60. /* we go do nothings here */
  61. mutex_unlock(&rdev->ib_pool.mutex);
  62. DRM_ERROR("all IB allocated none scheduled.\n");
  63. r = -EINVAL;
  64. goto out;
  65. }
  66. /* get the first ib on the scheduled list */
  67. nib = list_entry(rdev->ib_pool.scheduled_ibs.next,
  68. struct radeon_ib, list);
  69. if (nib->fence == NULL) {
  70. /* we go do nothings here */
  71. mutex_unlock(&rdev->ib_pool.mutex);
  72. DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
  73. r = -EINVAL;
  74. goto out;
  75. }
  76. mutex_unlock(&rdev->ib_pool.mutex);
  77. r = radeon_fence_wait(nib->fence, false);
  78. if (r) {
  79. DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
  80. (unsigned long)nib->gpu_addr, nib->length_dw);
  81. DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");
  82. goto out;
  83. }
  84. radeon_fence_unref(&nib->fence);
  85. nib->length_dw = 0;
  86. /* scheduled list is accessed here */
  87. mutex_lock(&rdev->ib_pool.mutex);
  88. list_del(&nib->list);
  89. INIT_LIST_HEAD(&nib->list);
  90. mutex_unlock(&rdev->ib_pool.mutex);
  91. *ib = nib;
  92. out:
  93. if (r) {
  94. radeon_fence_unref(&fence);
  95. } else {
  96. (*ib)->fence = fence;
  97. }
  98. return r;
  99. }
  100. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
  101. {
  102. struct radeon_ib *tmp = *ib;
  103. *ib = NULL;
  104. if (tmp == NULL) {
  105. return;
  106. }
  107. mutex_lock(&rdev->ib_pool.mutex);
  108. if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {
  109. /* IB is scheduled & not signaled don't do anythings */
  110. mutex_unlock(&rdev->ib_pool.mutex);
  111. return;
  112. }
  113. list_del(&tmp->list);
  114. INIT_LIST_HEAD(&tmp->list);
  115. if (tmp->fence)
  116. radeon_fence_unref(&tmp->fence);
  117. tmp->length_dw = 0;
  118. clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
  119. mutex_unlock(&rdev->ib_pool.mutex);
  120. }
  121. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
  122. {
  123. int r = 0;
  124. if (!ib->length_dw || !rdev->cp.ready) {
  125. /* TODO: Nothings in the ib we should report. */
  126. DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
  127. return -EINVAL;
  128. }
  129. /* 64 dwords should be enough for fence too */
  130. r = radeon_ring_lock(rdev, 64);
  131. if (r) {
  132. DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
  133. return r;
  134. }
  135. radeon_ring_ib_execute(rdev, ib);
  136. radeon_fence_emit(rdev, ib->fence);
  137. mutex_lock(&rdev->ib_pool.mutex);
  138. list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
  139. mutex_unlock(&rdev->ib_pool.mutex);
  140. radeon_ring_unlock_commit(rdev);
  141. return 0;
  142. }
  143. int radeon_ib_pool_init(struct radeon_device *rdev)
  144. {
  145. void *ptr;
  146. uint64_t gpu_addr;
  147. int i;
  148. int r = 0;
  149. if (rdev->ib_pool.robj)
  150. return 0;
  151. /* Allocate 1M object buffer */
  152. INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
  153. r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
  154. true, RADEON_GEM_DOMAIN_GTT,
  155. &rdev->ib_pool.robj);
  156. if (r) {
  157. DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
  158. return r;
  159. }
  160. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  161. if (unlikely(r != 0))
  162. return r;
  163. r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
  164. if (r) {
  165. radeon_bo_unreserve(rdev->ib_pool.robj);
  166. DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
  167. return r;
  168. }
  169. r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
  170. radeon_bo_unreserve(rdev->ib_pool.robj);
  171. if (r) {
  172. DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
  173. return r;
  174. }
  175. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  176. unsigned offset;
  177. offset = i * 64 * 1024;
  178. rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
  179. rdev->ib_pool.ibs[i].ptr = ptr + offset;
  180. rdev->ib_pool.ibs[i].idx = i;
  181. rdev->ib_pool.ibs[i].length_dw = 0;
  182. INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);
  183. }
  184. bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
  185. rdev->ib_pool.ready = true;
  186. DRM_INFO("radeon: ib pool ready.\n");
  187. if (radeon_debugfs_ib_init(rdev)) {
  188. DRM_ERROR("Failed to register debugfs file for IB !\n");
  189. }
  190. return r;
  191. }
  192. void radeon_ib_pool_fini(struct radeon_device *rdev)
  193. {
  194. int r;
  195. if (!rdev->ib_pool.ready) {
  196. return;
  197. }
  198. mutex_lock(&rdev->ib_pool.mutex);
  199. bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
  200. if (rdev->ib_pool.robj) {
  201. r = radeon_bo_reserve(rdev->ib_pool.robj, false);
  202. if (likely(r == 0)) {
  203. radeon_bo_kunmap(rdev->ib_pool.robj);
  204. radeon_bo_unpin(rdev->ib_pool.robj);
  205. radeon_bo_unreserve(rdev->ib_pool.robj);
  206. }
  207. radeon_bo_unref(&rdev->ib_pool.robj);
  208. rdev->ib_pool.robj = NULL;
  209. }
  210. mutex_unlock(&rdev->ib_pool.mutex);
  211. }
  212. /*
  213. * Ring.
  214. */
  215. void radeon_ring_free_size(struct radeon_device *rdev)
  216. {
  217. if (rdev->family >= CHIP_R600)
  218. rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
  219. else
  220. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  221. /* This works because ring_size is a power of 2 */
  222. rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
  223. rdev->cp.ring_free_dw -= rdev->cp.wptr;
  224. rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
  225. if (!rdev->cp.ring_free_dw) {
  226. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  227. }
  228. }
  229. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
  230. {
  231. int r;
  232. /* Align requested size with padding so unlock_commit can
  233. * pad safely */
  234. ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
  235. mutex_lock(&rdev->cp.mutex);
  236. while (ndw > (rdev->cp.ring_free_dw - 1)) {
  237. radeon_ring_free_size(rdev);
  238. if (ndw < rdev->cp.ring_free_dw) {
  239. break;
  240. }
  241. r = radeon_fence_wait_next(rdev);
  242. if (r) {
  243. mutex_unlock(&rdev->cp.mutex);
  244. return r;
  245. }
  246. }
  247. rdev->cp.count_dw = ndw;
  248. rdev->cp.wptr_old = rdev->cp.wptr;
  249. return 0;
  250. }
  251. void radeon_ring_unlock_commit(struct radeon_device *rdev)
  252. {
  253. unsigned count_dw_pad;
  254. unsigned i;
  255. /* We pad to match fetch size */
  256. count_dw_pad = (rdev->cp.align_mask + 1) -
  257. (rdev->cp.wptr & rdev->cp.align_mask);
  258. for (i = 0; i < count_dw_pad; i++) {
  259. radeon_ring_write(rdev, 2 << 30);
  260. }
  261. DRM_MEMORYBARRIER();
  262. radeon_cp_commit(rdev);
  263. mutex_unlock(&rdev->cp.mutex);
  264. }
  265. void radeon_ring_unlock_undo(struct radeon_device *rdev)
  266. {
  267. rdev->cp.wptr = rdev->cp.wptr_old;
  268. mutex_unlock(&rdev->cp.mutex);
  269. }
  270. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
  271. {
  272. int r;
  273. rdev->cp.ring_size = ring_size;
  274. /* Allocate ring buffer */
  275. if (rdev->cp.ring_obj == NULL) {
  276. r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
  277. RADEON_GEM_DOMAIN_GTT,
  278. &rdev->cp.ring_obj);
  279. if (r) {
  280. dev_err(rdev->dev, "(%d) ring create failed\n", r);
  281. return r;
  282. }
  283. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  284. if (unlikely(r != 0))
  285. return r;
  286. r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
  287. &rdev->cp.gpu_addr);
  288. if (r) {
  289. radeon_bo_unreserve(rdev->cp.ring_obj);
  290. dev_err(rdev->dev, "(%d) ring pin failed\n", r);
  291. return r;
  292. }
  293. r = radeon_bo_kmap(rdev->cp.ring_obj,
  294. (void **)&rdev->cp.ring);
  295. radeon_bo_unreserve(rdev->cp.ring_obj);
  296. if (r) {
  297. dev_err(rdev->dev, "(%d) ring map failed\n", r);
  298. return r;
  299. }
  300. }
  301. rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
  302. rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
  303. return 0;
  304. }
  305. void radeon_ring_fini(struct radeon_device *rdev)
  306. {
  307. int r;
  308. mutex_lock(&rdev->cp.mutex);
  309. if (rdev->cp.ring_obj) {
  310. r = radeon_bo_reserve(rdev->cp.ring_obj, false);
  311. if (likely(r == 0)) {
  312. radeon_bo_kunmap(rdev->cp.ring_obj);
  313. radeon_bo_unpin(rdev->cp.ring_obj);
  314. radeon_bo_unreserve(rdev->cp.ring_obj);
  315. }
  316. radeon_bo_unref(&rdev->cp.ring_obj);
  317. rdev->cp.ring = NULL;
  318. rdev->cp.ring_obj = NULL;
  319. }
  320. mutex_unlock(&rdev->cp.mutex);
  321. }
  322. /*
  323. * Debugfs info
  324. */
  325. #if defined(CONFIG_DEBUG_FS)
  326. static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
  327. {
  328. struct drm_info_node *node = (struct drm_info_node *) m->private;
  329. struct radeon_ib *ib = node->info_ent->data;
  330. unsigned i;
  331. if (ib == NULL) {
  332. return 0;
  333. }
  334. seq_printf(m, "IB %04lu\n", ib->idx);
  335. seq_printf(m, "IB fence %p\n", ib->fence);
  336. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  337. for (i = 0; i < ib->length_dw; i++) {
  338. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  339. }
  340. return 0;
  341. }
  342. static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
  343. static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
  344. #endif
  345. int radeon_debugfs_ib_init(struct radeon_device *rdev)
  346. {
  347. #if defined(CONFIG_DEBUG_FS)
  348. unsigned i;
  349. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  350. sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
  351. radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
  352. radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
  353. radeon_debugfs_ib_list[i].driver_features = 0;
  354. radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
  355. }
  356. return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
  357. RADEON_IB_POOL_SIZE);
  358. #else
  359. return 0;
  360. #endif
  361. }