radeon_fence.c 10 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <asm/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include "drmP.h"
  37. #include "drm.h"
  38. #include "radeon_reg.h"
  39. #include "radeon.h"
  40. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  41. {
  42. unsigned long irq_flags;
  43. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  44. if (fence->emited) {
  45. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  46. return 0;
  47. }
  48. fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
  49. if (!rdev->cp.ready) {
  50. /* FIXME: cp is not running assume everythings is done right
  51. * away
  52. */
  53. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  54. } else
  55. radeon_fence_ring_emit(rdev, fence);
  56. fence->emited = true;
  57. fence->timeout = jiffies + ((2000 * HZ) / 1000);
  58. list_del(&fence->list);
  59. list_add_tail(&fence->list, &rdev->fence_drv.emited);
  60. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  61. return 0;
  62. }
  63. static bool radeon_fence_poll_locked(struct radeon_device *rdev)
  64. {
  65. struct radeon_fence *fence;
  66. struct list_head *i, *n;
  67. uint32_t seq;
  68. bool wake = false;
  69. if (rdev == NULL) {
  70. return true;
  71. }
  72. if (rdev->shutdown) {
  73. return true;
  74. }
  75. seq = RREG32(rdev->fence_drv.scratch_reg);
  76. rdev->fence_drv.last_seq = seq;
  77. n = NULL;
  78. list_for_each(i, &rdev->fence_drv.emited) {
  79. fence = list_entry(i, struct radeon_fence, list);
  80. if (fence->seq == seq) {
  81. n = i;
  82. break;
  83. }
  84. }
  85. /* all fence previous to this one are considered as signaled */
  86. if (n) {
  87. i = n;
  88. do {
  89. n = i->prev;
  90. list_del(i);
  91. list_add_tail(i, &rdev->fence_drv.signaled);
  92. fence = list_entry(i, struct radeon_fence, list);
  93. fence->signaled = true;
  94. i = n;
  95. } while (i != &rdev->fence_drv.emited);
  96. wake = true;
  97. }
  98. return wake;
  99. }
  100. static void radeon_fence_destroy(struct kref *kref)
  101. {
  102. unsigned long irq_flags;
  103. struct radeon_fence *fence;
  104. fence = container_of(kref, struct radeon_fence, kref);
  105. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  106. list_del(&fence->list);
  107. fence->emited = false;
  108. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  109. kfree(fence);
  110. }
  111. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
  112. {
  113. unsigned long irq_flags;
  114. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  115. if ((*fence) == NULL) {
  116. return -ENOMEM;
  117. }
  118. kref_init(&((*fence)->kref));
  119. (*fence)->rdev = rdev;
  120. (*fence)->emited = false;
  121. (*fence)->signaled = false;
  122. (*fence)->seq = 0;
  123. INIT_LIST_HEAD(&(*fence)->list);
  124. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  125. list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
  126. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  127. return 0;
  128. }
  129. bool radeon_fence_signaled(struct radeon_fence *fence)
  130. {
  131. struct radeon_device *rdev = fence->rdev;
  132. unsigned long irq_flags;
  133. bool signaled = false;
  134. if (rdev->gpu_lockup) {
  135. return true;
  136. }
  137. if (fence == NULL) {
  138. return true;
  139. }
  140. write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
  141. signaled = fence->signaled;
  142. /* if we are shuting down report all fence as signaled */
  143. if (fence->rdev->shutdown) {
  144. signaled = true;
  145. }
  146. if (!fence->emited) {
  147. WARN(1, "Querying an unemited fence : %p !\n", fence);
  148. signaled = true;
  149. }
  150. if (!signaled) {
  151. radeon_fence_poll_locked(fence->rdev);
  152. signaled = fence->signaled;
  153. }
  154. write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
  155. return signaled;
  156. }
  157. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  158. {
  159. struct radeon_device *rdev;
  160. unsigned long cur_jiffies;
  161. unsigned long timeout;
  162. bool expired = false;
  163. int r;
  164. if (fence == NULL) {
  165. WARN(1, "Querying an invalid fence : %p !\n", fence);
  166. return 0;
  167. }
  168. rdev = fence->rdev;
  169. if (radeon_fence_signaled(fence)) {
  170. return 0;
  171. }
  172. retry:
  173. cur_jiffies = jiffies;
  174. timeout = HZ / 100;
  175. if (time_after(fence->timeout, cur_jiffies)) {
  176. timeout = fence->timeout - cur_jiffies;
  177. }
  178. if (intr) {
  179. radeon_irq_kms_sw_irq_get(rdev);
  180. r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
  181. radeon_fence_signaled(fence), timeout);
  182. radeon_irq_kms_sw_irq_put(rdev);
  183. if (unlikely(r < 0))
  184. return r;
  185. } else {
  186. radeon_irq_kms_sw_irq_get(rdev);
  187. r = wait_event_timeout(rdev->fence_drv.queue,
  188. radeon_fence_signaled(fence), timeout);
  189. radeon_irq_kms_sw_irq_put(rdev);
  190. }
  191. if (unlikely(!radeon_fence_signaled(fence))) {
  192. if (unlikely(r == 0)) {
  193. expired = true;
  194. }
  195. if (unlikely(expired)) {
  196. timeout = 1;
  197. if (time_after(cur_jiffies, fence->timeout)) {
  198. timeout = cur_jiffies - fence->timeout;
  199. }
  200. timeout = jiffies_to_msecs(timeout);
  201. if (timeout > 500) {
  202. DRM_ERROR("fence(%p:0x%08X) %lums timeout "
  203. "going to reset GPU\n",
  204. fence, fence->seq, timeout);
  205. radeon_gpu_reset(rdev);
  206. WREG32(rdev->fence_drv.scratch_reg, fence->seq);
  207. }
  208. }
  209. goto retry;
  210. }
  211. if (unlikely(expired)) {
  212. rdev->fence_drv.count_timeout++;
  213. cur_jiffies = jiffies;
  214. timeout = 1;
  215. if (time_after(cur_jiffies, fence->timeout)) {
  216. timeout = cur_jiffies - fence->timeout;
  217. }
  218. timeout = jiffies_to_msecs(timeout);
  219. DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
  220. fence, fence->seq, timeout);
  221. DRM_ERROR("last signaled fence(0x%08X)\n",
  222. rdev->fence_drv.last_seq);
  223. }
  224. return 0;
  225. }
  226. int radeon_fence_wait_next(struct radeon_device *rdev)
  227. {
  228. unsigned long irq_flags;
  229. struct radeon_fence *fence;
  230. int r;
  231. if (rdev->gpu_lockup) {
  232. return 0;
  233. }
  234. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  235. if (list_empty(&rdev->fence_drv.emited)) {
  236. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  237. return 0;
  238. }
  239. fence = list_entry(rdev->fence_drv.emited.next,
  240. struct radeon_fence, list);
  241. radeon_fence_ref(fence);
  242. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  243. r = radeon_fence_wait(fence, false);
  244. radeon_fence_unref(&fence);
  245. return r;
  246. }
  247. int radeon_fence_wait_last(struct radeon_device *rdev)
  248. {
  249. unsigned long irq_flags;
  250. struct radeon_fence *fence;
  251. int r;
  252. if (rdev->gpu_lockup) {
  253. return 0;
  254. }
  255. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  256. if (list_empty(&rdev->fence_drv.emited)) {
  257. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  258. return 0;
  259. }
  260. fence = list_entry(rdev->fence_drv.emited.prev,
  261. struct radeon_fence, list);
  262. radeon_fence_ref(fence);
  263. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  264. r = radeon_fence_wait(fence, false);
  265. radeon_fence_unref(&fence);
  266. return r;
  267. }
  268. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  269. {
  270. kref_get(&fence->kref);
  271. return fence;
  272. }
  273. void radeon_fence_unref(struct radeon_fence **fence)
  274. {
  275. struct radeon_fence *tmp = *fence;
  276. *fence = NULL;
  277. if (tmp) {
  278. kref_put(&tmp->kref, &radeon_fence_destroy);
  279. }
  280. }
  281. void radeon_fence_process(struct radeon_device *rdev)
  282. {
  283. unsigned long irq_flags;
  284. bool wake;
  285. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  286. wake = radeon_fence_poll_locked(rdev);
  287. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  288. if (wake) {
  289. wake_up_all(&rdev->fence_drv.queue);
  290. }
  291. }
  292. int radeon_fence_driver_init(struct radeon_device *rdev)
  293. {
  294. unsigned long irq_flags;
  295. int r;
  296. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  297. r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
  298. if (r) {
  299. DRM_ERROR("Fence failed to get a scratch register.");
  300. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  301. return r;
  302. }
  303. WREG32(rdev->fence_drv.scratch_reg, 0);
  304. atomic_set(&rdev->fence_drv.seq, 0);
  305. INIT_LIST_HEAD(&rdev->fence_drv.created);
  306. INIT_LIST_HEAD(&rdev->fence_drv.emited);
  307. INIT_LIST_HEAD(&rdev->fence_drv.signaled);
  308. rdev->fence_drv.count_timeout = 0;
  309. init_waitqueue_head(&rdev->fence_drv.queue);
  310. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  311. if (radeon_debugfs_fence_init(rdev)) {
  312. DRM_ERROR("Failed to register debugfs file for fence !\n");
  313. }
  314. return 0;
  315. }
  316. void radeon_fence_driver_fini(struct radeon_device *rdev)
  317. {
  318. unsigned long irq_flags;
  319. wake_up_all(&rdev->fence_drv.queue);
  320. write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  321. radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
  322. write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  323. DRM_INFO("radeon: fence finalized\n");
  324. }
  325. /*
  326. * Fence debugfs
  327. */
  328. #if defined(CONFIG_DEBUG_FS)
  329. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  330. {
  331. struct drm_info_node *node = (struct drm_info_node *)m->private;
  332. struct drm_device *dev = node->minor->dev;
  333. struct radeon_device *rdev = dev->dev_private;
  334. struct radeon_fence *fence;
  335. seq_printf(m, "Last signaled fence 0x%08X\n",
  336. RREG32(rdev->fence_drv.scratch_reg));
  337. if (!list_empty(&rdev->fence_drv.emited)) {
  338. fence = list_entry(rdev->fence_drv.emited.prev,
  339. struct radeon_fence, list);
  340. seq_printf(m, "Last emited fence %p with 0x%08X\n",
  341. fence, fence->seq);
  342. }
  343. return 0;
  344. }
  345. static struct drm_info_list radeon_debugfs_fence_list[] = {
  346. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  347. };
  348. #endif
  349. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  350. {
  351. #if defined(CONFIG_DEBUG_FS)
  352. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  353. #else
  354. return 0;
  355. #endif
  356. }