radeon.h 36 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151
  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30. /* TODO: Here are things that needs to be done :
  31. * - surface allocator & initializer : (bit like scratch reg) should
  32. * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  33. * related to surface
  34. * - WB : write back stuff (do it bit like scratch reg things)
  35. * - Vblank : look at Jesse's rework and what we should do
  36. * - r600/r700: gart & cp
  37. * - cs : clean cs ioctl use bitmap & things like that.
  38. * - power management stuff
  39. * - Barrier in gart code
  40. * - Unmappabled vram ?
  41. * - TESTING, TESTING, TESTING
  42. */
  43. /* Initialization path:
  44. * We expect that acceleration initialization might fail for various
  45. * reasons even thought we work hard to make it works on most
  46. * configurations. In order to still have a working userspace in such
  47. * situation the init path must succeed up to the memory controller
  48. * initialization point. Failure before this point are considered as
  49. * fatal error. Here is the init callchain :
  50. * radeon_device_init perform common structure, mutex initialization
  51. * asic_init setup the GPU memory layout and perform all
  52. * one time initialization (failure in this
  53. * function are considered fatal)
  54. * asic_startup setup the GPU acceleration, in order to
  55. * follow guideline the first thing this
  56. * function should do is setting the GPU
  57. * memory controller (only MC setup failure
  58. * are considered as fatal)
  59. */
  60. #include <asm/atomic.h>
  61. #include <linux/wait.h>
  62. #include <linux/list.h>
  63. #include <linux/kref.h>
  64. #include <ttm/ttm_bo_api.h>
  65. #include <ttm/ttm_bo_driver.h>
  66. #include <ttm/ttm_placement.h>
  67. #include <ttm/ttm_module.h>
  68. #include "radeon_family.h"
  69. #include "radeon_mode.h"
  70. #include "radeon_reg.h"
  71. /*
  72. * Modules parameters.
  73. */
  74. extern int radeon_no_wb;
  75. extern int radeon_modeset;
  76. extern int radeon_dynclks;
  77. extern int radeon_r4xx_atom;
  78. extern int radeon_agpmode;
  79. extern int radeon_vram_limit;
  80. extern int radeon_gart_size;
  81. extern int radeon_benchmarking;
  82. extern int radeon_testing;
  83. extern int radeon_connector_table;
  84. extern int radeon_tv;
  85. extern int radeon_new_pll;
  86. /*
  87. * Copy from radeon_drv.h so we don't have to include both and have conflicting
  88. * symbol;
  89. */
  90. #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
  91. #define RADEON_IB_POOL_SIZE 16
  92. #define RADEON_DEBUGFS_MAX_NUM_FILES 32
  93. #define RADEONFB_CONN_LIMIT 4
  94. #define RADEON_BIOS_NUM_SCRATCH 8
  95. /*
  96. * Errata workarounds.
  97. */
  98. enum radeon_pll_errata {
  99. CHIP_ERRATA_R300_CG = 0x00000001,
  100. CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
  101. CHIP_ERRATA_PLL_DELAY = 0x00000004
  102. };
  103. struct radeon_device;
  104. /*
  105. * BIOS.
  106. */
  107. bool radeon_get_bios(struct radeon_device *rdev);
  108. /*
  109. * Dummy page
  110. */
  111. struct radeon_dummy_page {
  112. struct page *page;
  113. dma_addr_t addr;
  114. };
  115. int radeon_dummy_page_init(struct radeon_device *rdev);
  116. void radeon_dummy_page_fini(struct radeon_device *rdev);
  117. /*
  118. * Clocks
  119. */
  120. struct radeon_clock {
  121. struct radeon_pll p1pll;
  122. struct radeon_pll p2pll;
  123. struct radeon_pll spll;
  124. struct radeon_pll mpll;
  125. /* 10 Khz units */
  126. uint32_t default_mclk;
  127. uint32_t default_sclk;
  128. };
  129. /*
  130. * Power management
  131. */
  132. int radeon_pm_init(struct radeon_device *rdev);
  133. /*
  134. * Fences.
  135. */
  136. struct radeon_fence_driver {
  137. uint32_t scratch_reg;
  138. atomic_t seq;
  139. uint32_t last_seq;
  140. unsigned long count_timeout;
  141. wait_queue_head_t queue;
  142. rwlock_t lock;
  143. struct list_head created;
  144. struct list_head emited;
  145. struct list_head signaled;
  146. };
  147. struct radeon_fence {
  148. struct radeon_device *rdev;
  149. struct kref kref;
  150. struct list_head list;
  151. /* protected by radeon_fence.lock */
  152. uint32_t seq;
  153. unsigned long timeout;
  154. bool emited;
  155. bool signaled;
  156. };
  157. int radeon_fence_driver_init(struct radeon_device *rdev);
  158. void radeon_fence_driver_fini(struct radeon_device *rdev);
  159. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  160. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  161. void radeon_fence_process(struct radeon_device *rdev);
  162. bool radeon_fence_signaled(struct radeon_fence *fence);
  163. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  164. int radeon_fence_wait_next(struct radeon_device *rdev);
  165. int radeon_fence_wait_last(struct radeon_device *rdev);
  166. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  167. void radeon_fence_unref(struct radeon_fence **fence);
  168. /*
  169. * Tiling registers
  170. */
  171. struct radeon_surface_reg {
  172. struct radeon_bo *bo;
  173. };
  174. #define RADEON_GEM_MAX_SURFACES 8
  175. /*
  176. * TTM.
  177. */
  178. struct radeon_mman {
  179. struct ttm_bo_global_ref bo_global_ref;
  180. struct ttm_global_reference mem_global_ref;
  181. bool mem_global_referenced;
  182. struct ttm_bo_device bdev;
  183. };
  184. struct radeon_bo {
  185. /* Protected by gem.mutex */
  186. struct list_head list;
  187. /* Protected by tbo.reserved */
  188. u32 placements[3];
  189. struct ttm_placement placement;
  190. struct ttm_buffer_object tbo;
  191. struct ttm_bo_kmap_obj kmap;
  192. unsigned pin_count;
  193. void *kptr;
  194. u32 tiling_flags;
  195. u32 pitch;
  196. int surface_reg;
  197. /* Constant after initialization */
  198. struct radeon_device *rdev;
  199. struct drm_gem_object *gobj;
  200. };
  201. struct radeon_bo_list {
  202. struct list_head list;
  203. struct radeon_bo *bo;
  204. uint64_t gpu_offset;
  205. unsigned rdomain;
  206. unsigned wdomain;
  207. u32 tiling_flags;
  208. };
  209. /*
  210. * GEM objects.
  211. */
  212. struct radeon_gem {
  213. struct mutex mutex;
  214. struct list_head objects;
  215. };
  216. int radeon_gem_init(struct radeon_device *rdev);
  217. void radeon_gem_fini(struct radeon_device *rdev);
  218. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  219. int alignment, int initial_domain,
  220. bool discardable, bool kernel,
  221. struct drm_gem_object **obj);
  222. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  223. uint64_t *gpu_addr);
  224. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  225. /*
  226. * GART structures, functions & helpers
  227. */
  228. struct radeon_mc;
  229. struct radeon_gart_table_ram {
  230. volatile uint32_t *ptr;
  231. };
  232. struct radeon_gart_table_vram {
  233. struct radeon_bo *robj;
  234. volatile uint32_t *ptr;
  235. };
  236. union radeon_gart_table {
  237. struct radeon_gart_table_ram ram;
  238. struct radeon_gart_table_vram vram;
  239. };
  240. #define RADEON_GPU_PAGE_SIZE 4096
  241. struct radeon_gart {
  242. dma_addr_t table_addr;
  243. unsigned num_gpu_pages;
  244. unsigned num_cpu_pages;
  245. unsigned table_size;
  246. union radeon_gart_table table;
  247. struct page **pages;
  248. dma_addr_t *pages_addr;
  249. bool ready;
  250. };
  251. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  252. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  253. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  254. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  255. int radeon_gart_init(struct radeon_device *rdev);
  256. void radeon_gart_fini(struct radeon_device *rdev);
  257. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  258. int pages);
  259. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  260. int pages, struct page **pagelist);
  261. /*
  262. * GPU MC structures, functions & helpers
  263. */
  264. struct radeon_mc {
  265. resource_size_t aper_size;
  266. resource_size_t aper_base;
  267. resource_size_t agp_base;
  268. /* for some chips with <= 32MB we need to lie
  269. * about vram size near mc fb location */
  270. u64 mc_vram_size;
  271. u64 gtt_location;
  272. u64 gtt_size;
  273. u64 gtt_start;
  274. u64 gtt_end;
  275. u64 vram_location;
  276. u64 vram_start;
  277. u64 vram_end;
  278. unsigned vram_width;
  279. u64 real_vram_size;
  280. int vram_mtrr;
  281. bool vram_is_ddr;
  282. };
  283. int radeon_mc_setup(struct radeon_device *rdev);
  284. /*
  285. * GPU scratch registers structures, functions & helpers
  286. */
  287. struct radeon_scratch {
  288. unsigned num_reg;
  289. bool free[32];
  290. uint32_t reg[32];
  291. };
  292. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  293. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  294. /*
  295. * IRQS.
  296. */
  297. struct radeon_irq {
  298. bool installed;
  299. bool sw_int;
  300. /* FIXME: use a define max crtc rather than hardcode it */
  301. bool crtc_vblank_int[2];
  302. /* FIXME: use defines for max hpd/dacs */
  303. bool hpd[6];
  304. spinlock_t sw_lock;
  305. int sw_refcount;
  306. };
  307. int radeon_irq_kms_init(struct radeon_device *rdev);
  308. void radeon_irq_kms_fini(struct radeon_device *rdev);
  309. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  310. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  311. /*
  312. * CP & ring.
  313. */
  314. struct radeon_ib {
  315. struct list_head list;
  316. unsigned long idx;
  317. uint64_t gpu_addr;
  318. struct radeon_fence *fence;
  319. uint32_t *ptr;
  320. uint32_t length_dw;
  321. };
  322. /*
  323. * locking -
  324. * mutex protects scheduled_ibs, ready, alloc_bm
  325. */
  326. struct radeon_ib_pool {
  327. struct mutex mutex;
  328. struct radeon_bo *robj;
  329. struct list_head scheduled_ibs;
  330. struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
  331. bool ready;
  332. DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  333. };
  334. struct radeon_cp {
  335. struct radeon_bo *ring_obj;
  336. volatile uint32_t *ring;
  337. unsigned rptr;
  338. unsigned wptr;
  339. unsigned wptr_old;
  340. unsigned ring_size;
  341. unsigned ring_free_dw;
  342. int count_dw;
  343. uint64_t gpu_addr;
  344. uint32_t align_mask;
  345. uint32_t ptr_mask;
  346. struct mutex mutex;
  347. bool ready;
  348. };
  349. /*
  350. * R6xx+ IH ring
  351. */
  352. struct r600_ih {
  353. struct radeon_bo *ring_obj;
  354. volatile uint32_t *ring;
  355. unsigned rptr;
  356. unsigned wptr;
  357. unsigned wptr_old;
  358. unsigned ring_size;
  359. uint64_t gpu_addr;
  360. uint32_t align_mask;
  361. uint32_t ptr_mask;
  362. spinlock_t lock;
  363. bool enabled;
  364. };
  365. struct r600_blit {
  366. struct radeon_bo *shader_obj;
  367. u64 shader_gpu_addr;
  368. u32 vs_offset, ps_offset;
  369. u32 state_offset;
  370. u32 state_len;
  371. u32 vb_used, vb_total;
  372. struct radeon_ib *vb_ib;
  373. };
  374. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  375. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  376. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  377. int radeon_ib_pool_init(struct radeon_device *rdev);
  378. void radeon_ib_pool_fini(struct radeon_device *rdev);
  379. int radeon_ib_test(struct radeon_device *rdev);
  380. /* Ring access between begin & end cannot sleep */
  381. void radeon_ring_free_size(struct radeon_device *rdev);
  382. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  383. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  384. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  385. int radeon_ring_test(struct radeon_device *rdev);
  386. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  387. void radeon_ring_fini(struct radeon_device *rdev);
  388. /*
  389. * CS.
  390. */
  391. struct radeon_cs_reloc {
  392. struct drm_gem_object *gobj;
  393. struct radeon_bo *robj;
  394. struct radeon_bo_list lobj;
  395. uint32_t handle;
  396. uint32_t flags;
  397. };
  398. struct radeon_cs_chunk {
  399. uint32_t chunk_id;
  400. uint32_t length_dw;
  401. int kpage_idx[2];
  402. uint32_t *kpage[2];
  403. uint32_t *kdata;
  404. void __user *user_ptr;
  405. int last_copied_page;
  406. int last_page_index;
  407. };
  408. struct radeon_cs_parser {
  409. struct radeon_device *rdev;
  410. struct drm_file *filp;
  411. /* chunks */
  412. unsigned nchunks;
  413. struct radeon_cs_chunk *chunks;
  414. uint64_t *chunks_array;
  415. /* IB */
  416. unsigned idx;
  417. /* relocations */
  418. unsigned nrelocs;
  419. struct radeon_cs_reloc *relocs;
  420. struct radeon_cs_reloc **relocs_ptr;
  421. struct list_head validated;
  422. /* indices of various chunks */
  423. int chunk_ib_idx;
  424. int chunk_relocs_idx;
  425. struct radeon_ib *ib;
  426. void *track;
  427. unsigned family;
  428. int parser_error;
  429. };
  430. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  431. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  432. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  433. {
  434. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  435. u32 pg_idx, pg_offset;
  436. u32 idx_value = 0;
  437. int new_page;
  438. pg_idx = (idx * 4) / PAGE_SIZE;
  439. pg_offset = (idx * 4) % PAGE_SIZE;
  440. if (ibc->kpage_idx[0] == pg_idx)
  441. return ibc->kpage[0][pg_offset/4];
  442. if (ibc->kpage_idx[1] == pg_idx)
  443. return ibc->kpage[1][pg_offset/4];
  444. new_page = radeon_cs_update_pages(p, pg_idx);
  445. if (new_page < 0) {
  446. p->parser_error = new_page;
  447. return 0;
  448. }
  449. idx_value = ibc->kpage[new_page][pg_offset/4];
  450. return idx_value;
  451. }
  452. struct radeon_cs_packet {
  453. unsigned idx;
  454. unsigned type;
  455. unsigned reg;
  456. unsigned opcode;
  457. int count;
  458. unsigned one_reg_wr;
  459. };
  460. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  461. struct radeon_cs_packet *pkt,
  462. unsigned idx, unsigned reg);
  463. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  464. struct radeon_cs_packet *pkt);
  465. /*
  466. * AGP
  467. */
  468. int radeon_agp_init(struct radeon_device *rdev);
  469. void radeon_agp_resume(struct radeon_device *rdev);
  470. void radeon_agp_fini(struct radeon_device *rdev);
  471. /*
  472. * Writeback
  473. */
  474. struct radeon_wb {
  475. struct radeon_bo *wb_obj;
  476. volatile uint32_t *wb;
  477. uint64_t gpu_addr;
  478. };
  479. /**
  480. * struct radeon_pm - power management datas
  481. * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
  482. * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  483. * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
  484. * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
  485. * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
  486. * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
  487. * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  488. * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
  489. * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
  490. * @sclk: GPU clock Mhz (core bandwith depends of this clock)
  491. * @needed_bandwidth: current bandwidth needs
  492. *
  493. * It keeps track of various data needed to take powermanagement decision.
  494. * Bandwith need is used to determine minimun clock of the GPU and memory.
  495. * Equation between gpu/memory clock and available bandwidth is hw dependent
  496. * (type of memory, bus size, efficiency, ...)
  497. */
  498. struct radeon_pm {
  499. fixed20_12 max_bandwidth;
  500. fixed20_12 igp_sideport_mclk;
  501. fixed20_12 igp_system_mclk;
  502. fixed20_12 igp_ht_link_clk;
  503. fixed20_12 igp_ht_link_width;
  504. fixed20_12 k8_bandwidth;
  505. fixed20_12 sideport_bandwidth;
  506. fixed20_12 ht_bandwidth;
  507. fixed20_12 core_bandwidth;
  508. fixed20_12 sclk;
  509. fixed20_12 needed_bandwidth;
  510. };
  511. /*
  512. * Benchmarking
  513. */
  514. void radeon_benchmark(struct radeon_device *rdev);
  515. /*
  516. * Testing
  517. */
  518. void radeon_test_moves(struct radeon_device *rdev);
  519. /*
  520. * Debugfs
  521. */
  522. int radeon_debugfs_add_files(struct radeon_device *rdev,
  523. struct drm_info_list *files,
  524. unsigned nfiles);
  525. int radeon_debugfs_fence_init(struct radeon_device *rdev);
  526. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  527. int r100_debugfs_cp_init(struct radeon_device *rdev);
  528. /*
  529. * ASIC specific functions.
  530. */
  531. struct radeon_asic {
  532. int (*init)(struct radeon_device *rdev);
  533. void (*fini)(struct radeon_device *rdev);
  534. int (*resume)(struct radeon_device *rdev);
  535. int (*suspend)(struct radeon_device *rdev);
  536. void (*vga_set_state)(struct radeon_device *rdev, bool state);
  537. int (*gpu_reset)(struct radeon_device *rdev);
  538. void (*gart_tlb_flush)(struct radeon_device *rdev);
  539. int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  540. int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  541. void (*cp_fini)(struct radeon_device *rdev);
  542. void (*cp_disable)(struct radeon_device *rdev);
  543. void (*cp_commit)(struct radeon_device *rdev);
  544. void (*ring_start)(struct radeon_device *rdev);
  545. int (*ring_test)(struct radeon_device *rdev);
  546. void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  547. int (*irq_set)(struct radeon_device *rdev);
  548. int (*irq_process)(struct radeon_device *rdev);
  549. u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  550. void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  551. int (*cs_parse)(struct radeon_cs_parser *p);
  552. int (*copy_blit)(struct radeon_device *rdev,
  553. uint64_t src_offset,
  554. uint64_t dst_offset,
  555. unsigned num_pages,
  556. struct radeon_fence *fence);
  557. int (*copy_dma)(struct radeon_device *rdev,
  558. uint64_t src_offset,
  559. uint64_t dst_offset,
  560. unsigned num_pages,
  561. struct radeon_fence *fence);
  562. int (*copy)(struct radeon_device *rdev,
  563. uint64_t src_offset,
  564. uint64_t dst_offset,
  565. unsigned num_pages,
  566. struct radeon_fence *fence);
  567. uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  568. void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  569. uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  570. void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  571. void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  572. void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  573. int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  574. uint32_t tiling_flags, uint32_t pitch,
  575. uint32_t offset, uint32_t obj_size);
  576. int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  577. void (*bandwidth_update)(struct radeon_device *rdev);
  578. void (*hdp_flush)(struct radeon_device *rdev);
  579. void (*hpd_init)(struct radeon_device *rdev);
  580. void (*hpd_fini)(struct radeon_device *rdev);
  581. bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  582. void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  583. };
  584. /*
  585. * Asic structures
  586. */
  587. struct r100_asic {
  588. const unsigned *reg_safe_bm;
  589. unsigned reg_safe_bm_size;
  590. };
  591. struct r300_asic {
  592. const unsigned *reg_safe_bm;
  593. unsigned reg_safe_bm_size;
  594. };
  595. struct r600_asic {
  596. unsigned max_pipes;
  597. unsigned max_tile_pipes;
  598. unsigned max_simds;
  599. unsigned max_backends;
  600. unsigned max_gprs;
  601. unsigned max_threads;
  602. unsigned max_stack_entries;
  603. unsigned max_hw_contexts;
  604. unsigned max_gs_threads;
  605. unsigned sx_max_export_size;
  606. unsigned sx_max_export_pos_size;
  607. unsigned sx_max_export_smx_size;
  608. unsigned sq_num_cf_insts;
  609. };
  610. struct rv770_asic {
  611. unsigned max_pipes;
  612. unsigned max_tile_pipes;
  613. unsigned max_simds;
  614. unsigned max_backends;
  615. unsigned max_gprs;
  616. unsigned max_threads;
  617. unsigned max_stack_entries;
  618. unsigned max_hw_contexts;
  619. unsigned max_gs_threads;
  620. unsigned sx_max_export_size;
  621. unsigned sx_max_export_pos_size;
  622. unsigned sx_max_export_smx_size;
  623. unsigned sq_num_cf_insts;
  624. unsigned sx_num_of_sets;
  625. unsigned sc_prim_fifo_size;
  626. unsigned sc_hiz_tile_fifo_size;
  627. unsigned sc_earlyz_tile_fifo_fize;
  628. };
  629. union radeon_asic_config {
  630. struct r300_asic r300;
  631. struct r100_asic r100;
  632. struct r600_asic r600;
  633. struct rv770_asic rv770;
  634. };
  635. /*
  636. * IOCTL.
  637. */
  638. int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
  639. struct drm_file *filp);
  640. int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
  641. struct drm_file *filp);
  642. int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
  643. struct drm_file *file_priv);
  644. int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
  645. struct drm_file *file_priv);
  646. int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  647. struct drm_file *file_priv);
  648. int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
  649. struct drm_file *file_priv);
  650. int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  651. struct drm_file *filp);
  652. int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
  653. struct drm_file *filp);
  654. int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
  655. struct drm_file *filp);
  656. int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
  657. struct drm_file *filp);
  658. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
  659. int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
  660. struct drm_file *filp);
  661. int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
  662. struct drm_file *filp);
  663. /*
  664. * Core structure, functions and helpers.
  665. */
  666. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  667. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  668. struct radeon_device {
  669. struct device *dev;
  670. struct drm_device *ddev;
  671. struct pci_dev *pdev;
  672. /* ASIC */
  673. union radeon_asic_config config;
  674. enum radeon_family family;
  675. unsigned long flags;
  676. int usec_timeout;
  677. enum radeon_pll_errata pll_errata;
  678. int num_gb_pipes;
  679. int num_z_pipes;
  680. int disp_priority;
  681. /* BIOS */
  682. uint8_t *bios;
  683. bool is_atom_bios;
  684. uint16_t bios_header_start;
  685. struct radeon_bo *stollen_vga_memory;
  686. struct fb_info *fbdev_info;
  687. struct radeon_bo *fbdev_rbo;
  688. struct radeon_framebuffer *fbdev_rfb;
  689. /* Register mmio */
  690. resource_size_t rmmio_base;
  691. resource_size_t rmmio_size;
  692. void *rmmio;
  693. radeon_rreg_t mc_rreg;
  694. radeon_wreg_t mc_wreg;
  695. radeon_rreg_t pll_rreg;
  696. radeon_wreg_t pll_wreg;
  697. uint32_t pcie_reg_mask;
  698. radeon_rreg_t pciep_rreg;
  699. radeon_wreg_t pciep_wreg;
  700. struct radeon_clock clock;
  701. struct radeon_mc mc;
  702. struct radeon_gart gart;
  703. struct radeon_mode_info mode_info;
  704. struct radeon_scratch scratch;
  705. struct radeon_mman mman;
  706. struct radeon_fence_driver fence_drv;
  707. struct radeon_cp cp;
  708. struct radeon_ib_pool ib_pool;
  709. struct radeon_irq irq;
  710. struct radeon_asic *asic;
  711. struct radeon_gem gem;
  712. struct radeon_pm pm;
  713. uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  714. struct mutex cs_mutex;
  715. struct radeon_wb wb;
  716. struct radeon_dummy_page dummy_page;
  717. bool gpu_lockup;
  718. bool shutdown;
  719. bool suspend;
  720. bool need_dma32;
  721. bool accel_working;
  722. struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  723. const struct firmware *me_fw; /* all family ME firmware */
  724. const struct firmware *pfp_fw; /* r6/700 PFP firmware */
  725. const struct firmware *rlc_fw; /* r6/700 RLC firmware */
  726. struct r600_blit r600_blit;
  727. int msi_enabled; /* msi enabled */
  728. struct r600_ih ih; /* r6/700 interrupt ring */
  729. struct workqueue_struct *wq;
  730. struct work_struct hotplug_work;
  731. };
  732. int radeon_device_init(struct radeon_device *rdev,
  733. struct drm_device *ddev,
  734. struct pci_dev *pdev,
  735. uint32_t flags);
  736. void radeon_device_fini(struct radeon_device *rdev);
  737. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  738. /* r600 blit */
  739. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  740. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  741. void r600_kms_blit_copy(struct radeon_device *rdev,
  742. u64 src_gpu_addr, u64 dst_gpu_addr,
  743. int size_bytes);
  744. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  745. {
  746. if (reg < 0x10000)
  747. return readl(((void __iomem *)rdev->rmmio) + reg);
  748. else {
  749. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  750. return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  751. }
  752. }
  753. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  754. {
  755. if (reg < 0x10000)
  756. writel(v, ((void __iomem *)rdev->rmmio) + reg);
  757. else {
  758. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  759. writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  760. }
  761. }
  762. /*
  763. * Cast helper
  764. */
  765. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  766. /*
  767. * Registers read & write functions.
  768. */
  769. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  770. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  771. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  772. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
  773. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  774. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  775. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  776. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  777. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  778. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  779. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  780. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  781. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  782. #define WREG32_P(reg, val, mask) \
  783. do { \
  784. uint32_t tmp_ = RREG32(reg); \
  785. tmp_ &= (mask); \
  786. tmp_ |= ((val) & ~(mask)); \
  787. WREG32(reg, tmp_); \
  788. } while (0)
  789. #define WREG32_PLL_P(reg, val, mask) \
  790. do { \
  791. uint32_t tmp_ = RREG32_PLL(reg); \
  792. tmp_ &= (mask); \
  793. tmp_ |= ((val) & ~(mask)); \
  794. WREG32_PLL(reg, tmp_); \
  795. } while (0)
  796. #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
  797. /*
  798. * Indirect registers accessor
  799. */
  800. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  801. {
  802. uint32_t r;
  803. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  804. r = RREG32(RADEON_PCIE_DATA);
  805. return r;
  806. }
  807. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  808. {
  809. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  810. WREG32(RADEON_PCIE_DATA, (v));
  811. }
  812. void r100_pll_errata_after_index(struct radeon_device *rdev);
  813. /*
  814. * ASICs helpers.
  815. */
  816. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  817. (rdev->pdev->device == 0x5969))
  818. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  819. (rdev->family == CHIP_RV200) || \
  820. (rdev->family == CHIP_RS100) || \
  821. (rdev->family == CHIP_RS200) || \
  822. (rdev->family == CHIP_RV250) || \
  823. (rdev->family == CHIP_RV280) || \
  824. (rdev->family == CHIP_RS300))
  825. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
  826. (rdev->family == CHIP_RV350) || \
  827. (rdev->family == CHIP_R350) || \
  828. (rdev->family == CHIP_RV380) || \
  829. (rdev->family == CHIP_R420) || \
  830. (rdev->family == CHIP_R423) || \
  831. (rdev->family == CHIP_RV410) || \
  832. (rdev->family == CHIP_RS400) || \
  833. (rdev->family == CHIP_RS480))
  834. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  835. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  836. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  837. /*
  838. * BIOS helpers.
  839. */
  840. #define RBIOS8(i) (rdev->bios[i])
  841. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  842. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  843. int radeon_combios_init(struct radeon_device *rdev);
  844. void radeon_combios_fini(struct radeon_device *rdev);
  845. int radeon_atombios_init(struct radeon_device *rdev);
  846. void radeon_atombios_fini(struct radeon_device *rdev);
  847. /*
  848. * RING helpers.
  849. */
  850. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  851. {
  852. #if DRM_DEBUG_CODE
  853. if (rdev->cp.count_dw <= 0) {
  854. DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  855. }
  856. #endif
  857. rdev->cp.ring[rdev->cp.wptr++] = v;
  858. rdev->cp.wptr &= rdev->cp.ptr_mask;
  859. rdev->cp.count_dw--;
  860. rdev->cp.ring_free_dw--;
  861. }
  862. /*
  863. * ASICs macro.
  864. */
  865. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  866. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  867. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  868. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  869. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  870. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  871. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  872. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  873. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  874. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  875. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  876. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  877. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  878. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  879. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  880. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  881. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  882. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  883. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  884. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  885. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  886. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  887. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  888. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  889. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  890. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  891. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  892. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  893. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  894. #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
  895. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  896. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  897. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  898. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  899. /* Common functions */
  900. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  901. extern int radeon_modeset_init(struct radeon_device *rdev);
  902. extern void radeon_modeset_fini(struct radeon_device *rdev);
  903. extern bool radeon_card_posted(struct radeon_device *rdev);
  904. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  905. extern int radeon_clocks_init(struct radeon_device *rdev);
  906. extern void radeon_clocks_fini(struct radeon_device *rdev);
  907. extern void radeon_scratch_init(struct radeon_device *rdev);
  908. extern void radeon_surface_init(struct radeon_device *rdev);
  909. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  910. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  911. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  912. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  913. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  914. struct r100_mc_save {
  915. u32 GENMO_WT;
  916. u32 CRTC_EXT_CNTL;
  917. u32 CRTC_GEN_CNTL;
  918. u32 CRTC2_GEN_CNTL;
  919. u32 CUR_OFFSET;
  920. u32 CUR2_OFFSET;
  921. };
  922. extern void r100_cp_disable(struct radeon_device *rdev);
  923. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  924. extern void r100_cp_fini(struct radeon_device *rdev);
  925. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  926. extern int r100_pci_gart_init(struct radeon_device *rdev);
  927. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  928. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  929. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  930. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  931. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  932. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  933. extern void r100_ib_fini(struct radeon_device *rdev);
  934. extern int r100_ib_init(struct radeon_device *rdev);
  935. extern void r100_irq_disable(struct radeon_device *rdev);
  936. extern int r100_irq_set(struct radeon_device *rdev);
  937. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  938. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  939. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  940. extern void r100_wb_disable(struct radeon_device *rdev);
  941. extern void r100_wb_fini(struct radeon_device *rdev);
  942. extern int r100_wb_init(struct radeon_device *rdev);
  943. extern void r100_hdp_reset(struct radeon_device *rdev);
  944. extern int r100_rb2d_reset(struct radeon_device *rdev);
  945. extern int r100_cp_reset(struct radeon_device *rdev);
  946. extern void r100_vga_render_disable(struct radeon_device *rdev);
  947. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  948. struct radeon_cs_packet *pkt,
  949. struct radeon_bo *robj);
  950. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  951. struct radeon_cs_packet *pkt,
  952. const unsigned *auth, unsigned n,
  953. radeon_packet0_check_t check);
  954. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  955. struct radeon_cs_packet *pkt,
  956. unsigned idx);
  957. extern void r100_enable_bm(struct radeon_device *rdev);
  958. extern void r100_set_common_regs(struct radeon_device *rdev);
  959. /* rv200,rv250,rv280 */
  960. extern void r200_set_safe_registers(struct radeon_device *rdev);
  961. /* r300,r350,rv350,rv370,rv380 */
  962. extern void r300_set_reg_safe(struct radeon_device *rdev);
  963. extern void r300_mc_program(struct radeon_device *rdev);
  964. extern void r300_vram_info(struct radeon_device *rdev);
  965. extern void r300_clock_startup(struct radeon_device *rdev);
  966. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  967. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  968. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  969. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  970. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  971. /* r420,r423,rv410 */
  972. extern int r420_mc_init(struct radeon_device *rdev);
  973. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  974. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  975. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  976. extern void r420_pipes_init(struct radeon_device *rdev);
  977. /* rv515 */
  978. struct rv515_mc_save {
  979. u32 d1vga_control;
  980. u32 d2vga_control;
  981. u32 vga_render_control;
  982. u32 vga_hdp_control;
  983. u32 d1crtc_control;
  984. u32 d2crtc_control;
  985. };
  986. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  987. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  988. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  989. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  990. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  991. extern void rv515_clock_startup(struct radeon_device *rdev);
  992. extern void rv515_debugfs(struct radeon_device *rdev);
  993. extern int rv515_suspend(struct radeon_device *rdev);
  994. /* rs400 */
  995. extern int rs400_gart_init(struct radeon_device *rdev);
  996. extern int rs400_gart_enable(struct radeon_device *rdev);
  997. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  998. extern void rs400_gart_disable(struct radeon_device *rdev);
  999. extern void rs400_gart_fini(struct radeon_device *rdev);
  1000. /* rs600 */
  1001. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1002. extern int rs600_irq_set(struct radeon_device *rdev);
  1003. extern void rs600_irq_disable(struct radeon_device *rdev);
  1004. /* rs690, rs740 */
  1005. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1006. struct drm_display_mode *mode1,
  1007. struct drm_display_mode *mode2);
  1008. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1009. extern bool r600_card_posted(struct radeon_device *rdev);
  1010. extern void r600_cp_stop(struct radeon_device *rdev);
  1011. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1012. extern int r600_cp_resume(struct radeon_device *rdev);
  1013. extern int r600_count_pipe_bits(uint32_t val);
  1014. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1015. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1016. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1017. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1018. extern int r600_ib_test(struct radeon_device *rdev);
  1019. extern int r600_ring_test(struct radeon_device *rdev);
  1020. extern void r600_wb_fini(struct radeon_device *rdev);
  1021. extern int r600_wb_enable(struct radeon_device *rdev);
  1022. extern void r600_wb_disable(struct radeon_device *rdev);
  1023. extern void r600_scratch_init(struct radeon_device *rdev);
  1024. extern int r600_blit_init(struct radeon_device *rdev);
  1025. extern void r600_blit_fini(struct radeon_device *rdev);
  1026. extern int r600_init_microcode(struct radeon_device *rdev);
  1027. extern int r600_gpu_reset(struct radeon_device *rdev);
  1028. /* r600 irq */
  1029. extern int r600_irq_init(struct radeon_device *rdev);
  1030. extern void r600_irq_fini(struct radeon_device *rdev);
  1031. extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1032. extern int r600_irq_set(struct radeon_device *rdev);
  1033. #include "radeon_object.h"
  1034. #endif