cm4040_cs.c 17 KB

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  1. /*
  2. * A driver for the Omnikey PCMCIA smartcard reader CardMan 4040
  3. *
  4. * (c) 2000-2004 Omnikey AG (http://www.omnikey.com/)
  5. *
  6. * (C) 2005-2006 Harald Welte <laforge@gnumonks.org>
  7. * - add support for poll()
  8. * - driver cleanup
  9. * - add waitqueues
  10. * - adhere to linux kernel coding style and policies
  11. * - support 2.6.13 "new style" pcmcia interface
  12. * - add class interface for udev device creation
  13. *
  14. * The device basically is a USB CCID compliant device that has been
  15. * attached to an I/O-Mapped FIFO.
  16. *
  17. * All rights reserved, Dual BSD/GPL Licensed.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/slab.h>
  22. #include <linux/init.h>
  23. #include <linux/fs.h>
  24. #include <linux/delay.h>
  25. #include <linux/poll.h>
  26. #include <linux/smp_lock.h>
  27. #include <linux/wait.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/io.h>
  30. #include <pcmcia/cs_types.h>
  31. #include <pcmcia/cs.h>
  32. #include <pcmcia/cistpl.h>
  33. #include <pcmcia/cisreg.h>
  34. #include <pcmcia/ciscode.h>
  35. #include <pcmcia/ds.h>
  36. #include "cm4040_cs.h"
  37. #define reader_to_dev(x) (&x->p_dev->dev)
  38. /* n (debug level) is ignored */
  39. /* additional debug output may be enabled by re-compiling with
  40. * CM4040_DEBUG set */
  41. /* #define CM4040_DEBUG */
  42. #define DEBUGP(n, rdr, x, args...) do { \
  43. dev_dbg(reader_to_dev(rdr), "%s:" x, \
  44. __func__ , ## args); \
  45. } while (0)
  46. static char *version =
  47. "OMNIKEY CardMan 4040 v1.1.0gm5 - All bugs added by Harald Welte";
  48. #define CCID_DRIVER_BULK_DEFAULT_TIMEOUT (150*HZ)
  49. #define CCID_DRIVER_ASYNC_POWERUP_TIMEOUT (35*HZ)
  50. #define CCID_DRIVER_MINIMUM_TIMEOUT (3*HZ)
  51. #define READ_WRITE_BUFFER_SIZE 512
  52. #define POLL_LOOP_COUNT 1000
  53. /* how often to poll for fifo status change */
  54. #define POLL_PERIOD msecs_to_jiffies(10)
  55. static void reader_release(struct pcmcia_device *link);
  56. static int major;
  57. static struct class *cmx_class;
  58. #define BS_READABLE 0x01
  59. #define BS_WRITABLE 0x02
  60. struct reader_dev {
  61. struct pcmcia_device *p_dev;
  62. dev_node_t node;
  63. wait_queue_head_t devq;
  64. wait_queue_head_t poll_wait;
  65. wait_queue_head_t read_wait;
  66. wait_queue_head_t write_wait;
  67. unsigned long buffer_status;
  68. unsigned long timeout;
  69. unsigned char s_buf[READ_WRITE_BUFFER_SIZE];
  70. unsigned char r_buf[READ_WRITE_BUFFER_SIZE];
  71. struct timer_list poll_timer;
  72. };
  73. static struct pcmcia_device *dev_table[CM_MAX_DEV];
  74. #ifndef CM4040_DEBUG
  75. #define xoutb outb
  76. #define xinb inb
  77. #else
  78. static inline void xoutb(unsigned char val, unsigned short port)
  79. {
  80. pr_debug("outb(val=%.2x,port=%.4x)\n", val, port);
  81. outb(val, port);
  82. }
  83. static inline unsigned char xinb(unsigned short port)
  84. {
  85. unsigned char val;
  86. val = inb(port);
  87. pr_debug("%.2x=inb(%.4x)\n", val, port);
  88. return val;
  89. }
  90. #endif
  91. /* poll the device fifo status register. not to be confused with
  92. * the poll syscall. */
  93. static void cm4040_do_poll(unsigned long dummy)
  94. {
  95. struct reader_dev *dev = (struct reader_dev *) dummy;
  96. unsigned int obs = xinb(dev->p_dev->io.BasePort1
  97. + REG_OFFSET_BUFFER_STATUS);
  98. if ((obs & BSR_BULK_IN_FULL)) {
  99. set_bit(BS_READABLE, &dev->buffer_status);
  100. DEBUGP(4, dev, "waking up read_wait\n");
  101. wake_up_interruptible(&dev->read_wait);
  102. } else
  103. clear_bit(BS_READABLE, &dev->buffer_status);
  104. if (!(obs & BSR_BULK_OUT_FULL)) {
  105. set_bit(BS_WRITABLE, &dev->buffer_status);
  106. DEBUGP(4, dev, "waking up write_wait\n");
  107. wake_up_interruptible(&dev->write_wait);
  108. } else
  109. clear_bit(BS_WRITABLE, &dev->buffer_status);
  110. if (dev->buffer_status)
  111. wake_up_interruptible(&dev->poll_wait);
  112. mod_timer(&dev->poll_timer, jiffies + POLL_PERIOD);
  113. }
  114. static void cm4040_stop_poll(struct reader_dev *dev)
  115. {
  116. del_timer_sync(&dev->poll_timer);
  117. }
  118. static int wait_for_bulk_out_ready(struct reader_dev *dev)
  119. {
  120. int i, rc;
  121. int iobase = dev->p_dev->io.BasePort1;
  122. for (i = 0; i < POLL_LOOP_COUNT; i++) {
  123. if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS)
  124. & BSR_BULK_OUT_FULL) == 0) {
  125. DEBUGP(4, dev, "BulkOut empty (i=%d)\n", i);
  126. return 1;
  127. }
  128. }
  129. DEBUGP(4, dev, "wait_event_interruptible_timeout(timeout=%ld\n",
  130. dev->timeout);
  131. rc = wait_event_interruptible_timeout(dev->write_wait,
  132. test_and_clear_bit(BS_WRITABLE,
  133. &dev->buffer_status),
  134. dev->timeout);
  135. if (rc > 0)
  136. DEBUGP(4, dev, "woke up: BulkOut empty\n");
  137. else if (rc == 0)
  138. DEBUGP(4, dev, "woke up: BulkOut full, returning 0 :(\n");
  139. else if (rc < 0)
  140. DEBUGP(4, dev, "woke up: signal arrived\n");
  141. return rc;
  142. }
  143. /* Write to Sync Control Register */
  144. static int write_sync_reg(unsigned char val, struct reader_dev *dev)
  145. {
  146. int iobase = dev->p_dev->io.BasePort1;
  147. int rc;
  148. rc = wait_for_bulk_out_ready(dev);
  149. if (rc <= 0)
  150. return rc;
  151. xoutb(val, iobase + REG_OFFSET_SYNC_CONTROL);
  152. rc = wait_for_bulk_out_ready(dev);
  153. if (rc <= 0)
  154. return rc;
  155. return 1;
  156. }
  157. static int wait_for_bulk_in_ready(struct reader_dev *dev)
  158. {
  159. int i, rc;
  160. int iobase = dev->p_dev->io.BasePort1;
  161. for (i = 0; i < POLL_LOOP_COUNT; i++) {
  162. if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS)
  163. & BSR_BULK_IN_FULL) == BSR_BULK_IN_FULL) {
  164. DEBUGP(3, dev, "BulkIn full (i=%d)\n", i);
  165. return 1;
  166. }
  167. }
  168. DEBUGP(4, dev, "wait_event_interruptible_timeout(timeout=%ld\n",
  169. dev->timeout);
  170. rc = wait_event_interruptible_timeout(dev->read_wait,
  171. test_and_clear_bit(BS_READABLE,
  172. &dev->buffer_status),
  173. dev->timeout);
  174. if (rc > 0)
  175. DEBUGP(4, dev, "woke up: BulkIn full\n");
  176. else if (rc == 0)
  177. DEBUGP(4, dev, "woke up: BulkIn not full, returning 0 :(\n");
  178. else if (rc < 0)
  179. DEBUGP(4, dev, "woke up: signal arrived\n");
  180. return rc;
  181. }
  182. static ssize_t cm4040_read(struct file *filp, char __user *buf,
  183. size_t count, loff_t *ppos)
  184. {
  185. struct reader_dev *dev = filp->private_data;
  186. int iobase = dev->p_dev->io.BasePort1;
  187. size_t bytes_to_read;
  188. unsigned long i;
  189. size_t min_bytes_to_read;
  190. int rc;
  191. unsigned char uc;
  192. DEBUGP(2, dev, "-> cm4040_read(%s,%d)\n", current->comm, current->pid);
  193. if (count == 0)
  194. return 0;
  195. if (count < 10)
  196. return -EFAULT;
  197. if (filp->f_flags & O_NONBLOCK) {
  198. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  199. DEBUGP(2, dev, "<- cm4040_read (failure)\n");
  200. return -EAGAIN;
  201. }
  202. if (!pcmcia_dev_present(dev->p_dev))
  203. return -ENODEV;
  204. for (i = 0; i < 5; i++) {
  205. rc = wait_for_bulk_in_ready(dev);
  206. if (rc <= 0) {
  207. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  208. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  209. if (rc == -ERESTARTSYS)
  210. return rc;
  211. return -EIO;
  212. }
  213. dev->r_buf[i] = xinb(iobase + REG_OFFSET_BULK_IN);
  214. #ifdef CM4040_DEBUG
  215. pr_debug("%lu:%2x ", i, dev->r_buf[i]);
  216. }
  217. pr_debug("\n");
  218. #else
  219. }
  220. #endif
  221. bytes_to_read = 5 + le32_to_cpu(*(__le32 *)&dev->r_buf[1]);
  222. DEBUGP(6, dev, "BytesToRead=%zu\n", bytes_to_read);
  223. min_bytes_to_read = min(count, bytes_to_read + 5);
  224. min_bytes_to_read = min_t(size_t, min_bytes_to_read, READ_WRITE_BUFFER_SIZE);
  225. DEBUGP(6, dev, "Min=%zu\n", min_bytes_to_read);
  226. for (i = 0; i < (min_bytes_to_read-5); i++) {
  227. rc = wait_for_bulk_in_ready(dev);
  228. if (rc <= 0) {
  229. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  230. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  231. if (rc == -ERESTARTSYS)
  232. return rc;
  233. return -EIO;
  234. }
  235. dev->r_buf[i+5] = xinb(iobase + REG_OFFSET_BULK_IN);
  236. #ifdef CM4040_DEBUG
  237. pr_debug("%lu:%2x ", i, dev->r_buf[i]);
  238. }
  239. pr_debug("\n");
  240. #else
  241. }
  242. #endif
  243. *ppos = min_bytes_to_read;
  244. if (copy_to_user(buf, dev->r_buf, min_bytes_to_read))
  245. return -EFAULT;
  246. rc = wait_for_bulk_in_ready(dev);
  247. if (rc <= 0) {
  248. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  249. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  250. if (rc == -ERESTARTSYS)
  251. return rc;
  252. return -EIO;
  253. }
  254. rc = write_sync_reg(SCR_READER_TO_HOST_DONE, dev);
  255. if (rc <= 0) {
  256. DEBUGP(5, dev, "write_sync_reg c=%.2x\n", rc);
  257. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  258. if (rc == -ERESTARTSYS)
  259. return rc;
  260. else
  261. return -EIO;
  262. }
  263. uc = xinb(iobase + REG_OFFSET_BULK_IN);
  264. DEBUGP(2, dev, "<- cm4040_read (successfully)\n");
  265. return min_bytes_to_read;
  266. }
  267. static ssize_t cm4040_write(struct file *filp, const char __user *buf,
  268. size_t count, loff_t *ppos)
  269. {
  270. struct reader_dev *dev = filp->private_data;
  271. int iobase = dev->p_dev->io.BasePort1;
  272. ssize_t rc;
  273. int i;
  274. unsigned int bytes_to_write;
  275. DEBUGP(2, dev, "-> cm4040_write(%s,%d)\n", current->comm, current->pid);
  276. if (count == 0) {
  277. DEBUGP(2, dev, "<- cm4040_write empty read (successfully)\n");
  278. return 0;
  279. }
  280. if ((count < 5) || (count > READ_WRITE_BUFFER_SIZE)) {
  281. DEBUGP(2, dev, "<- cm4040_write buffersize=%Zd < 5\n", count);
  282. return -EIO;
  283. }
  284. if (filp->f_flags & O_NONBLOCK) {
  285. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  286. DEBUGP(4, dev, "<- cm4040_write (failure)\n");
  287. return -EAGAIN;
  288. }
  289. if (!pcmcia_dev_present(dev->p_dev))
  290. return -ENODEV;
  291. bytes_to_write = count;
  292. if (copy_from_user(dev->s_buf, buf, bytes_to_write))
  293. return -EFAULT;
  294. switch (dev->s_buf[0]) {
  295. case CMD_PC_TO_RDR_XFRBLOCK:
  296. case CMD_PC_TO_RDR_SECURE:
  297. case CMD_PC_TO_RDR_TEST_SECURE:
  298. case CMD_PC_TO_RDR_OK_SECURE:
  299. dev->timeout = CCID_DRIVER_BULK_DEFAULT_TIMEOUT;
  300. break;
  301. case CMD_PC_TO_RDR_ICCPOWERON:
  302. dev->timeout = CCID_DRIVER_ASYNC_POWERUP_TIMEOUT;
  303. break;
  304. case CMD_PC_TO_RDR_GETSLOTSTATUS:
  305. case CMD_PC_TO_RDR_ICCPOWEROFF:
  306. case CMD_PC_TO_RDR_GETPARAMETERS:
  307. case CMD_PC_TO_RDR_RESETPARAMETERS:
  308. case CMD_PC_TO_RDR_SETPARAMETERS:
  309. case CMD_PC_TO_RDR_ESCAPE:
  310. case CMD_PC_TO_RDR_ICCCLOCK:
  311. default:
  312. dev->timeout = CCID_DRIVER_MINIMUM_TIMEOUT;
  313. break;
  314. }
  315. rc = write_sync_reg(SCR_HOST_TO_READER_START, dev);
  316. if (rc <= 0) {
  317. DEBUGP(5, dev, "write_sync_reg c=%.2Zx\n", rc);
  318. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  319. if (rc == -ERESTARTSYS)
  320. return rc;
  321. else
  322. return -EIO;
  323. }
  324. DEBUGP(4, dev, "start \n");
  325. for (i = 0; i < bytes_to_write; i++) {
  326. rc = wait_for_bulk_out_ready(dev);
  327. if (rc <= 0) {
  328. DEBUGP(5, dev, "wait_for_bulk_out_ready rc=%.2Zx\n",
  329. rc);
  330. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  331. if (rc == -ERESTARTSYS)
  332. return rc;
  333. else
  334. return -EIO;
  335. }
  336. xoutb(dev->s_buf[i],iobase + REG_OFFSET_BULK_OUT);
  337. }
  338. DEBUGP(4, dev, "end\n");
  339. rc = write_sync_reg(SCR_HOST_TO_READER_DONE, dev);
  340. if (rc <= 0) {
  341. DEBUGP(5, dev, "write_sync_reg c=%.2Zx\n", rc);
  342. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  343. if (rc == -ERESTARTSYS)
  344. return rc;
  345. else
  346. return -EIO;
  347. }
  348. DEBUGP(2, dev, "<- cm4040_write (successfully)\n");
  349. return count;
  350. }
  351. static unsigned int cm4040_poll(struct file *filp, poll_table *wait)
  352. {
  353. struct reader_dev *dev = filp->private_data;
  354. unsigned int mask = 0;
  355. poll_wait(filp, &dev->poll_wait, wait);
  356. if (test_and_clear_bit(BS_READABLE, &dev->buffer_status))
  357. mask |= POLLIN | POLLRDNORM;
  358. if (test_and_clear_bit(BS_WRITABLE, &dev->buffer_status))
  359. mask |= POLLOUT | POLLWRNORM;
  360. DEBUGP(2, dev, "<- cm4040_poll(%u)\n", mask);
  361. return mask;
  362. }
  363. static int cm4040_open(struct inode *inode, struct file *filp)
  364. {
  365. struct reader_dev *dev;
  366. struct pcmcia_device *link;
  367. int minor = iminor(inode);
  368. int ret;
  369. if (minor >= CM_MAX_DEV)
  370. return -ENODEV;
  371. lock_kernel();
  372. link = dev_table[minor];
  373. if (link == NULL || !pcmcia_dev_present(link)) {
  374. ret = -ENODEV;
  375. goto out;
  376. }
  377. if (link->open) {
  378. ret = -EBUSY;
  379. goto out;
  380. }
  381. dev = link->priv;
  382. filp->private_data = dev;
  383. if (filp->f_flags & O_NONBLOCK) {
  384. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  385. ret = -EAGAIN;
  386. goto out;
  387. }
  388. link->open = 1;
  389. dev->poll_timer.data = (unsigned long) dev;
  390. mod_timer(&dev->poll_timer, jiffies + POLL_PERIOD);
  391. DEBUGP(2, dev, "<- cm4040_open (successfully)\n");
  392. ret = nonseekable_open(inode, filp);
  393. out:
  394. unlock_kernel();
  395. return ret;
  396. }
  397. static int cm4040_close(struct inode *inode, struct file *filp)
  398. {
  399. struct reader_dev *dev = filp->private_data;
  400. struct pcmcia_device *link;
  401. int minor = iminor(inode);
  402. DEBUGP(2, dev, "-> cm4040_close(maj/min=%d.%d)\n", imajor(inode),
  403. iminor(inode));
  404. if (minor >= CM_MAX_DEV)
  405. return -ENODEV;
  406. link = dev_table[minor];
  407. if (link == NULL)
  408. return -ENODEV;
  409. cm4040_stop_poll(dev);
  410. link->open = 0;
  411. wake_up(&dev->devq);
  412. DEBUGP(2, dev, "<- cm4040_close\n");
  413. return 0;
  414. }
  415. static void cm4040_reader_release(struct pcmcia_device *link)
  416. {
  417. struct reader_dev *dev = link->priv;
  418. DEBUGP(3, dev, "-> cm4040_reader_release\n");
  419. while (link->open) {
  420. DEBUGP(3, dev, KERN_INFO MODULE_NAME ": delaying release "
  421. "until process has terminated\n");
  422. wait_event(dev->devq, (link->open == 0));
  423. }
  424. DEBUGP(3, dev, "<- cm4040_reader_release\n");
  425. return;
  426. }
  427. static int cm4040_config_check(struct pcmcia_device *p_dev,
  428. cistpl_cftable_entry_t *cfg,
  429. cistpl_cftable_entry_t *dflt,
  430. unsigned int vcc,
  431. void *priv_data)
  432. {
  433. int rc;
  434. if (!cfg->io.nwin)
  435. return -ENODEV;
  436. /* Get the IOaddr */
  437. p_dev->io.BasePort1 = cfg->io.win[0].base;
  438. p_dev->io.NumPorts1 = cfg->io.win[0].len;
  439. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  440. if (!(cfg->io.flags & CISTPL_IO_8BIT))
  441. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  442. if (!(cfg->io.flags & CISTPL_IO_16BIT))
  443. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  444. p_dev->io.IOAddrLines = cfg->io.flags & CISTPL_IO_LINES_MASK;
  445. rc = pcmcia_request_io(p_dev, &p_dev->io);
  446. dev_printk(KERN_INFO, &p_dev->dev,
  447. "pcmcia_request_io returned 0x%x\n", rc);
  448. return rc;
  449. }
  450. static int reader_config(struct pcmcia_device *link, int devno)
  451. {
  452. struct reader_dev *dev;
  453. int fail_rc;
  454. link->io.BasePort2 = 0;
  455. link->io.NumPorts2 = 0;
  456. link->io.Attributes2 = 0;
  457. if (pcmcia_loop_config(link, cm4040_config_check, NULL))
  458. goto cs_release;
  459. link->conf.IntType = 00000002;
  460. fail_rc = pcmcia_request_configuration(link, &link->conf);
  461. if (fail_rc != 0) {
  462. dev_printk(KERN_INFO, &link->dev,
  463. "pcmcia_request_configuration failed 0x%x\n",
  464. fail_rc);
  465. goto cs_release;
  466. }
  467. dev = link->priv;
  468. sprintf(dev->node.dev_name, DEVICE_NAME "%d", devno);
  469. dev->node.major = major;
  470. dev->node.minor = devno;
  471. dev->node.next = &dev->node;
  472. DEBUGP(2, dev, "device " DEVICE_NAME "%d at 0x%.4x-0x%.4x\n", devno,
  473. link->io.BasePort1, link->io.BasePort1+link->io.NumPorts1);
  474. DEBUGP(2, dev, "<- reader_config (succ)\n");
  475. return 0;
  476. cs_release:
  477. reader_release(link);
  478. return -ENODEV;
  479. }
  480. static void reader_release(struct pcmcia_device *link)
  481. {
  482. cm4040_reader_release(link);
  483. pcmcia_disable_device(link);
  484. }
  485. static int reader_probe(struct pcmcia_device *link)
  486. {
  487. struct reader_dev *dev;
  488. int i, ret;
  489. for (i = 0; i < CM_MAX_DEV; i++) {
  490. if (dev_table[i] == NULL)
  491. break;
  492. }
  493. if (i == CM_MAX_DEV)
  494. return -ENODEV;
  495. dev = kzalloc(sizeof(struct reader_dev), GFP_KERNEL);
  496. if (dev == NULL)
  497. return -ENOMEM;
  498. dev->timeout = CCID_DRIVER_MINIMUM_TIMEOUT;
  499. dev->buffer_status = 0;
  500. link->priv = dev;
  501. dev->p_dev = link;
  502. link->conf.IntType = INT_MEMORY_AND_IO;
  503. dev_table[i] = link;
  504. init_waitqueue_head(&dev->devq);
  505. init_waitqueue_head(&dev->poll_wait);
  506. init_waitqueue_head(&dev->read_wait);
  507. init_waitqueue_head(&dev->write_wait);
  508. setup_timer(&dev->poll_timer, cm4040_do_poll, 0);
  509. ret = reader_config(link, i);
  510. if (ret) {
  511. dev_table[i] = NULL;
  512. kfree(dev);
  513. return ret;
  514. }
  515. device_create(cmx_class, NULL, MKDEV(major, i), NULL, "cmx%d", i);
  516. return 0;
  517. }
  518. static void reader_detach(struct pcmcia_device *link)
  519. {
  520. struct reader_dev *dev = link->priv;
  521. int devno;
  522. /* find device */
  523. for (devno = 0; devno < CM_MAX_DEV; devno++) {
  524. if (dev_table[devno] == link)
  525. break;
  526. }
  527. if (devno == CM_MAX_DEV)
  528. return;
  529. reader_release(link);
  530. dev_table[devno] = NULL;
  531. kfree(dev);
  532. device_destroy(cmx_class, MKDEV(major, devno));
  533. return;
  534. }
  535. static const struct file_operations reader_fops = {
  536. .owner = THIS_MODULE,
  537. .read = cm4040_read,
  538. .write = cm4040_write,
  539. .open = cm4040_open,
  540. .release = cm4040_close,
  541. .poll = cm4040_poll,
  542. };
  543. static struct pcmcia_device_id cm4040_ids[] = {
  544. PCMCIA_DEVICE_MANF_CARD(0x0223, 0x0200),
  545. PCMCIA_DEVICE_PROD_ID12("OMNIKEY", "CardMan 4040",
  546. 0xE32CDD8C, 0x8F23318B),
  547. PCMCIA_DEVICE_NULL,
  548. };
  549. MODULE_DEVICE_TABLE(pcmcia, cm4040_ids);
  550. static struct pcmcia_driver reader_driver = {
  551. .owner = THIS_MODULE,
  552. .drv = {
  553. .name = "cm4040_cs",
  554. },
  555. .probe = reader_probe,
  556. .remove = reader_detach,
  557. .id_table = cm4040_ids,
  558. };
  559. static int __init cm4040_init(void)
  560. {
  561. int rc;
  562. printk(KERN_INFO "%s\n", version);
  563. cmx_class = class_create(THIS_MODULE, "cardman_4040");
  564. if (IS_ERR(cmx_class))
  565. return PTR_ERR(cmx_class);
  566. major = register_chrdev(0, DEVICE_NAME, &reader_fops);
  567. if (major < 0) {
  568. printk(KERN_WARNING MODULE_NAME
  569. ": could not get major number\n");
  570. class_destroy(cmx_class);
  571. return major;
  572. }
  573. rc = pcmcia_register_driver(&reader_driver);
  574. if (rc < 0) {
  575. unregister_chrdev(major, DEVICE_NAME);
  576. class_destroy(cmx_class);
  577. return rc;
  578. }
  579. return 0;
  580. }
  581. static void __exit cm4040_exit(void)
  582. {
  583. printk(KERN_INFO MODULE_NAME ": unloading\n");
  584. pcmcia_unregister_driver(&reader_driver);
  585. unregister_chrdev(major, DEVICE_NAME);
  586. class_destroy(cmx_class);
  587. }
  588. module_init(cm4040_init);
  589. module_exit(cm4040_exit);
  590. MODULE_LICENSE("Dual BSD/GPL");