setup.c 16 KB

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  1. /*
  2. * Renesas - AP-325RXA
  3. * (Compatible with Algo System ., LTD. - AP-320A)
  4. *
  5. * Copyright (C) 2008 Renesas Solutions Corp.
  6. * Author : Yusuke Goda <goda.yuske@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/mtd/sh_flctl.h>
  18. #include <linux/delay.h>
  19. #include <linux/i2c.h>
  20. #include <linux/smsc911x.h>
  21. #include <linux/gpio.h>
  22. #include <media/ov772x.h>
  23. #include <media/soc_camera.h>
  24. #include <media/soc_camera_platform.h>
  25. #include <media/sh_mobile_ceu.h>
  26. #include <video/sh_mobile_lcdc.h>
  27. #include <asm/io.h>
  28. #include <asm/clock.h>
  29. #include <asm/suspend.h>
  30. #include <cpu/sh7723.h>
  31. static struct smsc911x_platform_config smsc911x_config = {
  32. .phy_interface = PHY_INTERFACE_MODE_MII,
  33. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  34. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  35. .flags = SMSC911X_USE_32BIT,
  36. };
  37. static struct resource smsc9118_resources[] = {
  38. [0] = {
  39. .start = 0xb6080000,
  40. .end = 0xb60fffff,
  41. .flags = IORESOURCE_MEM,
  42. },
  43. [1] = {
  44. .start = 35,
  45. .end = 35,
  46. .flags = IORESOURCE_IRQ,
  47. }
  48. };
  49. static struct platform_device smsc9118_device = {
  50. .name = "smsc911x",
  51. .id = -1,
  52. .num_resources = ARRAY_SIZE(smsc9118_resources),
  53. .resource = smsc9118_resources,
  54. .dev = {
  55. .platform_data = &smsc911x_config,
  56. },
  57. };
  58. /*
  59. * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
  60. * If this area erased, this board can not boot.
  61. */
  62. static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
  63. {
  64. .name = "uboot",
  65. .offset = 0,
  66. .size = (1 * 1024 * 1024),
  67. .mask_flags = MTD_WRITEABLE, /* Read-only */
  68. }, {
  69. .name = "kernel",
  70. .offset = MTDPART_OFS_APPEND,
  71. .size = (2 * 1024 * 1024),
  72. }, {
  73. .name = "free-area0",
  74. .offset = MTDPART_OFS_APPEND,
  75. .size = ((7 * 1024 * 1024) + (512 * 1024)),
  76. }, {
  77. .name = "CPLD-Data",
  78. .offset = MTDPART_OFS_APPEND,
  79. .mask_flags = MTD_WRITEABLE, /* Read-only */
  80. .size = (1024 * 128 * 2),
  81. }, {
  82. .name = "free-area1",
  83. .offset = MTDPART_OFS_APPEND,
  84. .size = MTDPART_SIZ_FULL,
  85. },
  86. };
  87. static struct physmap_flash_data ap325rxa_nor_flash_data = {
  88. .width = 2,
  89. .parts = ap325rxa_nor_flash_partitions,
  90. .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
  91. };
  92. static struct resource ap325rxa_nor_flash_resources[] = {
  93. [0] = {
  94. .name = "NOR Flash",
  95. .start = 0x00000000,
  96. .end = 0x00ffffff,
  97. .flags = IORESOURCE_MEM,
  98. }
  99. };
  100. static struct platform_device ap325rxa_nor_flash_device = {
  101. .name = "physmap-flash",
  102. .resource = ap325rxa_nor_flash_resources,
  103. .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
  104. .dev = {
  105. .platform_data = &ap325rxa_nor_flash_data,
  106. },
  107. };
  108. static struct mtd_partition nand_partition_info[] = {
  109. {
  110. .name = "nand_data",
  111. .offset = 0,
  112. .size = MTDPART_SIZ_FULL,
  113. },
  114. };
  115. static struct resource nand_flash_resources[] = {
  116. [0] = {
  117. .start = 0xa4530000,
  118. .end = 0xa45300ff,
  119. .flags = IORESOURCE_MEM,
  120. }
  121. };
  122. static struct sh_flctl_platform_data nand_flash_data = {
  123. .parts = nand_partition_info,
  124. .nr_parts = ARRAY_SIZE(nand_partition_info),
  125. .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
  126. .has_hwecc = 1,
  127. };
  128. static struct platform_device nand_flash_device = {
  129. .name = "sh_flctl",
  130. .resource = nand_flash_resources,
  131. .num_resources = ARRAY_SIZE(nand_flash_resources),
  132. .dev = {
  133. .platform_data = &nand_flash_data,
  134. },
  135. };
  136. #define FPGA_LCDREG 0xB4100180
  137. #define FPGA_BKLREG 0xB4100212
  138. #define FPGA_LCDREG_VAL 0x0018
  139. #define PORT_MSELCRB 0xA4050182
  140. #define PORT_HIZCRC 0xA405015C
  141. #define PORT_DRVCRA 0xA405018A
  142. #define PORT_DRVCRB 0xA405018C
  143. static void ap320_wvga_power_on(void *board_data)
  144. {
  145. msleep(100);
  146. /* ASD AP-320/325 LCD ON */
  147. ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
  148. /* backlight */
  149. gpio_set_value(GPIO_PTS3, 0);
  150. ctrl_outw(0x100, FPGA_BKLREG);
  151. }
  152. static void ap320_wvga_power_off(void *board_data)
  153. {
  154. /* backlight */
  155. ctrl_outw(0, FPGA_BKLREG);
  156. gpio_set_value(GPIO_PTS3, 1);
  157. /* ASD AP-320/325 LCD OFF */
  158. ctrl_outw(0, FPGA_LCDREG);
  159. }
  160. static struct sh_mobile_lcdc_info lcdc_info = {
  161. .clock_source = LCDC_CLK_EXTERNAL,
  162. .ch[0] = {
  163. .chan = LCDC_CHAN_MAINLCD,
  164. .bpp = 16,
  165. .interface_type = RGB18,
  166. .clock_divider = 1,
  167. .lcd_cfg = {
  168. .name = "LB070WV1",
  169. .xres = 800,
  170. .yres = 480,
  171. .left_margin = 32,
  172. .right_margin = 160,
  173. .hsync_len = 8,
  174. .upper_margin = 63,
  175. .lower_margin = 80,
  176. .vsync_len = 1,
  177. .sync = 0, /* hsync and vsync are active low */
  178. },
  179. .lcd_size_cfg = { /* 7.0 inch */
  180. .width = 152,
  181. .height = 91,
  182. },
  183. .board_cfg = {
  184. .display_on = ap320_wvga_power_on,
  185. .display_off = ap320_wvga_power_off,
  186. },
  187. }
  188. };
  189. static struct resource lcdc_resources[] = {
  190. [0] = {
  191. .name = "LCDC",
  192. .start = 0xfe940000, /* P4-only space */
  193. .end = 0xfe942fff,
  194. .flags = IORESOURCE_MEM,
  195. },
  196. [1] = {
  197. .start = 28,
  198. .flags = IORESOURCE_IRQ,
  199. },
  200. };
  201. static struct platform_device lcdc_device = {
  202. .name = "sh_mobile_lcdc_fb",
  203. .num_resources = ARRAY_SIZE(lcdc_resources),
  204. .resource = lcdc_resources,
  205. .dev = {
  206. .platform_data = &lcdc_info,
  207. },
  208. .archdata = {
  209. .hwblk_id = HWBLK_LCDC,
  210. },
  211. };
  212. static void camera_power(int val)
  213. {
  214. gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
  215. mdelay(10);
  216. }
  217. #ifdef CONFIG_I2C
  218. /* support for the old ncm03j camera */
  219. static unsigned char camera_ncm03j_magic[] =
  220. {
  221. 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
  222. 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
  223. 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
  224. 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
  225. 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
  226. 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
  227. 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
  228. 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
  229. 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
  230. 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
  231. 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
  232. 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
  233. 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
  234. 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
  235. 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
  236. 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
  237. };
  238. static int camera_probe(void)
  239. {
  240. struct i2c_adapter *a = i2c_get_adapter(0);
  241. struct i2c_msg msg;
  242. int ret;
  243. if (!a)
  244. return -ENODEV;
  245. camera_power(1);
  246. msg.addr = 0x6e;
  247. msg.buf = camera_ncm03j_magic;
  248. msg.len = 2;
  249. msg.flags = 0;
  250. ret = i2c_transfer(a, &msg, 1);
  251. camera_power(0);
  252. return ret;
  253. }
  254. static int camera_set_capture(struct soc_camera_platform_info *info,
  255. int enable)
  256. {
  257. struct i2c_adapter *a = i2c_get_adapter(0);
  258. struct i2c_msg msg;
  259. int ret = 0;
  260. int i;
  261. camera_power(0);
  262. if (!enable)
  263. return 0; /* no disable for now */
  264. camera_power(1);
  265. for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
  266. u_int8_t buf[8];
  267. msg.addr = 0x6e;
  268. msg.buf = buf;
  269. msg.len = 2;
  270. msg.flags = 0;
  271. buf[0] = camera_ncm03j_magic[i];
  272. buf[1] = camera_ncm03j_magic[i + 1];
  273. ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
  274. }
  275. return ret;
  276. }
  277. static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev);
  278. static void ap325rxa_camera_del(struct soc_camera_link *icl);
  279. static struct soc_camera_platform_info camera_info = {
  280. .format_name = "UYVY",
  281. .format_depth = 16,
  282. .format = {
  283. .pixelformat = V4L2_PIX_FMT_UYVY,
  284. .colorspace = V4L2_COLORSPACE_SMPTE170M,
  285. .width = 640,
  286. .height = 480,
  287. },
  288. .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
  289. SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
  290. .set_capture = camera_set_capture,
  291. .link = {
  292. .bus_id = 0,
  293. .add_device = ap325rxa_camera_add,
  294. .del_device = ap325rxa_camera_del,
  295. .module_name = "soc_camera_platform",
  296. },
  297. };
  298. static void dummy_release(struct device *dev)
  299. {
  300. }
  301. static struct platform_device camera_device = {
  302. .name = "soc_camera_platform",
  303. .dev = {
  304. .platform_data = &camera_info,
  305. .release = dummy_release,
  306. },
  307. };
  308. static int ap325rxa_camera_add(struct soc_camera_link *icl,
  309. struct device *dev)
  310. {
  311. if (icl != &camera_info.link || camera_probe() <= 0)
  312. return -ENODEV;
  313. camera_info.dev = dev;
  314. return platform_device_register(&camera_device);
  315. }
  316. static void ap325rxa_camera_del(struct soc_camera_link *icl)
  317. {
  318. if (icl != &camera_info.link)
  319. return;
  320. platform_device_unregister(&camera_device);
  321. memset(&camera_device.dev.kobj, 0,
  322. sizeof(camera_device.dev.kobj));
  323. }
  324. #endif /* CONFIG_I2C */
  325. static int ov7725_power(struct device *dev, int mode)
  326. {
  327. camera_power(0);
  328. if (mode)
  329. camera_power(1);
  330. return 0;
  331. }
  332. static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
  333. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  334. };
  335. static struct resource ceu_resources[] = {
  336. [0] = {
  337. .name = "CEU",
  338. .start = 0xfe910000,
  339. .end = 0xfe91009f,
  340. .flags = IORESOURCE_MEM,
  341. },
  342. [1] = {
  343. .start = 52,
  344. .flags = IORESOURCE_IRQ,
  345. },
  346. [2] = {
  347. /* place holder for contiguous memory */
  348. },
  349. };
  350. static struct platform_device ceu_device = {
  351. .name = "sh_mobile_ceu",
  352. .id = 0, /* "ceu0" clock */
  353. .num_resources = ARRAY_SIZE(ceu_resources),
  354. .resource = ceu_resources,
  355. .dev = {
  356. .platform_data = &sh_mobile_ceu_info,
  357. },
  358. .archdata = {
  359. .hwblk_id = HWBLK_CEU,
  360. },
  361. };
  362. static struct resource sdhi0_cn3_resources[] = {
  363. [0] = {
  364. .name = "SDHI0",
  365. .start = 0x04ce0000,
  366. .end = 0x04ce01ff,
  367. .flags = IORESOURCE_MEM,
  368. },
  369. [1] = {
  370. .start = 101,
  371. .flags = IORESOURCE_IRQ,
  372. },
  373. };
  374. static struct platform_device sdhi0_cn3_device = {
  375. .name = "sh_mobile_sdhi",
  376. .id = 0, /* "sdhi0" clock */
  377. .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
  378. .resource = sdhi0_cn3_resources,
  379. .archdata = {
  380. .hwblk_id = HWBLK_SDHI0,
  381. },
  382. };
  383. static struct resource sdhi1_cn7_resources[] = {
  384. [0] = {
  385. .name = "SDHI1",
  386. .start = 0x04cf0000,
  387. .end = 0x04cf01ff,
  388. .flags = IORESOURCE_MEM,
  389. },
  390. [1] = {
  391. .start = 24,
  392. .flags = IORESOURCE_IRQ,
  393. },
  394. };
  395. static struct platform_device sdhi1_cn7_device = {
  396. .name = "sh_mobile_sdhi",
  397. .id = 1, /* "sdhi1" clock */
  398. .num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
  399. .resource = sdhi1_cn7_resources,
  400. .archdata = {
  401. .hwblk_id = HWBLK_SDHI1,
  402. },
  403. };
  404. static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
  405. {
  406. I2C_BOARD_INFO("pcf8563", 0x51),
  407. },
  408. };
  409. static struct i2c_board_info ap325rxa_i2c_camera[] = {
  410. {
  411. I2C_BOARD_INFO("ov772x", 0x21),
  412. },
  413. };
  414. static struct ov772x_camera_info ov7725_info = {
  415. .buswidth = SOCAM_DATAWIDTH_8,
  416. .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
  417. .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
  418. .link = {
  419. .bus_id = 0,
  420. .power = ov7725_power,
  421. .board_info = &ap325rxa_i2c_camera[0],
  422. .i2c_adapter_id = 0,
  423. .module_name = "ov772x",
  424. },
  425. };
  426. static struct platform_device ap325rxa_camera[] = {
  427. {
  428. .name = "soc-camera-pdrv",
  429. .id = 0,
  430. .dev = {
  431. .platform_data = &ov7725_info.link,
  432. },
  433. }, {
  434. .name = "soc-camera-pdrv",
  435. .id = 1,
  436. .dev = {
  437. .platform_data = &camera_info.link,
  438. },
  439. },
  440. };
  441. static struct platform_device *ap325rxa_devices[] __initdata = {
  442. &smsc9118_device,
  443. &ap325rxa_nor_flash_device,
  444. &lcdc_device,
  445. &ceu_device,
  446. &nand_flash_device,
  447. &sdhi0_cn3_device,
  448. &sdhi1_cn7_device,
  449. &ap325rxa_camera[0],
  450. &ap325rxa_camera[1],
  451. };
  452. extern char ap325rxa_sdram_enter_start;
  453. extern char ap325rxa_sdram_enter_end;
  454. extern char ap325rxa_sdram_leave_start;
  455. extern char ap325rxa_sdram_leave_end;
  456. static int __init ap325rxa_devices_setup(void)
  457. {
  458. /* register board specific self-refresh code */
  459. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
  460. &ap325rxa_sdram_enter_start,
  461. &ap325rxa_sdram_enter_end,
  462. &ap325rxa_sdram_leave_start,
  463. &ap325rxa_sdram_leave_end);
  464. /* LD3 and LD4 LEDs */
  465. gpio_request(GPIO_PTX5, NULL); /* RUN */
  466. gpio_direction_output(GPIO_PTX5, 1);
  467. gpio_export(GPIO_PTX5, 0);
  468. gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
  469. gpio_direction_output(GPIO_PTX4, 0);
  470. gpio_export(GPIO_PTX4, 0);
  471. /* SW1 input */
  472. gpio_request(GPIO_PTF7, NULL); /* MODE */
  473. gpio_direction_input(GPIO_PTF7);
  474. gpio_export(GPIO_PTF7, 0);
  475. /* LCDC */
  476. gpio_request(GPIO_FN_LCDD15, NULL);
  477. gpio_request(GPIO_FN_LCDD14, NULL);
  478. gpio_request(GPIO_FN_LCDD13, NULL);
  479. gpio_request(GPIO_FN_LCDD12, NULL);
  480. gpio_request(GPIO_FN_LCDD11, NULL);
  481. gpio_request(GPIO_FN_LCDD10, NULL);
  482. gpio_request(GPIO_FN_LCDD9, NULL);
  483. gpio_request(GPIO_FN_LCDD8, NULL);
  484. gpio_request(GPIO_FN_LCDD7, NULL);
  485. gpio_request(GPIO_FN_LCDD6, NULL);
  486. gpio_request(GPIO_FN_LCDD5, NULL);
  487. gpio_request(GPIO_FN_LCDD4, NULL);
  488. gpio_request(GPIO_FN_LCDD3, NULL);
  489. gpio_request(GPIO_FN_LCDD2, NULL);
  490. gpio_request(GPIO_FN_LCDD1, NULL);
  491. gpio_request(GPIO_FN_LCDD0, NULL);
  492. gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
  493. gpio_request(GPIO_FN_LCDDCK, NULL);
  494. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  495. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  496. gpio_request(GPIO_FN_LCDVSYN, NULL);
  497. gpio_request(GPIO_FN_LCDHSYN, NULL);
  498. gpio_request(GPIO_FN_LCDDISP, NULL);
  499. gpio_request(GPIO_FN_LCDDON, NULL);
  500. /* LCD backlight */
  501. gpio_request(GPIO_PTS3, NULL);
  502. gpio_direction_output(GPIO_PTS3, 1);
  503. /* CEU */
  504. gpio_request(GPIO_FN_VIO_CLK2, NULL);
  505. gpio_request(GPIO_FN_VIO_VD2, NULL);
  506. gpio_request(GPIO_FN_VIO_HD2, NULL);
  507. gpio_request(GPIO_FN_VIO_FLD, NULL);
  508. gpio_request(GPIO_FN_VIO_CKO, NULL);
  509. gpio_request(GPIO_FN_VIO_D15, NULL);
  510. gpio_request(GPIO_FN_VIO_D14, NULL);
  511. gpio_request(GPIO_FN_VIO_D13, NULL);
  512. gpio_request(GPIO_FN_VIO_D12, NULL);
  513. gpio_request(GPIO_FN_VIO_D11, NULL);
  514. gpio_request(GPIO_FN_VIO_D10, NULL);
  515. gpio_request(GPIO_FN_VIO_D9, NULL);
  516. gpio_request(GPIO_FN_VIO_D8, NULL);
  517. gpio_request(GPIO_PTZ7, NULL);
  518. gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
  519. gpio_request(GPIO_PTZ6, NULL);
  520. gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
  521. gpio_request(GPIO_PTZ5, NULL);
  522. gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
  523. gpio_request(GPIO_PTZ4, NULL);
  524. gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
  525. ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
  526. /* FLCTL */
  527. gpio_request(GPIO_FN_FCE, NULL);
  528. gpio_request(GPIO_FN_NAF7, NULL);
  529. gpio_request(GPIO_FN_NAF6, NULL);
  530. gpio_request(GPIO_FN_NAF5, NULL);
  531. gpio_request(GPIO_FN_NAF4, NULL);
  532. gpio_request(GPIO_FN_NAF3, NULL);
  533. gpio_request(GPIO_FN_NAF2, NULL);
  534. gpio_request(GPIO_FN_NAF1, NULL);
  535. gpio_request(GPIO_FN_NAF0, NULL);
  536. gpio_request(GPIO_FN_FCDE, NULL);
  537. gpio_request(GPIO_FN_FOE, NULL);
  538. gpio_request(GPIO_FN_FSC, NULL);
  539. gpio_request(GPIO_FN_FWE, NULL);
  540. gpio_request(GPIO_FN_FRB, NULL);
  541. ctrl_outw(0, PORT_HIZCRC);
  542. ctrl_outw(0xFFFF, PORT_DRVCRA);
  543. ctrl_outw(0xFFFF, PORT_DRVCRB);
  544. platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
  545. /* SDHI0 - CN3 - SD CARD */
  546. gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
  547. gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
  548. gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
  549. gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
  550. gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
  551. gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
  552. gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
  553. gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
  554. /* SDHI1 - CN7 - MICRO SD CARD */
  555. gpio_request(GPIO_FN_SDHI1CD, NULL);
  556. gpio_request(GPIO_FN_SDHI1D3, NULL);
  557. gpio_request(GPIO_FN_SDHI1D2, NULL);
  558. gpio_request(GPIO_FN_SDHI1D1, NULL);
  559. gpio_request(GPIO_FN_SDHI1D0, NULL);
  560. gpio_request(GPIO_FN_SDHI1CMD, NULL);
  561. gpio_request(GPIO_FN_SDHI1CLK, NULL);
  562. i2c_register_board_info(0, ap325rxa_i2c_devices,
  563. ARRAY_SIZE(ap325rxa_i2c_devices));
  564. return platform_add_devices(ap325rxa_devices,
  565. ARRAY_SIZE(ap325rxa_devices));
  566. }
  567. arch_initcall(ap325rxa_devices_setup);
  568. /* Return the board specific boot mode pin configuration */
  569. static int ap325rxa_mode_pins(void)
  570. {
  571. /* MD0=0, MD1=0, MD2=0: Clock Mode 0
  572. * MD3=0: 16-bit Area0 Bus Width
  573. * MD5=1: Little Endian
  574. * TSTMD=1, MD8=1: Test Mode Disabled
  575. */
  576. return MODE_PIN5 | MODE_PIN8;
  577. }
  578. static struct sh_machine_vector mv_ap325rxa __initmv = {
  579. .mv_name = "AP-325RXA",
  580. .mv_mode_pins = ap325rxa_mode_pins,
  581. };