ip0x.c 7.0 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2007 David Rowe
  4. * 2006 Intratrade Ltd.
  5. * Ivan Danov <idanov@gmail.com>
  6. * 2005 National ICT Australia (NICTA)
  7. * Aidan Williams <aidan@nicta.com.au>
  8. *
  9. * Licensed under the GPL-2 or later.
  10. */
  11. #include <linux/device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/partitions.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/spi/flash.h>
  17. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  18. #include <linux/usb/isp1362.h>
  19. #endif
  20. #include <asm/irq.h>
  21. #include <asm/bfin5xx_spi.h>
  22. /*
  23. * Name the Board for the /proc/cpuinfo
  24. */
  25. const char bfin_board_name[] = "IP04/IP08";
  26. /*
  27. * Driver needs to know address, irq and flag pin.
  28. */
  29. #if defined(CONFIG_BFIN532_IP0X)
  30. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  31. #include <linux/dm9000.h>
  32. static struct resource dm9000_resource1[] = {
  33. {
  34. .start = 0x20100000,
  35. .end = 0x20100000 + 1,
  36. .flags = IORESOURCE_MEM
  37. },{
  38. .start = 0x20100000 + 2,
  39. .end = 0x20100000 + 3,
  40. .flags = IORESOURCE_MEM
  41. },{
  42. .start = IRQ_PF15,
  43. .end = IRQ_PF15,
  44. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  45. }
  46. };
  47. static struct resource dm9000_resource2[] = {
  48. {
  49. .start = 0x20200000,
  50. .end = 0x20200000 + 1,
  51. .flags = IORESOURCE_MEM
  52. },{
  53. .start = 0x20200000 + 2,
  54. .end = 0x20200000 + 3,
  55. .flags = IORESOURCE_MEM
  56. },{
  57. .start = IRQ_PF14,
  58. .end = IRQ_PF14,
  59. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  60. }
  61. };
  62. /*
  63. * for the moment we limit ourselves to 16bit IO until some
  64. * better IO routines can be written and tested
  65. */
  66. static struct dm9000_plat_data dm9000_platdata1 = {
  67. .flags = DM9000_PLATF_16BITONLY,
  68. };
  69. static struct platform_device dm9000_device1 = {
  70. .name = "dm9000",
  71. .id = 0,
  72. .num_resources = ARRAY_SIZE(dm9000_resource1),
  73. .resource = dm9000_resource1,
  74. .dev = {
  75. .platform_data = &dm9000_platdata1,
  76. }
  77. };
  78. static struct dm9000_plat_data dm9000_platdata2 = {
  79. .flags = DM9000_PLATF_16BITONLY,
  80. };
  81. static struct platform_device dm9000_device2 = {
  82. .name = "dm9000",
  83. .id = 1,
  84. .num_resources = ARRAY_SIZE(dm9000_resource2),
  85. .resource = dm9000_resource2,
  86. .dev = {
  87. .platform_data = &dm9000_platdata2,
  88. }
  89. };
  90. #endif
  91. #endif
  92. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  93. /* all SPI peripherals info goes here */
  94. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  95. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  96. /*
  97. * CPOL (Clock Polarity)
  98. * 0 - Active high SCK
  99. * 1 - Active low SCK
  100. * CPHA (Clock Phase) Selects transfer format and operation mode
  101. * 0 - SCLK toggles from middle of the first data bit, slave select
  102. * pins controlled by hardware.
  103. * 1 - SCLK toggles from beginning of first data bit, slave select
  104. * pins controller by user software.
  105. * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
  106. * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
  107. * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
  108. */
  109. .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
  110. .enable_dma = 0, /* if 1 - block!!! */
  111. .bits_per_word = 8,
  112. };
  113. #endif
  114. /* Notice: for blackfin, the speed_hz is the value of register
  115. * SPI_BAUD, not the real baudrate */
  116. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  117. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  118. {
  119. .modalias = "mmc_spi",
  120. .max_speed_hz = 2,
  121. .bus_num = 1,
  122. .chip_select = 5,
  123. .controller_data = &mmc_spi_chip_info,
  124. },
  125. #endif
  126. };
  127. /* SPI controller data */
  128. static struct bfin5xx_spi_master spi_bfin_master_info = {
  129. .num_chipselect = 8,
  130. .enable_dma = 1, /* master has the ability to do dma transfer */
  131. };
  132. static struct platform_device spi_bfin_master_device = {
  133. .name = "bfin-spi-master",
  134. .id = 1, /* Bus number */
  135. .dev = {
  136. .platform_data = &spi_bfin_master_info, /* Passed to driver */
  137. },
  138. };
  139. #endif /* spi master and devices */
  140. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  141. static struct resource bfin_uart_resources[] = {
  142. {
  143. .start = 0xFFC00400,
  144. .end = 0xFFC004FF,
  145. .flags = IORESOURCE_MEM,
  146. },
  147. };
  148. static struct platform_device bfin_uart_device = {
  149. .name = "bfin-uart",
  150. .id = 1,
  151. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  152. .resource = bfin_uart_resources,
  153. };
  154. #endif
  155. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  156. #ifdef CONFIG_BFIN_SIR0
  157. static struct resource bfin_sir0_resources[] = {
  158. {
  159. .start = 0xFFC00400,
  160. .end = 0xFFC004FF,
  161. .flags = IORESOURCE_MEM,
  162. },
  163. {
  164. .start = IRQ_UART0_RX,
  165. .end = IRQ_UART0_RX+1,
  166. .flags = IORESOURCE_IRQ,
  167. },
  168. {
  169. .start = CH_UART0_RX,
  170. .end = CH_UART0_RX+1,
  171. .flags = IORESOURCE_DMA,
  172. },
  173. };
  174. static struct platform_device bfin_sir0_device = {
  175. .name = "bfin_sir",
  176. .id = 0,
  177. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  178. .resource = bfin_sir0_resources,
  179. };
  180. #endif
  181. #endif
  182. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  183. static struct resource isp1362_hcd_resources[] = {
  184. {
  185. .start = 0x20300000,
  186. .end = 0x20300000 + 1,
  187. .flags = IORESOURCE_MEM,
  188. },{
  189. .start = 0x20300000 + 2,
  190. .end = 0x20300000 + 3,
  191. .flags = IORESOURCE_MEM,
  192. },{
  193. .start = IRQ_PF11,
  194. .end = IRQ_PF11,
  195. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  196. },
  197. };
  198. static struct isp1362_platform_data isp1362_priv = {
  199. .sel15Kres = 1,
  200. .clknotstop = 0,
  201. .oc_enable = 0, /* external OC */
  202. .int_act_high = 0,
  203. .int_edge_triggered = 0,
  204. .remote_wakeup_connected = 0,
  205. .no_power_switching = 1,
  206. .power_switching_mode = 0,
  207. };
  208. static struct platform_device isp1362_hcd_device = {
  209. .name = "isp1362-hcd",
  210. .id = 0,
  211. .dev = {
  212. .platform_data = &isp1362_priv,
  213. },
  214. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  215. .resource = isp1362_hcd_resources,
  216. };
  217. #endif
  218. static struct platform_device *ip0x_devices[] __initdata = {
  219. #if defined(CONFIG_BFIN532_IP0X)
  220. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  221. &dm9000_device1,
  222. &dm9000_device2,
  223. #endif
  224. #endif
  225. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  226. &spi_bfin_master_device,
  227. #endif
  228. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  229. &bfin_uart_device,
  230. #endif
  231. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  232. #ifdef CONFIG_BFIN_SIR0
  233. &bfin_sir0_device,
  234. #endif
  235. #endif
  236. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  237. &isp1362_hcd_device,
  238. #endif
  239. };
  240. static int __init ip0x_init(void)
  241. {
  242. int i;
  243. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  244. platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
  245. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  246. for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
  247. int j = 1 << bfin_spi_board_info[i].chip_select;
  248. /* set spi cs to 1 */
  249. bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
  250. bfin_write_FIO_FLAG_S(j);
  251. }
  252. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  253. #endif
  254. return 0;
  255. }
  256. arch_initcall(ip0x_init);