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arch
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blackfin
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mach-bf518
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include
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mach
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blackfin.h

blackfin.h 2.0 KB
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  1. /*
    2. 

  2.  * Copyright 2008-2009 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the GPL-2 or later
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _MACH_BLACKFIN_H_
    8. 

  8. #define _MACH_BLACKFIN_H_
    9. 

  9. 

  10. #include "bf518.h"
    11. 

  11. #include "defBF512.h"
    12. 

  12. #include "anomaly.h"
    13. 

  13. 

  14. #if defined(CONFIG_BF518)
    15. 

  15. #include "defBF518.h"
    16. 

  16. #endif
    17. 

  17. 

  18. #if defined(CONFIG_BF516)
    19. 

  19. #include "defBF516.h"
    20. 

  20. #endif
    21. 

  21. 

  22. #if defined(CONFIG_BF514)
    23. 

  23. #include "defBF514.h"
    24. 

  24. #endif
    25. 

  25. 

  26. #if defined(CONFIG_BF512)
    27. 

  27. #include "defBF512.h"
    28. 

  28. #endif
    29. 

  29. 

  30. #if !defined(__ASSEMBLY__)
    31. 

  31. #include "cdefBF512.h"
    32. 

  32. 

  33. #if defined(CONFIG_BF518)
    34. 

  34. #include "cdefBF518.h"
    35. 

  35. #endif
    36. 

  36. 

  37. #if defined(CONFIG_BF516)
    38. 

  38. #include "cdefBF516.h"
    39. 

  39. #endif
    40. 

  40. 

  41. #if defined(CONFIG_BF514)
    42. 

  42. #include "cdefBF514.h"
    43. 

  43. #endif
    44. 

  44. #endif
    45. 

  45. 

  46. #define BFIN_UART_NR_PORTS	2
    47. 

  47. 

  48. #define OFFSET_THR              0x00	/* Transmit Holding register            */
    49. 

  49. #define OFFSET_RBR              0x00	/* Receive Buffer register              */
    50. 

  50. #define OFFSET_DLL              0x00	/* Divisor Latch (Low-Byte)             */
    51. 

  51. #define OFFSET_IER              0x04	/* Interrupt Enable Register            */
    52. 

  52. #define OFFSET_DLH              0x04	/* Divisor Latch (High-Byte)            */
    53. 

  53. #define OFFSET_IIR              0x08	/* Interrupt Identification Register    */
    54. 

  54. #define OFFSET_LCR              0x0C	/* Line Control Register                */
    55. 

  55. #define OFFSET_MCR              0x10	/* Modem Control Register               */
    56. 

  56. #define OFFSET_LSR              0x14	/* Line Status Register                 */
    57. 

  57. #define OFFSET_MSR              0x18	/* Modem Status Register                */
    58. 

  58. #define OFFSET_SCR              0x1C	/* SCR Scratch Register                 */
    59. 

  59. #define OFFSET_GCTL             0x24	/* Global Control Register              */
    60. 

  60. 

  61. /* PLL_DIV Masks													*/
    62. 

  62. #define CCLK_DIV1 CSEL_DIV1	/*          CCLK = VCO / 1                                  */
    63. 

  63. #define CCLK_DIV2 CSEL_DIV2	/*          CCLK = VCO / 2                                  */
    64. 

  64. #define CCLK_DIV4 CSEL_DIV4	/*          CCLK = VCO / 4                                  */
    65. 

  65. #define CCLK_DIV8 CSEL_DIV8	/*          CCLK = VCO / 8                                  */
    66. 

  66. 

  67. #endif
    68.