generic.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465
  1. /*
  2. * linux/arch/arm/mach-sa1100/generic.c
  3. *
  4. * Author: Nicolas Pitre
  5. *
  6. * Code common to all SA11x0 machines.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/cpufreq.h>
  18. #include <linux/ioport.h>
  19. #include <linux/sched.h> /* just for sched_clock() - funny that */
  20. #include <linux/platform_device.h>
  21. #include <linux/cnt32_to_63.h>
  22. #include <asm/div64.h>
  23. #include <mach/hardware.h>
  24. #include <asm/system.h>
  25. #include <asm/pgtable.h>
  26. #include <asm/mach/map.h>
  27. #include <asm/mach/flash.h>
  28. #include <asm/irq.h>
  29. #include <asm/gpio.h>
  30. #include "generic.h"
  31. unsigned int reset_status;
  32. EXPORT_SYMBOL(reset_status);
  33. #define NR_FREQS 16
  34. /*
  35. * This table is setup for a 3.6864MHz Crystal.
  36. */
  37. static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
  38. 590, /* 59.0 MHz */
  39. 737, /* 73.7 MHz */
  40. 885, /* 88.5 MHz */
  41. 1032, /* 103.2 MHz */
  42. 1180, /* 118.0 MHz */
  43. 1327, /* 132.7 MHz */
  44. 1475, /* 147.5 MHz */
  45. 1622, /* 162.2 MHz */
  46. 1769, /* 176.9 MHz */
  47. 1917, /* 191.7 MHz */
  48. 2064, /* 206.4 MHz */
  49. 2212, /* 221.2 MHz */
  50. 2359, /* 235.9 MHz */
  51. 2507, /* 250.7 MHz */
  52. 2654, /* 265.4 MHz */
  53. 2802 /* 280.2 MHz */
  54. };
  55. #if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110)
  56. /* rounds up(!) */
  57. unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
  58. {
  59. int i;
  60. khz /= 100;
  61. for (i = 0; i < NR_FREQS; i++)
  62. if (cclk_frequency_100khz[i] >= khz)
  63. break;
  64. return i;
  65. }
  66. unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
  67. {
  68. unsigned int freq = 0;
  69. if (idx < NR_FREQS)
  70. freq = cclk_frequency_100khz[idx] * 100;
  71. return freq;
  72. }
  73. /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
  74. * this platform, anyway.
  75. */
  76. int sa11x0_verify_speed(struct cpufreq_policy *policy)
  77. {
  78. unsigned int tmp;
  79. if (policy->cpu)
  80. return -EINVAL;
  81. cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  82. /* make sure that at least one frequency is within the policy */
  83. tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
  84. if (tmp > policy->max)
  85. policy->max = tmp;
  86. cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  87. return 0;
  88. }
  89. unsigned int sa11x0_getspeed(unsigned int cpu)
  90. {
  91. if (cpu)
  92. return 0;
  93. return cclk_frequency_100khz[PPCR & 0xf] * 100;
  94. }
  95. #else
  96. /*
  97. * We still need to provide this so building without cpufreq works.
  98. */
  99. unsigned int cpufreq_get(unsigned int cpu)
  100. {
  101. return cclk_frequency_100khz[PPCR & 0xf] * 100;
  102. }
  103. EXPORT_SYMBOL(cpufreq_get);
  104. #endif
  105. /*
  106. * This is the SA11x0 sched_clock implementation. This has
  107. * a resolution of 271ns, and a maximum value of 32025597s (370 days).
  108. *
  109. * The return value is guaranteed to be monotonic in that range as
  110. * long as there is always less than 582 seconds between successive
  111. * calls to this function.
  112. *
  113. * ( * 1E9 / 3686400 => * 78125 / 288)
  114. */
  115. unsigned long long sched_clock(void)
  116. {
  117. unsigned long long v = cnt32_to_63(OSCR);
  118. /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
  119. v *= 78125<<1;
  120. do_div(v, 288<<1);
  121. return v;
  122. }
  123. /*
  124. * Default power-off for SA1100
  125. */
  126. static void sa1100_power_off(void)
  127. {
  128. mdelay(100);
  129. local_irq_disable();
  130. /* disable internal oscillator, float CS lines */
  131. PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
  132. /* enable wake-up on GPIO0 (Assabet...) */
  133. PWER = GFER = GRER = 1;
  134. /*
  135. * set scratchpad to zero, just in case it is used as a
  136. * restart address by the bootloader.
  137. */
  138. PSPR = 0;
  139. /* enter sleep mode */
  140. PMCR = PMCR_SF;
  141. }
  142. static void sa11x0_register_device(struct platform_device *dev, void *data)
  143. {
  144. int err;
  145. dev->dev.platform_data = data;
  146. err = platform_device_register(dev);
  147. if (err)
  148. printk(KERN_ERR "Unable to register device %s: %d\n",
  149. dev->name, err);
  150. }
  151. static struct resource sa11x0udc_resources[] = {
  152. [0] = {
  153. .start = 0x80000000,
  154. .end = 0x8000ffff,
  155. .flags = IORESOURCE_MEM,
  156. },
  157. };
  158. static u64 sa11x0udc_dma_mask = 0xffffffffUL;
  159. static struct platform_device sa11x0udc_device = {
  160. .name = "sa11x0-udc",
  161. .id = -1,
  162. .dev = {
  163. .dma_mask = &sa11x0udc_dma_mask,
  164. .coherent_dma_mask = 0xffffffff,
  165. },
  166. .num_resources = ARRAY_SIZE(sa11x0udc_resources),
  167. .resource = sa11x0udc_resources,
  168. };
  169. static struct resource sa11x0uart1_resources[] = {
  170. [0] = {
  171. .start = 0x80010000,
  172. .end = 0x8001ffff,
  173. .flags = IORESOURCE_MEM,
  174. },
  175. };
  176. static struct platform_device sa11x0uart1_device = {
  177. .name = "sa11x0-uart",
  178. .id = 1,
  179. .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
  180. .resource = sa11x0uart1_resources,
  181. };
  182. static struct resource sa11x0uart3_resources[] = {
  183. [0] = {
  184. .start = 0x80050000,
  185. .end = 0x8005ffff,
  186. .flags = IORESOURCE_MEM,
  187. },
  188. };
  189. static struct platform_device sa11x0uart3_device = {
  190. .name = "sa11x0-uart",
  191. .id = 3,
  192. .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
  193. .resource = sa11x0uart3_resources,
  194. };
  195. static struct resource sa11x0mcp_resources[] = {
  196. [0] = {
  197. .start = 0x80060000,
  198. .end = 0x8006ffff,
  199. .flags = IORESOURCE_MEM,
  200. },
  201. };
  202. static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
  203. static struct platform_device sa11x0mcp_device = {
  204. .name = "sa11x0-mcp",
  205. .id = -1,
  206. .dev = {
  207. .dma_mask = &sa11x0mcp_dma_mask,
  208. .coherent_dma_mask = 0xffffffff,
  209. },
  210. .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
  211. .resource = sa11x0mcp_resources,
  212. };
  213. void sa11x0_register_mcp(struct mcp_plat_data *data)
  214. {
  215. sa11x0_register_device(&sa11x0mcp_device, data);
  216. }
  217. static struct resource sa11x0ssp_resources[] = {
  218. [0] = {
  219. .start = 0x80070000,
  220. .end = 0x8007ffff,
  221. .flags = IORESOURCE_MEM,
  222. },
  223. };
  224. static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
  225. static struct platform_device sa11x0ssp_device = {
  226. .name = "sa11x0-ssp",
  227. .id = -1,
  228. .dev = {
  229. .dma_mask = &sa11x0ssp_dma_mask,
  230. .coherent_dma_mask = 0xffffffff,
  231. },
  232. .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
  233. .resource = sa11x0ssp_resources,
  234. };
  235. static struct resource sa11x0fb_resources[] = {
  236. [0] = {
  237. .start = 0xb0100000,
  238. .end = 0xb010ffff,
  239. .flags = IORESOURCE_MEM,
  240. },
  241. [1] = {
  242. .start = IRQ_LCD,
  243. .end = IRQ_LCD,
  244. .flags = IORESOURCE_IRQ,
  245. },
  246. };
  247. static struct platform_device sa11x0fb_device = {
  248. .name = "sa11x0-fb",
  249. .id = -1,
  250. .dev = {
  251. .coherent_dma_mask = 0xffffffff,
  252. },
  253. .num_resources = ARRAY_SIZE(sa11x0fb_resources),
  254. .resource = sa11x0fb_resources,
  255. };
  256. static struct platform_device sa11x0pcmcia_device = {
  257. .name = "sa11x0-pcmcia",
  258. .id = -1,
  259. };
  260. static struct platform_device sa11x0mtd_device = {
  261. .name = "sa1100-mtd",
  262. .id = -1,
  263. };
  264. void sa11x0_register_mtd(struct flash_platform_data *flash,
  265. struct resource *res, int nr)
  266. {
  267. flash->name = "sa1100";
  268. sa11x0mtd_device.resource = res;
  269. sa11x0mtd_device.num_resources = nr;
  270. sa11x0_register_device(&sa11x0mtd_device, flash);
  271. }
  272. static struct resource sa11x0ir_resources[] = {
  273. {
  274. .start = __PREG(Ser2UTCR0),
  275. .end = __PREG(Ser2UTCR0) + 0x24 - 1,
  276. .flags = IORESOURCE_MEM,
  277. }, {
  278. .start = __PREG(Ser2HSCR0),
  279. .end = __PREG(Ser2HSCR0) + 0x1c - 1,
  280. .flags = IORESOURCE_MEM,
  281. }, {
  282. .start = __PREG(Ser2HSCR2),
  283. .end = __PREG(Ser2HSCR2) + 0x04 - 1,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = IRQ_Ser2ICP,
  287. .end = IRQ_Ser2ICP,
  288. .flags = IORESOURCE_IRQ,
  289. }
  290. };
  291. static struct platform_device sa11x0ir_device = {
  292. .name = "sa11x0-ir",
  293. .id = -1,
  294. .num_resources = ARRAY_SIZE(sa11x0ir_resources),
  295. .resource = sa11x0ir_resources,
  296. };
  297. void sa11x0_register_irda(struct irda_platform_data *irda)
  298. {
  299. sa11x0_register_device(&sa11x0ir_device, irda);
  300. }
  301. static struct platform_device sa11x0rtc_device = {
  302. .name = "sa1100-rtc",
  303. .id = -1,
  304. };
  305. static struct platform_device *sa11x0_devices[] __initdata = {
  306. &sa11x0udc_device,
  307. &sa11x0uart1_device,
  308. &sa11x0uart3_device,
  309. &sa11x0ssp_device,
  310. &sa11x0pcmcia_device,
  311. &sa11x0fb_device,
  312. &sa11x0rtc_device,
  313. };
  314. static int __init sa1100_init(void)
  315. {
  316. pm_power_off = sa1100_power_off;
  317. return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
  318. }
  319. arch_initcall(sa1100_init);
  320. void (*sa1100fb_backlight_power)(int on);
  321. void (*sa1100fb_lcd_power)(int on);
  322. EXPORT_SYMBOL(sa1100fb_backlight_power);
  323. EXPORT_SYMBOL(sa1100fb_lcd_power);
  324. /*
  325. * Common I/O mapping:
  326. *
  327. * Typically, static virtual address mappings are as follow:
  328. *
  329. * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
  330. * 0xf4000000-0xf4ffffff: SA-1111
  331. * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
  332. * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
  333. * 0xffff0000-0xffff0fff: SA1100 exception vectors
  334. * 0xffff2000-0xffff2fff: Minicache copy_user_page area
  335. *
  336. * Below 0xe8000000 is reserved for vm allocation.
  337. *
  338. * The machine specific code must provide the extra mapping beside the
  339. * default mapping provided here.
  340. */
  341. static struct map_desc standard_io_desc[] __initdata = {
  342. { /* PCM */
  343. .virtual = 0xf8000000,
  344. .pfn = __phys_to_pfn(0x80000000),
  345. .length = 0x00100000,
  346. .type = MT_DEVICE
  347. }, { /* SCM */
  348. .virtual = 0xfa000000,
  349. .pfn = __phys_to_pfn(0x90000000),
  350. .length = 0x00100000,
  351. .type = MT_DEVICE
  352. }, { /* MER */
  353. .virtual = 0xfc000000,
  354. .pfn = __phys_to_pfn(0xa0000000),
  355. .length = 0x00100000,
  356. .type = MT_DEVICE
  357. }, { /* LCD + DMA */
  358. .virtual = 0xfe000000,
  359. .pfn = __phys_to_pfn(0xb0000000),
  360. .length = 0x00200000,
  361. .type = MT_DEVICE
  362. },
  363. };
  364. void __init sa1100_map_io(void)
  365. {
  366. iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
  367. }
  368. /*
  369. * Disable the memory bus request/grant signals on the SA1110 to
  370. * ensure that we don't receive spurious memory requests. We set
  371. * the MBGNT signal false to ensure the SA1111 doesn't own the
  372. * SDRAM bus.
  373. */
  374. void __init sa1110_mb_disable(void)
  375. {
  376. unsigned long flags;
  377. local_irq_save(flags);
  378. PGSR &= ~GPIO_MBGNT;
  379. GPCR = GPIO_MBGNT;
  380. GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
  381. GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
  382. local_irq_restore(flags);
  383. }
  384. /*
  385. * If the system is going to use the SA-1111 DMA engines, set up
  386. * the memory bus request/grant pins.
  387. */
  388. void __devinit sa1110_mb_enable(void)
  389. {
  390. unsigned long flags;
  391. local_irq_save(flags);
  392. PGSR &= ~GPIO_MBGNT;
  393. GPCR = GPIO_MBGNT;
  394. GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
  395. GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
  396. TUCR |= TUCR_MR;
  397. local_irq_restore(flags);
  398. }