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linux-vybrid_pu...
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arch
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arm
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mach-ep93xx
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soc.h

soc.h 1.9 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-ep93xx/soc.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
    5. 

  5.  * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License as published by
    9. 

  9.  * the Free Software Foundation; either version 2 of the License, or (at
    10. 

  10.  * your option) any later version.
    11. 

  11.  */
    12. 

  12. 

  13. #ifndef _EP93XX_SOC_H
    14. 

  14. #define _EP93XX_SOC_H
    15. 

  15. 

  16. /*
    17. 

  17.  * EP93xx Physical Memory Map:
    18. 

  18.  *
    19. 

  19.  * The ASDO pin is sampled at system reset to select a synchronous or
    20. 

  20.  * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
    21. 

  21.  * the synchronous boot mode is selected.  When ASDO is "0" (i.e
    22. 

  22.  * pulled-down) the asynchronous boot mode is selected.
    23. 

  23.  *
    24. 

  24.  * In synchronous boot mode nSDCE3 is decoded starting at physical address
    25. 

  25.  * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
    26. 

  26.  * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
    27. 

  27.  * decoded at 0xf0000000.
    28. 

  28.  *
    29. 

  29.  * There is known errata for the EP93xx dealing with External Memory
    30. 

  30.  * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
    31. 

  31.  * Guidelines" for more information.  This document can be found at:
    32. 

  32.  *
    33. 

  33.  *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
    34. 

  34.  */
    35. 

  35. 

  36. #define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
    37. 

  37. #define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
    38. 

  38. #define EP93XX_CS1_PHYS_BASE		0x10000000
    39. 

  39. #define EP93XX_CS2_PHYS_BASE		0x20000000
    40. 

  40. #define EP93XX_CS3_PHYS_BASE		0x30000000
    41. 

  41. #define EP93XX_PCMCIA_PHYS_BASE		0x40000000
    42. 

  42. #define EP93XX_CS6_PHYS_BASE		0x60000000
    43. 

  43. #define EP93XX_CS7_PHYS_BASE		0x70000000
    44. 

  44. #define EP93XX_SDCE0_PHYS_BASE		0xc0000000
    45. 

  45. #define EP93XX_SDCE1_PHYS_BASE		0xd0000000
    46. 

  46. #define EP93XX_SDCE2_PHYS_BASE		0xe0000000
    47. 

  47. #define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
    48. 

  48. #define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */
    49. 

  49. 

  50. #endif /* _EP93XX_SOC_H */
    51.