tifm_sd.c 26 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.7"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
  34. #define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
  35. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  46. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  47. #define TIFM_MMCSD_RSP_R0 0x0000
  48. #define TIFM_MMCSD_RSP_R1 0x0100
  49. #define TIFM_MMCSD_RSP_R2 0x0200
  50. #define TIFM_MMCSD_RSP_R3 0x0300
  51. #define TIFM_MMCSD_RSP_R4 0x0400
  52. #define TIFM_MMCSD_RSP_R5 0x0500
  53. #define TIFM_MMCSD_RSP_R6 0x0600
  54. #define TIFM_MMCSD_RSP_BUSY 0x0800
  55. #define TIFM_MMCSD_CMD_BC 0x0000
  56. #define TIFM_MMCSD_CMD_BCR 0x1000
  57. #define TIFM_MMCSD_CMD_AC 0x2000
  58. #define TIFM_MMCSD_CMD_ADTC 0x3000
  59. typedef enum {
  60. IDLE = 0,
  61. CMD, /* main command ended */
  62. BRS, /* block transfer finished */
  63. SCMD, /* stop command ended */
  64. CARD, /* card left busy state */
  65. FIFO, /* FIFO operation completed (uncertain) */
  66. READY
  67. } card_state_t;
  68. enum {
  69. FIFO_RDY = 0x0001, /* hardware dependent value */
  70. HOST_REG = 0x0002,
  71. EJECT = 0x0004,
  72. EJECT_DONE = 0x0008,
  73. CARD_BUSY = 0x0010,
  74. OPENDRAIN = 0x0040, /* hardware dependent value */
  75. CARD_EVENT = 0x0100, /* hardware dependent value */
  76. CARD_RO = 0x0200, /* hardware dependent value */
  77. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  78. struct tifm_sd {
  79. struct tifm_dev *dev;
  80. unsigned int flags;
  81. card_state_t state;
  82. unsigned int clk_freq;
  83. unsigned int clk_div;
  84. unsigned long timeout_jiffies; // software timeout - 2 sec
  85. struct mmc_request *req;
  86. struct work_struct cmd_handler;
  87. struct delayed_work abort_handler;
  88. wait_queue_head_t can_eject;
  89. size_t written_blocks;
  90. size_t buffer_size;
  91. size_t buffer_pos;
  92. };
  93. static char* tifm_sd_kmap_atomic(struct mmc_data *data)
  94. {
  95. return kmap_atomic(data->sg->page, KM_BIO_SRC_IRQ) + data->sg->offset;
  96. }
  97. static void tifm_sd_kunmap_atomic(char *buffer, struct mmc_data *data)
  98. {
  99. kunmap_atomic(buffer - data->sg->offset, KM_BIO_SRC_IRQ);
  100. }
  101. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  102. unsigned int host_status)
  103. {
  104. struct mmc_command *cmd = host->req->cmd;
  105. unsigned int t_val = 0, cnt = 0;
  106. char *buffer;
  107. if (host_status & TIFM_MMCSD_BRS) {
  108. /* in non-dma rx mode BRS fires when fifo is still not empty */
  109. if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
  110. buffer = tifm_sd_kmap_atomic(host->req->data);
  111. while (host->buffer_size > host->buffer_pos) {
  112. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  113. buffer[host->buffer_pos++] = t_val & 0xff;
  114. buffer[host->buffer_pos++] =
  115. (t_val >> 8) & 0xff;
  116. }
  117. tifm_sd_kunmap_atomic(buffer, host->req->data);
  118. }
  119. return 1;
  120. } else if (no_dma) {
  121. buffer = tifm_sd_kmap_atomic(host->req->data);
  122. if ((cmd->data->flags & MMC_DATA_READ) &&
  123. (host_status & TIFM_MMCSD_AF)) {
  124. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  125. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  126. if (host->buffer_size > host->buffer_pos) {
  127. buffer[host->buffer_pos++] =
  128. t_val & 0xff;
  129. buffer[host->buffer_pos++] =
  130. (t_val >> 8) & 0xff;
  131. }
  132. }
  133. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  134. && (host_status & TIFM_MMCSD_AE)) {
  135. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  136. if (host->buffer_size > host->buffer_pos) {
  137. t_val = buffer[host->buffer_pos++]
  138. & 0x00ff;
  139. t_val |= ((buffer[host->buffer_pos++])
  140. << 8) & 0xff00;
  141. writel(t_val,
  142. sock->addr + SOCK_MMCSD_DATA);
  143. }
  144. }
  145. }
  146. tifm_sd_kunmap_atomic(buffer, host->req->data);
  147. }
  148. return 0;
  149. }
  150. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  151. {
  152. unsigned int rc = 0;
  153. switch (mmc_resp_type(cmd)) {
  154. case MMC_RSP_NONE:
  155. rc |= TIFM_MMCSD_RSP_R0;
  156. break;
  157. case MMC_RSP_R1B:
  158. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  159. case MMC_RSP_R1:
  160. rc |= TIFM_MMCSD_RSP_R1;
  161. break;
  162. case MMC_RSP_R2:
  163. rc |= TIFM_MMCSD_RSP_R2;
  164. break;
  165. case MMC_RSP_R3:
  166. rc |= TIFM_MMCSD_RSP_R3;
  167. break;
  168. default:
  169. BUG();
  170. }
  171. switch (mmc_cmd_type(cmd)) {
  172. case MMC_CMD_BC:
  173. rc |= TIFM_MMCSD_CMD_BC;
  174. break;
  175. case MMC_CMD_BCR:
  176. rc |= TIFM_MMCSD_CMD_BCR;
  177. break;
  178. case MMC_CMD_AC:
  179. rc |= TIFM_MMCSD_CMD_AC;
  180. break;
  181. case MMC_CMD_ADTC:
  182. rc |= TIFM_MMCSD_CMD_ADTC;
  183. break;
  184. default:
  185. BUG();
  186. }
  187. return rc;
  188. }
  189. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  190. {
  191. struct tifm_dev *sock = host->dev;
  192. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  193. (host->flags & OPENDRAIN);
  194. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  195. cmd_mask |= TIFM_MMCSD_READ;
  196. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  197. cmd->opcode, cmd->arg, cmd_mask);
  198. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  199. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  200. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  201. }
  202. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  203. {
  204. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  205. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  206. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  207. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  208. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  209. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  210. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  211. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  212. }
  213. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  214. unsigned int host_status)
  215. {
  216. struct mmc_command *cmd = host->req->cmd;
  217. change_state:
  218. switch (host->state) {
  219. case IDLE:
  220. return;
  221. case CMD:
  222. if (host_status & TIFM_MMCSD_EOC) {
  223. tifm_sd_fetch_resp(cmd, sock);
  224. if (cmd->data) {
  225. host->state = BRS;
  226. } else {
  227. host->state = READY;
  228. }
  229. goto change_state;
  230. }
  231. break;
  232. case BRS:
  233. if (tifm_sd_transfer_data(sock, host, host_status)) {
  234. if (cmd->data->flags & MMC_DATA_WRITE) {
  235. host->state = CARD;
  236. } else {
  237. if (no_dma) {
  238. if (host->req->stop) {
  239. tifm_sd_exec(host, host->req->stop);
  240. host->state = SCMD;
  241. } else {
  242. host->state = READY;
  243. }
  244. } else {
  245. host->state = FIFO;
  246. }
  247. }
  248. goto change_state;
  249. }
  250. break;
  251. case SCMD:
  252. if (host_status & TIFM_MMCSD_EOC) {
  253. tifm_sd_fetch_resp(host->req->stop, sock);
  254. host->state = READY;
  255. goto change_state;
  256. }
  257. break;
  258. case CARD:
  259. dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
  260. host->written_blocks);
  261. if (!(host->flags & CARD_BUSY)
  262. && (host->written_blocks == cmd->data->blocks)) {
  263. if (no_dma) {
  264. if (host->req->stop) {
  265. tifm_sd_exec(host, host->req->stop);
  266. host->state = SCMD;
  267. } else {
  268. host->state = READY;
  269. }
  270. } else {
  271. host->state = FIFO;
  272. }
  273. goto change_state;
  274. }
  275. break;
  276. case FIFO:
  277. if (host->flags & FIFO_RDY) {
  278. host->flags &= ~FIFO_RDY;
  279. if (host->req->stop) {
  280. tifm_sd_exec(host, host->req->stop);
  281. host->state = SCMD;
  282. } else {
  283. host->state = READY;
  284. }
  285. goto change_state;
  286. }
  287. break;
  288. case READY:
  289. queue_work(sock->wq, &host->cmd_handler);
  290. return;
  291. }
  292. queue_delayed_work(sock->wq, &host->abort_handler,
  293. host->timeout_jiffies);
  294. }
  295. /* Called from interrupt handler */
  296. static unsigned int tifm_sd_signal_irq(struct tifm_dev *sock,
  297. unsigned int sock_irq_status)
  298. {
  299. struct tifm_sd *host;
  300. unsigned int host_status = 0, fifo_status = 0;
  301. int error_code = 0;
  302. spin_lock(&sock->lock);
  303. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  304. cancel_delayed_work(&host->abort_handler);
  305. if (sock_irq_status & FIFO_EVENT) {
  306. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  307. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  308. host->flags |= fifo_status & FIFO_RDY;
  309. }
  310. if (sock_irq_status & CARD_EVENT) {
  311. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  312. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  313. if (!(host->flags & HOST_REG))
  314. queue_work(sock->wq, &host->cmd_handler);
  315. if (!host->req)
  316. goto done;
  317. if (host_status & TIFM_MMCSD_ERRMASK) {
  318. if (host_status & TIFM_MMCSD_CERR)
  319. error_code = MMC_ERR_FAILED;
  320. else if (host_status &
  321. (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  322. error_code = MMC_ERR_TIMEOUT;
  323. else if (host_status &
  324. (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  325. error_code = MMC_ERR_BADCRC;
  326. writel(TIFM_FIFO_INT_SETALL,
  327. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  328. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  329. if (host->req->stop) {
  330. if (host->state == SCMD) {
  331. host->req->stop->error = error_code;
  332. } else if (host->state == BRS
  333. || host->state == CARD
  334. || host->state == FIFO) {
  335. host->req->cmd->error = error_code;
  336. tifm_sd_exec(host, host->req->stop);
  337. queue_delayed_work(sock->wq,
  338. &host->abort_handler,
  339. host->timeout_jiffies);
  340. host->state = SCMD;
  341. goto done;
  342. } else {
  343. host->req->cmd->error = error_code;
  344. }
  345. } else {
  346. host->req->cmd->error = error_code;
  347. }
  348. host->state = READY;
  349. }
  350. if (host_status & TIFM_MMCSD_CB)
  351. host->flags |= CARD_BUSY;
  352. if ((host_status & TIFM_MMCSD_EOFB) &&
  353. (host->flags & CARD_BUSY)) {
  354. host->written_blocks++;
  355. host->flags &= ~CARD_BUSY;
  356. }
  357. }
  358. if (host->req)
  359. tifm_sd_process_cmd(sock, host, host_status);
  360. done:
  361. dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
  362. host_status, fifo_status);
  363. spin_unlock(&sock->lock);
  364. return sock_irq_status;
  365. }
  366. static void tifm_sd_prepare_data(struct tifm_sd *card, struct mmc_command *cmd)
  367. {
  368. struct tifm_dev *sock = card->dev;
  369. unsigned int dest_cnt;
  370. /* DMA style IO */
  371. writel(TIFM_FIFO_INT_SETALL,
  372. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  373. writel(ilog2(cmd->data->blksz) - 2,
  374. sock->addr + SOCK_FIFO_PAGE_SIZE);
  375. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  376. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  377. dest_cnt = (cmd->data->blocks) << 8;
  378. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  379. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  380. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  381. if (cmd->data->flags & MMC_DATA_WRITE) {
  382. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  383. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  384. sock->addr + SOCK_DMA_CONTROL);
  385. } else {
  386. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  387. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  388. }
  389. }
  390. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  391. struct mmc_data *data)
  392. {
  393. struct tifm_dev *sock = host->dev;
  394. unsigned int data_timeout = data->timeout_clks;
  395. if (fixed_timeout)
  396. return;
  397. data_timeout += data->timeout_ns /
  398. ((1000000000 / host->clk_freq) * host->clk_div);
  399. data_timeout *= 10; // call it fudge factor for now
  400. if (data_timeout < 0xffff) {
  401. writel((~TIFM_MMCSD_DPE) &
  402. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  403. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  404. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  405. } else {
  406. writel(TIFM_MMCSD_DPE |
  407. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  408. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  409. data_timeout = (data_timeout >> 10) + 1;
  410. if(data_timeout > 0xffff)
  411. data_timeout = 0; /* set to unlimited */
  412. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  413. }
  414. }
  415. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  416. {
  417. struct tifm_sd *host = mmc_priv(mmc);
  418. struct tifm_dev *sock = host->dev;
  419. unsigned long flags;
  420. int sg_count = 0;
  421. struct mmc_data *r_data = mrq->cmd->data;
  422. spin_lock_irqsave(&sock->lock, flags);
  423. if (host->flags & EJECT) {
  424. spin_unlock_irqrestore(&sock->lock, flags);
  425. goto err_out;
  426. }
  427. if (host->req) {
  428. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  429. spin_unlock_irqrestore(&sock->lock, flags);
  430. goto err_out;
  431. }
  432. if (r_data) {
  433. tifm_sd_set_data_timeout(host, r_data);
  434. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  435. mrq->cmd->flags & MMC_DATA_WRITE
  436. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  437. if (sg_count != 1) {
  438. printk(KERN_ERR DRIVER_NAME
  439. ": scatterlist map failed\n");
  440. spin_unlock_irqrestore(&sock->lock, flags);
  441. goto err_out;
  442. }
  443. host->written_blocks = 0;
  444. host->flags &= ~CARD_BUSY;
  445. tifm_sd_prepare_data(host, mrq->cmd);
  446. }
  447. host->req = mrq;
  448. host->state = CMD;
  449. queue_delayed_work(sock->wq, &host->abort_handler,
  450. host->timeout_jiffies);
  451. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  452. sock->addr + SOCK_CONTROL);
  453. tifm_sd_exec(host, mrq->cmd);
  454. spin_unlock_irqrestore(&sock->lock, flags);
  455. return;
  456. err_out:
  457. if (sg_count > 0)
  458. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  459. (r_data->flags & MMC_DATA_WRITE)
  460. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  461. mrq->cmd->error = MMC_ERR_TIMEOUT;
  462. mmc_request_done(mmc, mrq);
  463. }
  464. static void tifm_sd_end_cmd(struct work_struct *work)
  465. {
  466. struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
  467. struct tifm_dev *sock = host->dev;
  468. struct mmc_host *mmc = tifm_get_drvdata(sock);
  469. struct mmc_request *mrq;
  470. struct mmc_data *r_data = NULL;
  471. unsigned long flags;
  472. spin_lock_irqsave(&sock->lock, flags);
  473. mrq = host->req;
  474. host->req = NULL;
  475. host->state = IDLE;
  476. if (!mrq) {
  477. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  478. spin_unlock_irqrestore(&sock->lock, flags);
  479. return;
  480. }
  481. r_data = mrq->cmd->data;
  482. if (r_data) {
  483. if (r_data->flags & MMC_DATA_WRITE) {
  484. r_data->bytes_xfered = host->written_blocks *
  485. r_data->blksz;
  486. } else {
  487. r_data->bytes_xfered = r_data->blocks -
  488. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  489. r_data->bytes_xfered *= r_data->blksz;
  490. r_data->bytes_xfered += r_data->blksz -
  491. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  492. }
  493. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  494. (r_data->flags & MMC_DATA_WRITE)
  495. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  496. }
  497. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  498. sock->addr + SOCK_CONTROL);
  499. spin_unlock_irqrestore(&sock->lock, flags);
  500. mmc_request_done(mmc, mrq);
  501. }
  502. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  503. {
  504. struct tifm_sd *host = mmc_priv(mmc);
  505. struct tifm_dev *sock = host->dev;
  506. unsigned long flags;
  507. struct mmc_data *r_data = mrq->cmd->data;
  508. spin_lock_irqsave(&sock->lock, flags);
  509. if (host->flags & EJECT) {
  510. spin_unlock_irqrestore(&sock->lock, flags);
  511. goto err_out;
  512. }
  513. if (host->req) {
  514. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  515. spin_unlock_irqrestore(&sock->lock, flags);
  516. goto err_out;
  517. }
  518. if (r_data) {
  519. tifm_sd_set_data_timeout(host, r_data);
  520. host->buffer_size = mrq->cmd->data->blocks *
  521. mrq->cmd->data->blksz;
  522. writel(TIFM_MMCSD_BUFINT |
  523. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  524. sock->addr + SOCK_MMCSD_INT_ENABLE);
  525. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) |
  526. (TIFM_MMCSD_FIFO_SIZE - 1),
  527. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  528. host->written_blocks = 0;
  529. host->flags &= ~CARD_BUSY;
  530. host->buffer_pos = 0;
  531. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  532. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  533. }
  534. host->req = mrq;
  535. host->state = CMD;
  536. queue_delayed_work(sock->wq, &host->abort_handler,
  537. host->timeout_jiffies);
  538. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  539. sock->addr + SOCK_CONTROL);
  540. tifm_sd_exec(host, mrq->cmd);
  541. spin_unlock_irqrestore(&sock->lock, flags);
  542. return;
  543. err_out:
  544. mrq->cmd->error = MMC_ERR_TIMEOUT;
  545. mmc_request_done(mmc, mrq);
  546. }
  547. static void tifm_sd_end_cmd_nodma(struct work_struct *work)
  548. {
  549. struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
  550. struct tifm_dev *sock = host->dev;
  551. struct mmc_host *mmc = tifm_get_drvdata(sock);
  552. struct mmc_request *mrq;
  553. struct mmc_data *r_data = NULL;
  554. unsigned long flags;
  555. spin_lock_irqsave(&sock->lock, flags);
  556. mrq = host->req;
  557. host->req = NULL;
  558. host->state = IDLE;
  559. if (!mrq) {
  560. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  561. spin_unlock_irqrestore(&sock->lock, flags);
  562. return;
  563. }
  564. r_data = mrq->cmd->data;
  565. if (r_data) {
  566. writel((~TIFM_MMCSD_BUFINT) &
  567. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  568. sock->addr + SOCK_MMCSD_INT_ENABLE);
  569. if (r_data->flags & MMC_DATA_WRITE) {
  570. r_data->bytes_xfered = host->written_blocks *
  571. r_data->blksz;
  572. } else {
  573. r_data->bytes_xfered = r_data->blocks -
  574. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  575. r_data->bytes_xfered *= r_data->blksz;
  576. r_data->bytes_xfered += r_data->blksz -
  577. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  578. }
  579. host->buffer_pos = 0;
  580. host->buffer_size = 0;
  581. }
  582. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  583. sock->addr + SOCK_CONTROL);
  584. spin_unlock_irqrestore(&sock->lock, flags);
  585. mmc_request_done(mmc, mrq);
  586. }
  587. static void tifm_sd_abort(struct work_struct *work)
  588. {
  589. struct tifm_sd *host =
  590. container_of(work, struct tifm_sd, abort_handler.work);
  591. printk(KERN_ERR DRIVER_NAME
  592. ": card failed to respond for a long period of time");
  593. tifm_eject(host->dev);
  594. }
  595. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  596. {
  597. struct tifm_sd *host = mmc_priv(mmc);
  598. struct tifm_dev *sock = host->dev;
  599. unsigned int clk_div1, clk_div2;
  600. unsigned long flags;
  601. spin_lock_irqsave(&sock->lock, flags);
  602. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  603. ios->power_mode);
  604. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  605. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  606. sock->addr + SOCK_MMCSD_CONFIG);
  607. } else {
  608. writel((~TIFM_MMCSD_4BBUS) &
  609. readl(sock->addr + SOCK_MMCSD_CONFIG),
  610. sock->addr + SOCK_MMCSD_CONFIG);
  611. }
  612. if (ios->clock) {
  613. clk_div1 = 20000000 / ios->clock;
  614. if (!clk_div1)
  615. clk_div1 = 1;
  616. clk_div2 = 24000000 / ios->clock;
  617. if (!clk_div2)
  618. clk_div2 = 1;
  619. if ((20000000 / clk_div1) > ios->clock)
  620. clk_div1++;
  621. if ((24000000 / clk_div2) > ios->clock)
  622. clk_div2++;
  623. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  624. host->clk_freq = 20000000;
  625. host->clk_div = clk_div1;
  626. writel((~TIFM_CTRL_FAST_CLK) &
  627. readl(sock->addr + SOCK_CONTROL),
  628. sock->addr + SOCK_CONTROL);
  629. } else {
  630. host->clk_freq = 24000000;
  631. host->clk_div = clk_div2;
  632. writel(TIFM_CTRL_FAST_CLK |
  633. readl(sock->addr + SOCK_CONTROL),
  634. sock->addr + SOCK_CONTROL);
  635. }
  636. } else {
  637. host->clk_div = 0;
  638. }
  639. host->clk_div &= TIFM_MMCSD_CLKMASK;
  640. writel(host->clk_div | ((~TIFM_MMCSD_CLKMASK) &
  641. readl(sock->addr + SOCK_MMCSD_CONFIG)),
  642. sock->addr + SOCK_MMCSD_CONFIG);
  643. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  644. host->flags |= OPENDRAIN;
  645. else
  646. host->flags &= ~OPENDRAIN;
  647. /* chip_select : maybe later */
  648. //vdd
  649. //power is set before probe / after remove
  650. //I believe, power_off when already marked for eject is sufficient to
  651. // allow removal.
  652. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  653. host->flags |= EJECT_DONE;
  654. wake_up_all(&host->can_eject);
  655. }
  656. spin_unlock_irqrestore(&sock->lock, flags);
  657. }
  658. static int tifm_sd_ro(struct mmc_host *mmc)
  659. {
  660. int rc;
  661. struct tifm_sd *host = mmc_priv(mmc);
  662. struct tifm_dev *sock = host->dev;
  663. unsigned long flags;
  664. spin_lock_irqsave(&sock->lock, flags);
  665. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  666. rc = (host->flags & CARD_RO) ? 1 : 0;
  667. spin_unlock_irqrestore(&sock->lock, flags);
  668. return rc;
  669. }
  670. static struct mmc_host_ops tifm_sd_ops = {
  671. .request = tifm_sd_request,
  672. .set_ios = tifm_sd_ios,
  673. .get_ro = tifm_sd_ro
  674. };
  675. static void tifm_sd_register_host(struct work_struct *work)
  676. {
  677. struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
  678. struct tifm_dev *sock = host->dev;
  679. struct mmc_host *mmc = tifm_get_drvdata(sock);
  680. unsigned long flags;
  681. spin_lock_irqsave(&sock->lock, flags);
  682. host->flags |= HOST_REG;
  683. PREPARE_WORK(&host->cmd_handler,
  684. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd);
  685. spin_unlock_irqrestore(&sock->lock, flags);
  686. dev_dbg(&sock->dev, "adding host\n");
  687. mmc_add_host(mmc);
  688. }
  689. static int tifm_sd_probe(struct tifm_dev *sock)
  690. {
  691. struct mmc_host *mmc;
  692. struct tifm_sd *host;
  693. int rc = -EIO;
  694. if (!(TIFM_SOCK_STATE_OCCUPIED &
  695. readl(sock->addr + SOCK_PRESENT_STATE))) {
  696. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  697. return rc;
  698. }
  699. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  700. if (!mmc)
  701. return -ENOMEM;
  702. host = mmc_priv(mmc);
  703. host->dev = sock;
  704. host->clk_div = 61;
  705. init_waitqueue_head(&host->can_eject);
  706. INIT_WORK(&host->cmd_handler, tifm_sd_register_host);
  707. INIT_DELAYED_WORK(&host->abort_handler, tifm_sd_abort);
  708. tifm_set_drvdata(sock, mmc);
  709. sock->signal_irq = tifm_sd_signal_irq;
  710. host->clk_freq = 20000000;
  711. host->timeout_jiffies = msecs_to_jiffies(1000);
  712. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  713. mmc->ops = &tifm_sd_ops;
  714. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  715. mmc->caps = MMC_CAP_4_BIT_DATA;
  716. mmc->f_min = 20000000 / 60;
  717. mmc->f_max = 24000000;
  718. mmc->max_hw_segs = 1;
  719. mmc->max_phys_segs = 1;
  720. mmc->max_sectors = 127;
  721. mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
  722. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  723. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  724. writel(host->clk_div | TIFM_MMCSD_POWER,
  725. sock->addr + SOCK_MMCSD_CONFIG);
  726. for (rc = 0; rc < 50; rc++) {
  727. /* Wait for reset ack */
  728. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  729. rc = 0;
  730. break;
  731. }
  732. msleep(10);
  733. }
  734. if (rc) {
  735. printk(KERN_ERR DRIVER_NAME
  736. ": card not ready - probe failed\n");
  737. mmc_free_host(mmc);
  738. return -ENODEV;
  739. }
  740. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  741. writel(host->clk_div | TIFM_MMCSD_POWER,
  742. sock->addr + SOCK_MMCSD_CONFIG);
  743. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  744. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  745. sock->addr + SOCK_MMCSD_INT_ENABLE);
  746. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); // command timeout 64 clocks for now
  747. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  748. writel(host->clk_div | TIFM_MMCSD_POWER,
  749. sock->addr + SOCK_MMCSD_CONFIG);
  750. queue_delayed_work(sock->wq, &host->abort_handler,
  751. host->timeout_jiffies);
  752. return 0;
  753. }
  754. static int tifm_sd_host_is_down(struct tifm_dev *sock)
  755. {
  756. struct mmc_host *mmc = tifm_get_drvdata(sock);
  757. struct tifm_sd *host = mmc_priv(mmc);
  758. unsigned long flags;
  759. int rc = 0;
  760. spin_lock_irqsave(&sock->lock, flags);
  761. rc = (host->flags & EJECT_DONE);
  762. spin_unlock_irqrestore(&sock->lock, flags);
  763. return rc;
  764. }
  765. static void tifm_sd_remove(struct tifm_dev *sock)
  766. {
  767. struct mmc_host *mmc = tifm_get_drvdata(sock);
  768. struct tifm_sd *host = mmc_priv(mmc);
  769. unsigned long flags;
  770. spin_lock_irqsave(&sock->lock, flags);
  771. host->flags |= EJECT;
  772. if (host->req)
  773. queue_work(sock->wq, &host->cmd_handler);
  774. spin_unlock_irqrestore(&sock->lock, flags);
  775. wait_event_timeout(host->can_eject, tifm_sd_host_is_down(sock),
  776. host->timeout_jiffies);
  777. if (host->flags & HOST_REG)
  778. mmc_remove_host(mmc);
  779. /* The meaning of the bit majority in this constant is unknown. */
  780. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  781. sock->addr + SOCK_CONTROL);
  782. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  783. writel(TIFM_FIFO_INT_SETALL,
  784. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  785. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  786. tifm_set_drvdata(sock, NULL);
  787. mmc_free_host(mmc);
  788. }
  789. static tifm_media_id tifm_sd_id_tbl[] = {
  790. FM_SD, 0
  791. };
  792. static struct tifm_driver tifm_sd_driver = {
  793. .driver = {
  794. .name = DRIVER_NAME,
  795. .owner = THIS_MODULE
  796. },
  797. .id_table = tifm_sd_id_tbl,
  798. .probe = tifm_sd_probe,
  799. .remove = tifm_sd_remove
  800. };
  801. static int __init tifm_sd_init(void)
  802. {
  803. return tifm_register_driver(&tifm_sd_driver);
  804. }
  805. static void __exit tifm_sd_exit(void)
  806. {
  807. tifm_unregister_driver(&tifm_sd_driver);
  808. }
  809. MODULE_AUTHOR("Alex Dubov");
  810. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  811. MODULE_LICENSE("GPL");
  812. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  813. MODULE_VERSION(DRIVER_VERSION);
  814. module_init(tifm_sd_init);
  815. module_exit(tifm_sd_exit);