sdhci-pci.c 27 KB

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  1. /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
  2. *
  3. * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or (at
  8. * your option) any later version.
  9. *
  10. * Thanks to the following companies for their support:
  11. *
  12. * - JMicron (hardware and technical support)
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/highmem.h>
  16. #include <linux/pci.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/slab.h>
  19. #include <linux/device.h>
  20. #include <linux/mmc/host.h>
  21. #include <asm/scatterlist.h>
  22. #include <asm/io.h>
  23. #include "sdhci.h"
  24. /*
  25. * PCI registers
  26. */
  27. #define PCI_SDHCI_IFPIO 0x00
  28. #define PCI_SDHCI_IFDMA 0x01
  29. #define PCI_SDHCI_IFVENDOR 0x02
  30. #define PCI_SLOT_INFO 0x40 /* 8 bits */
  31. #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
  32. #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
  33. #define MAX_SLOTS 8
  34. struct sdhci_pci_chip;
  35. struct sdhci_pci_slot;
  36. struct sdhci_pci_fixes {
  37. unsigned int quirks;
  38. int (*probe)(struct sdhci_pci_chip*);
  39. int (*probe_slot)(struct sdhci_pci_slot*);
  40. void (*remove_slot)(struct sdhci_pci_slot*, int);
  41. int (*suspend)(struct sdhci_pci_chip*,
  42. pm_message_t);
  43. int (*resume)(struct sdhci_pci_chip*);
  44. };
  45. struct sdhci_pci_slot {
  46. struct sdhci_pci_chip *chip;
  47. struct sdhci_host *host;
  48. int pci_bar;
  49. };
  50. struct sdhci_pci_chip {
  51. struct pci_dev *pdev;
  52. unsigned int quirks;
  53. const struct sdhci_pci_fixes *fixes;
  54. int num_slots; /* Slots on controller */
  55. struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
  56. };
  57. /*****************************************************************************\
  58. * *
  59. * Hardware specific quirk handling *
  60. * *
  61. \*****************************************************************************/
  62. static int ricoh_probe(struct sdhci_pci_chip *chip)
  63. {
  64. if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
  65. chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
  66. chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
  67. return 0;
  68. }
  69. static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
  70. {
  71. slot->host->caps =
  72. ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
  73. & SDHCI_TIMEOUT_CLK_MASK) |
  74. ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
  75. & SDHCI_CLOCK_BASE_MASK) |
  76. SDHCI_TIMEOUT_CLK_UNIT |
  77. SDHCI_CAN_VDD_330 |
  78. SDHCI_CAN_DO_SDMA;
  79. return 0;
  80. }
  81. static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
  82. {
  83. /* Apply a delay to allow controller to settle */
  84. /* Otherwise it becomes confused if card state changed
  85. during suspend */
  86. msleep(500);
  87. return 0;
  88. }
  89. static const struct sdhci_pci_fixes sdhci_ricoh = {
  90. .probe = ricoh_probe,
  91. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
  92. SDHCI_QUIRK_FORCE_DMA |
  93. SDHCI_QUIRK_CLOCK_BEFORE_RESET,
  94. };
  95. static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
  96. .probe_slot = ricoh_mmc_probe_slot,
  97. .resume = ricoh_mmc_resume,
  98. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
  99. SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  100. SDHCI_QUIRK_NO_CARD_NO_RESET |
  101. SDHCI_QUIRK_MISSING_CAPS
  102. };
  103. static const struct sdhci_pci_fixes sdhci_ene_712 = {
  104. .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  105. SDHCI_QUIRK_BROKEN_DMA,
  106. };
  107. static const struct sdhci_pci_fixes sdhci_ene_714 = {
  108. .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  109. SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
  110. SDHCI_QUIRK_BROKEN_DMA,
  111. };
  112. static const struct sdhci_pci_fixes sdhci_cafe = {
  113. .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
  114. SDHCI_QUIRK_NO_BUSY_IRQ |
  115. SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
  116. };
  117. /*
  118. * ADMA operation is disabled for Moorestown platform due to
  119. * hardware bugs.
  120. */
  121. static int mrst_hc_probe(struct sdhci_pci_chip *chip)
  122. {
  123. /*
  124. * slots number is fixed here for MRST as SDIO3/5 are never used and
  125. * have hardware bugs.
  126. */
  127. chip->num_slots = 1;
  128. return 0;
  129. }
  130. static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
  131. .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
  132. };
  133. static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
  134. .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
  135. .probe = mrst_hc_probe,
  136. };
  137. static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
  138. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  139. };
  140. static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = {
  141. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  142. };
  143. /* O2Micro extra registers */
  144. #define O2_SD_LOCK_WP 0xD3
  145. #define O2_SD_MULTI_VCC3V 0xEE
  146. #define O2_SD_CLKREQ 0xEC
  147. #define O2_SD_CAPS 0xE0
  148. #define O2_SD_ADMA1 0xE2
  149. #define O2_SD_ADMA2 0xE7
  150. #define O2_SD_INF_MOD 0xF1
  151. static int o2_probe(struct sdhci_pci_chip *chip)
  152. {
  153. int ret;
  154. u8 scratch;
  155. switch (chip->pdev->device) {
  156. case PCI_DEVICE_ID_O2_8220:
  157. case PCI_DEVICE_ID_O2_8221:
  158. case PCI_DEVICE_ID_O2_8320:
  159. case PCI_DEVICE_ID_O2_8321:
  160. /* This extra setup is required due to broken ADMA. */
  161. ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
  162. if (ret)
  163. return ret;
  164. scratch &= 0x7f;
  165. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  166. /* Set Multi 3 to VCC3V# */
  167. pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
  168. /* Disable CLK_REQ# support after media DET */
  169. ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
  170. if (ret)
  171. return ret;
  172. scratch |= 0x20;
  173. pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
  174. /* Choose capabilities, enable SDMA. We have to write 0x01
  175. * to the capabilities register first to unlock it.
  176. */
  177. ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
  178. if (ret)
  179. return ret;
  180. scratch |= 0x01;
  181. pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
  182. pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
  183. /* Disable ADMA1/2 */
  184. pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
  185. pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
  186. /* Disable the infinite transfer mode */
  187. ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
  188. if (ret)
  189. return ret;
  190. scratch |= 0x08;
  191. pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
  192. /* Lock WP */
  193. ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
  194. if (ret)
  195. return ret;
  196. scratch |= 0x80;
  197. pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
  198. }
  199. return 0;
  200. }
  201. static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
  202. {
  203. u8 scratch;
  204. int ret;
  205. ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
  206. if (ret)
  207. return ret;
  208. /*
  209. * Turn PMOS on [bit 0], set over current detection to 2.4 V
  210. * [bit 1:2] and enable over current debouncing [bit 6].
  211. */
  212. if (on)
  213. scratch |= 0x47;
  214. else
  215. scratch &= ~0x47;
  216. ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
  217. if (ret)
  218. return ret;
  219. return 0;
  220. }
  221. static int jmicron_probe(struct sdhci_pci_chip *chip)
  222. {
  223. int ret;
  224. u16 mmcdev = 0;
  225. if (chip->pdev->revision == 0) {
  226. chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
  227. SDHCI_QUIRK_32BIT_DMA_SIZE |
  228. SDHCI_QUIRK_32BIT_ADMA_SIZE |
  229. SDHCI_QUIRK_RESET_AFTER_REQUEST |
  230. SDHCI_QUIRK_BROKEN_SMALL_PIO;
  231. }
  232. /*
  233. * JMicron chips can have two interfaces to the same hardware
  234. * in order to work around limitations in Microsoft's driver.
  235. * We need to make sure we only bind to one of them.
  236. *
  237. * This code assumes two things:
  238. *
  239. * 1. The PCI code adds subfunctions in order.
  240. *
  241. * 2. The MMC interface has a lower subfunction number
  242. * than the SD interface.
  243. */
  244. if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
  245. mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
  246. else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
  247. mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
  248. if (mmcdev) {
  249. struct pci_dev *sd_dev;
  250. sd_dev = NULL;
  251. while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
  252. mmcdev, sd_dev)) != NULL) {
  253. if ((PCI_SLOT(chip->pdev->devfn) ==
  254. PCI_SLOT(sd_dev->devfn)) &&
  255. (chip->pdev->bus == sd_dev->bus))
  256. break;
  257. }
  258. if (sd_dev) {
  259. pci_dev_put(sd_dev);
  260. dev_info(&chip->pdev->dev, "Refusing to bind to "
  261. "secondary interface.\n");
  262. return -ENODEV;
  263. }
  264. }
  265. /*
  266. * JMicron chips need a bit of a nudge to enable the power
  267. * output pins.
  268. */
  269. ret = jmicron_pmos(chip, 1);
  270. if (ret) {
  271. dev_err(&chip->pdev->dev, "Failure enabling card power\n");
  272. return ret;
  273. }
  274. return 0;
  275. }
  276. static void jmicron_enable_mmc(struct sdhci_host *host, int on)
  277. {
  278. u8 scratch;
  279. scratch = readb(host->ioaddr + 0xC0);
  280. if (on)
  281. scratch |= 0x01;
  282. else
  283. scratch &= ~0x01;
  284. writeb(scratch, host->ioaddr + 0xC0);
  285. }
  286. static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
  287. {
  288. if (slot->chip->pdev->revision == 0) {
  289. u16 version;
  290. version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
  291. version = (version & SDHCI_VENDOR_VER_MASK) >>
  292. SDHCI_VENDOR_VER_SHIFT;
  293. /*
  294. * Older versions of the chip have lots of nasty glitches
  295. * in the ADMA engine. It's best just to avoid it
  296. * completely.
  297. */
  298. if (version < 0xAC)
  299. slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
  300. }
  301. /* JM388 MMC doesn't support 1.8V while SD supports it */
  302. if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
  303. slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
  304. MMC_VDD_29_30 | MMC_VDD_30_31 |
  305. MMC_VDD_165_195; /* allow 1.8V */
  306. slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
  307. MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
  308. }
  309. /*
  310. * The secondary interface requires a bit set to get the
  311. * interrupts.
  312. */
  313. if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
  314. slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
  315. jmicron_enable_mmc(slot->host, 1);
  316. slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
  317. return 0;
  318. }
  319. static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
  320. {
  321. if (dead)
  322. return;
  323. if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
  324. slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
  325. jmicron_enable_mmc(slot->host, 0);
  326. }
  327. static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
  328. {
  329. int i;
  330. if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
  331. chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
  332. for (i = 0;i < chip->num_slots;i++)
  333. jmicron_enable_mmc(chip->slots[i]->host, 0);
  334. }
  335. return 0;
  336. }
  337. static int jmicron_resume(struct sdhci_pci_chip *chip)
  338. {
  339. int ret, i;
  340. if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
  341. chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
  342. for (i = 0;i < chip->num_slots;i++)
  343. jmicron_enable_mmc(chip->slots[i]->host, 1);
  344. }
  345. ret = jmicron_pmos(chip, 1);
  346. if (ret) {
  347. dev_err(&chip->pdev->dev, "Failure enabling card power\n");
  348. return ret;
  349. }
  350. return 0;
  351. }
  352. static const struct sdhci_pci_fixes sdhci_o2 = {
  353. .probe = o2_probe,
  354. };
  355. static const struct sdhci_pci_fixes sdhci_jmicron = {
  356. .probe = jmicron_probe,
  357. .probe_slot = jmicron_probe_slot,
  358. .remove_slot = jmicron_remove_slot,
  359. .suspend = jmicron_suspend,
  360. .resume = jmicron_resume,
  361. };
  362. /* SysKonnect CardBus2SDIO extra registers */
  363. #define SYSKT_CTRL 0x200
  364. #define SYSKT_RDFIFO_STAT 0x204
  365. #define SYSKT_WRFIFO_STAT 0x208
  366. #define SYSKT_POWER_DATA 0x20c
  367. #define SYSKT_POWER_330 0xef
  368. #define SYSKT_POWER_300 0xf8
  369. #define SYSKT_POWER_184 0xcc
  370. #define SYSKT_POWER_CMD 0x20d
  371. #define SYSKT_POWER_START (1 << 7)
  372. #define SYSKT_POWER_STATUS 0x20e
  373. #define SYSKT_POWER_STATUS_OK (1 << 0)
  374. #define SYSKT_BOARD_REV 0x210
  375. #define SYSKT_CHIP_REV 0x211
  376. #define SYSKT_CONF_DATA 0x212
  377. #define SYSKT_CONF_DATA_1V8 (1 << 2)
  378. #define SYSKT_CONF_DATA_2V5 (1 << 1)
  379. #define SYSKT_CONF_DATA_3V3 (1 << 0)
  380. static int syskt_probe(struct sdhci_pci_chip *chip)
  381. {
  382. if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  383. chip->pdev->class &= ~0x0000FF;
  384. chip->pdev->class |= PCI_SDHCI_IFDMA;
  385. }
  386. return 0;
  387. }
  388. static int syskt_probe_slot(struct sdhci_pci_slot *slot)
  389. {
  390. int tm, ps;
  391. u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
  392. u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
  393. dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
  394. "board rev %d.%d, chip rev %d.%d\n",
  395. board_rev >> 4, board_rev & 0xf,
  396. chip_rev >> 4, chip_rev & 0xf);
  397. if (chip_rev >= 0x20)
  398. slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
  399. writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
  400. writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
  401. udelay(50);
  402. tm = 10; /* Wait max 1 ms */
  403. do {
  404. ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
  405. if (ps & SYSKT_POWER_STATUS_OK)
  406. break;
  407. udelay(100);
  408. } while (--tm);
  409. if (!tm) {
  410. dev_err(&slot->chip->pdev->dev,
  411. "power regulator never stabilized");
  412. writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
  413. return -ENODEV;
  414. }
  415. return 0;
  416. }
  417. static const struct sdhci_pci_fixes sdhci_syskt = {
  418. .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
  419. .probe = syskt_probe,
  420. .probe_slot = syskt_probe_slot,
  421. };
  422. static int via_probe(struct sdhci_pci_chip *chip)
  423. {
  424. if (chip->pdev->revision == 0x10)
  425. chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
  426. return 0;
  427. }
  428. static const struct sdhci_pci_fixes sdhci_via = {
  429. .probe = via_probe,
  430. };
  431. static const struct pci_device_id pci_ids[] __devinitdata = {
  432. {
  433. .vendor = PCI_VENDOR_ID_RICOH,
  434. .device = PCI_DEVICE_ID_RICOH_R5C822,
  435. .subvendor = PCI_ANY_ID,
  436. .subdevice = PCI_ANY_ID,
  437. .driver_data = (kernel_ulong_t)&sdhci_ricoh,
  438. },
  439. {
  440. .vendor = PCI_VENDOR_ID_RICOH,
  441. .device = 0x843,
  442. .subvendor = PCI_ANY_ID,
  443. .subdevice = PCI_ANY_ID,
  444. .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
  445. },
  446. {
  447. .vendor = PCI_VENDOR_ID_RICOH,
  448. .device = 0xe822,
  449. .subvendor = PCI_ANY_ID,
  450. .subdevice = PCI_ANY_ID,
  451. .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
  452. },
  453. {
  454. .vendor = PCI_VENDOR_ID_RICOH,
  455. .device = 0xe823,
  456. .subvendor = PCI_ANY_ID,
  457. .subdevice = PCI_ANY_ID,
  458. .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
  459. },
  460. {
  461. .vendor = PCI_VENDOR_ID_ENE,
  462. .device = PCI_DEVICE_ID_ENE_CB712_SD,
  463. .subvendor = PCI_ANY_ID,
  464. .subdevice = PCI_ANY_ID,
  465. .driver_data = (kernel_ulong_t)&sdhci_ene_712,
  466. },
  467. {
  468. .vendor = PCI_VENDOR_ID_ENE,
  469. .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
  470. .subvendor = PCI_ANY_ID,
  471. .subdevice = PCI_ANY_ID,
  472. .driver_data = (kernel_ulong_t)&sdhci_ene_712,
  473. },
  474. {
  475. .vendor = PCI_VENDOR_ID_ENE,
  476. .device = PCI_DEVICE_ID_ENE_CB714_SD,
  477. .subvendor = PCI_ANY_ID,
  478. .subdevice = PCI_ANY_ID,
  479. .driver_data = (kernel_ulong_t)&sdhci_ene_714,
  480. },
  481. {
  482. .vendor = PCI_VENDOR_ID_ENE,
  483. .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
  484. .subvendor = PCI_ANY_ID,
  485. .subdevice = PCI_ANY_ID,
  486. .driver_data = (kernel_ulong_t)&sdhci_ene_714,
  487. },
  488. {
  489. .vendor = PCI_VENDOR_ID_MARVELL,
  490. .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
  491. .subvendor = PCI_ANY_ID,
  492. .subdevice = PCI_ANY_ID,
  493. .driver_data = (kernel_ulong_t)&sdhci_cafe,
  494. },
  495. {
  496. .vendor = PCI_VENDOR_ID_JMICRON,
  497. .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
  498. .subvendor = PCI_ANY_ID,
  499. .subdevice = PCI_ANY_ID,
  500. .driver_data = (kernel_ulong_t)&sdhci_jmicron,
  501. },
  502. {
  503. .vendor = PCI_VENDOR_ID_JMICRON,
  504. .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
  505. .subvendor = PCI_ANY_ID,
  506. .subdevice = PCI_ANY_ID,
  507. .driver_data = (kernel_ulong_t)&sdhci_jmicron,
  508. },
  509. {
  510. .vendor = PCI_VENDOR_ID_JMICRON,
  511. .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
  512. .subvendor = PCI_ANY_ID,
  513. .subdevice = PCI_ANY_ID,
  514. .driver_data = (kernel_ulong_t)&sdhci_jmicron,
  515. },
  516. {
  517. .vendor = PCI_VENDOR_ID_JMICRON,
  518. .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
  519. .subvendor = PCI_ANY_ID,
  520. .subdevice = PCI_ANY_ID,
  521. .driver_data = (kernel_ulong_t)&sdhci_jmicron,
  522. },
  523. {
  524. .vendor = PCI_VENDOR_ID_SYSKONNECT,
  525. .device = 0x8000,
  526. .subvendor = PCI_ANY_ID,
  527. .subdevice = PCI_ANY_ID,
  528. .driver_data = (kernel_ulong_t)&sdhci_syskt,
  529. },
  530. {
  531. .vendor = PCI_VENDOR_ID_VIA,
  532. .device = 0x95d0,
  533. .subvendor = PCI_ANY_ID,
  534. .subdevice = PCI_ANY_ID,
  535. .driver_data = (kernel_ulong_t)&sdhci_via,
  536. },
  537. {
  538. .vendor = PCI_VENDOR_ID_INTEL,
  539. .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
  540. .subvendor = PCI_ANY_ID,
  541. .subdevice = PCI_ANY_ID,
  542. .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
  543. },
  544. {
  545. .vendor = PCI_VENDOR_ID_INTEL,
  546. .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
  547. .subvendor = PCI_ANY_ID,
  548. .subdevice = PCI_ANY_ID,
  549. .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
  550. },
  551. {
  552. .vendor = PCI_VENDOR_ID_INTEL,
  553. .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
  554. .subvendor = PCI_ANY_ID,
  555. .subdevice = PCI_ANY_ID,
  556. .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
  557. },
  558. {
  559. .vendor = PCI_VENDOR_ID_INTEL,
  560. .device = PCI_DEVICE_ID_INTEL_MFD_SD,
  561. .subvendor = PCI_ANY_ID,
  562. .subdevice = PCI_ANY_ID,
  563. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
  564. },
  565. {
  566. .vendor = PCI_VENDOR_ID_INTEL,
  567. .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
  568. .subvendor = PCI_ANY_ID,
  569. .subdevice = PCI_ANY_ID,
  570. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  571. },
  572. {
  573. .vendor = PCI_VENDOR_ID_INTEL,
  574. .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
  575. .subvendor = PCI_ANY_ID,
  576. .subdevice = PCI_ANY_ID,
  577. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  578. },
  579. {
  580. .vendor = PCI_VENDOR_ID_INTEL,
  581. .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
  582. .subvendor = PCI_ANY_ID,
  583. .subdevice = PCI_ANY_ID,
  584. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  585. },
  586. {
  587. .vendor = PCI_VENDOR_ID_INTEL,
  588. .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
  589. .subvendor = PCI_ANY_ID,
  590. .subdevice = PCI_ANY_ID,
  591. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  592. },
  593. {
  594. .vendor = PCI_VENDOR_ID_O2,
  595. .device = PCI_DEVICE_ID_O2_8120,
  596. .subvendor = PCI_ANY_ID,
  597. .subdevice = PCI_ANY_ID,
  598. .driver_data = (kernel_ulong_t)&sdhci_o2,
  599. },
  600. {
  601. .vendor = PCI_VENDOR_ID_O2,
  602. .device = PCI_DEVICE_ID_O2_8220,
  603. .subvendor = PCI_ANY_ID,
  604. .subdevice = PCI_ANY_ID,
  605. .driver_data = (kernel_ulong_t)&sdhci_o2,
  606. },
  607. {
  608. .vendor = PCI_VENDOR_ID_O2,
  609. .device = PCI_DEVICE_ID_O2_8221,
  610. .subvendor = PCI_ANY_ID,
  611. .subdevice = PCI_ANY_ID,
  612. .driver_data = (kernel_ulong_t)&sdhci_o2,
  613. },
  614. {
  615. .vendor = PCI_VENDOR_ID_O2,
  616. .device = PCI_DEVICE_ID_O2_8320,
  617. .subvendor = PCI_ANY_ID,
  618. .subdevice = PCI_ANY_ID,
  619. .driver_data = (kernel_ulong_t)&sdhci_o2,
  620. },
  621. {
  622. .vendor = PCI_VENDOR_ID_O2,
  623. .device = PCI_DEVICE_ID_O2_8321,
  624. .subvendor = PCI_ANY_ID,
  625. .subdevice = PCI_ANY_ID,
  626. .driver_data = (kernel_ulong_t)&sdhci_o2,
  627. },
  628. { /* Generic SD host controller */
  629. PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  630. },
  631. { /* end: all zeroes */ },
  632. };
  633. MODULE_DEVICE_TABLE(pci, pci_ids);
  634. /*****************************************************************************\
  635. * *
  636. * SDHCI core callbacks *
  637. * *
  638. \*****************************************************************************/
  639. static int sdhci_pci_enable_dma(struct sdhci_host *host)
  640. {
  641. struct sdhci_pci_slot *slot;
  642. struct pci_dev *pdev;
  643. int ret;
  644. slot = sdhci_priv(host);
  645. pdev = slot->chip->pdev;
  646. if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
  647. ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
  648. (host->flags & SDHCI_USE_SDMA)) {
  649. dev_warn(&pdev->dev, "Will use DMA mode even though HW "
  650. "doesn't fully claim to support it.\n");
  651. }
  652. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  653. if (ret)
  654. return ret;
  655. pci_set_master(pdev);
  656. return 0;
  657. }
  658. static struct sdhci_ops sdhci_pci_ops = {
  659. .enable_dma = sdhci_pci_enable_dma,
  660. };
  661. /*****************************************************************************\
  662. * *
  663. * Suspend/resume *
  664. * *
  665. \*****************************************************************************/
  666. #ifdef CONFIG_PM
  667. static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
  668. {
  669. struct sdhci_pci_chip *chip;
  670. struct sdhci_pci_slot *slot;
  671. mmc_pm_flag_t slot_pm_flags;
  672. mmc_pm_flag_t pm_flags = 0;
  673. int i, ret;
  674. chip = pci_get_drvdata(pdev);
  675. if (!chip)
  676. return 0;
  677. for (i = 0;i < chip->num_slots;i++) {
  678. slot = chip->slots[i];
  679. if (!slot)
  680. continue;
  681. ret = sdhci_suspend_host(slot->host, state);
  682. if (ret) {
  683. for (i--;i >= 0;i--)
  684. sdhci_resume_host(chip->slots[i]->host);
  685. return ret;
  686. }
  687. slot_pm_flags = slot->host->mmc->pm_flags;
  688. if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
  689. sdhci_enable_irq_wakeups(slot->host);
  690. pm_flags |= slot_pm_flags;
  691. }
  692. if (chip->fixes && chip->fixes->suspend) {
  693. ret = chip->fixes->suspend(chip, state);
  694. if (ret) {
  695. for (i = chip->num_slots - 1;i >= 0;i--)
  696. sdhci_resume_host(chip->slots[i]->host);
  697. return ret;
  698. }
  699. }
  700. pci_save_state(pdev);
  701. if (pm_flags & MMC_PM_KEEP_POWER) {
  702. if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
  703. pci_pme_active(pdev, true);
  704. pci_enable_wake(pdev, PCI_D3hot, 1);
  705. }
  706. pci_set_power_state(pdev, PCI_D3hot);
  707. } else {
  708. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  709. pci_disable_device(pdev);
  710. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  711. }
  712. return 0;
  713. }
  714. static int sdhci_pci_resume (struct pci_dev *pdev)
  715. {
  716. struct sdhci_pci_chip *chip;
  717. struct sdhci_pci_slot *slot;
  718. int i, ret;
  719. chip = pci_get_drvdata(pdev);
  720. if (!chip)
  721. return 0;
  722. pci_set_power_state(pdev, PCI_D0);
  723. pci_restore_state(pdev);
  724. ret = pci_enable_device(pdev);
  725. if (ret)
  726. return ret;
  727. if (chip->fixes && chip->fixes->resume) {
  728. ret = chip->fixes->resume(chip);
  729. if (ret)
  730. return ret;
  731. }
  732. for (i = 0;i < chip->num_slots;i++) {
  733. slot = chip->slots[i];
  734. if (!slot)
  735. continue;
  736. ret = sdhci_resume_host(slot->host);
  737. if (ret)
  738. return ret;
  739. }
  740. return 0;
  741. }
  742. #else /* CONFIG_PM */
  743. #define sdhci_pci_suspend NULL
  744. #define sdhci_pci_resume NULL
  745. #endif /* CONFIG_PM */
  746. /*****************************************************************************\
  747. * *
  748. * Device probing/removal *
  749. * *
  750. \*****************************************************************************/
  751. static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
  752. struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
  753. {
  754. struct sdhci_pci_slot *slot;
  755. struct sdhci_host *host;
  756. int ret;
  757. if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
  758. dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
  759. return ERR_PTR(-ENODEV);
  760. }
  761. if (pci_resource_len(pdev, bar) != 0x100) {
  762. dev_err(&pdev->dev, "Invalid iomem size. You may "
  763. "experience problems.\n");
  764. }
  765. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  766. dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
  767. return ERR_PTR(-ENODEV);
  768. }
  769. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  770. dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
  771. return ERR_PTR(-ENODEV);
  772. }
  773. host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
  774. if (IS_ERR(host)) {
  775. dev_err(&pdev->dev, "cannot allocate host\n");
  776. return ERR_CAST(host);
  777. }
  778. slot = sdhci_priv(host);
  779. slot->chip = chip;
  780. slot->host = host;
  781. slot->pci_bar = bar;
  782. host->hw_name = "PCI";
  783. host->ops = &sdhci_pci_ops;
  784. host->quirks = chip->quirks;
  785. host->irq = pdev->irq;
  786. ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
  787. if (ret) {
  788. dev_err(&pdev->dev, "cannot request region\n");
  789. goto free;
  790. }
  791. host->ioaddr = pci_ioremap_bar(pdev, bar);
  792. if (!host->ioaddr) {
  793. dev_err(&pdev->dev, "failed to remap registers\n");
  794. ret = -ENOMEM;
  795. goto release;
  796. }
  797. if (chip->fixes && chip->fixes->probe_slot) {
  798. ret = chip->fixes->probe_slot(slot);
  799. if (ret)
  800. goto unmap;
  801. }
  802. host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
  803. ret = sdhci_add_host(host);
  804. if (ret)
  805. goto remove;
  806. return slot;
  807. remove:
  808. if (chip->fixes && chip->fixes->remove_slot)
  809. chip->fixes->remove_slot(slot, 0);
  810. unmap:
  811. iounmap(host->ioaddr);
  812. release:
  813. pci_release_region(pdev, bar);
  814. free:
  815. sdhci_free_host(host);
  816. return ERR_PTR(ret);
  817. }
  818. static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
  819. {
  820. int dead;
  821. u32 scratch;
  822. dead = 0;
  823. scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
  824. if (scratch == (u32)-1)
  825. dead = 1;
  826. sdhci_remove_host(slot->host, dead);
  827. if (slot->chip->fixes && slot->chip->fixes->remove_slot)
  828. slot->chip->fixes->remove_slot(slot, dead);
  829. pci_release_region(slot->chip->pdev, slot->pci_bar);
  830. sdhci_free_host(slot->host);
  831. }
  832. static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
  833. const struct pci_device_id *ent)
  834. {
  835. struct sdhci_pci_chip *chip;
  836. struct sdhci_pci_slot *slot;
  837. u8 slots, first_bar;
  838. int ret, i;
  839. BUG_ON(pdev == NULL);
  840. BUG_ON(ent == NULL);
  841. dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
  842. (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
  843. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  844. if (ret)
  845. return ret;
  846. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  847. dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
  848. if (slots == 0)
  849. return -ENODEV;
  850. BUG_ON(slots > MAX_SLOTS);
  851. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  852. if (ret)
  853. return ret;
  854. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  855. if (first_bar > 5) {
  856. dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
  857. return -ENODEV;
  858. }
  859. ret = pci_enable_device(pdev);
  860. if (ret)
  861. return ret;
  862. chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
  863. if (!chip) {
  864. ret = -ENOMEM;
  865. goto err;
  866. }
  867. chip->pdev = pdev;
  868. chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data;
  869. if (chip->fixes)
  870. chip->quirks = chip->fixes->quirks;
  871. chip->num_slots = slots;
  872. pci_set_drvdata(pdev, chip);
  873. if (chip->fixes && chip->fixes->probe) {
  874. ret = chip->fixes->probe(chip);
  875. if (ret)
  876. goto free;
  877. }
  878. slots = chip->num_slots; /* Quirk may have changed this */
  879. for (i = 0;i < slots;i++) {
  880. slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
  881. if (IS_ERR(slot)) {
  882. for (i--;i >= 0;i--)
  883. sdhci_pci_remove_slot(chip->slots[i]);
  884. ret = PTR_ERR(slot);
  885. goto free;
  886. }
  887. chip->slots[i] = slot;
  888. }
  889. return 0;
  890. free:
  891. pci_set_drvdata(pdev, NULL);
  892. kfree(chip);
  893. err:
  894. pci_disable_device(pdev);
  895. return ret;
  896. }
  897. static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
  898. {
  899. int i;
  900. struct sdhci_pci_chip *chip;
  901. chip = pci_get_drvdata(pdev);
  902. if (chip) {
  903. for (i = 0;i < chip->num_slots; i++)
  904. sdhci_pci_remove_slot(chip->slots[i]);
  905. pci_set_drvdata(pdev, NULL);
  906. kfree(chip);
  907. }
  908. pci_disable_device(pdev);
  909. }
  910. static struct pci_driver sdhci_driver = {
  911. .name = "sdhci-pci",
  912. .id_table = pci_ids,
  913. .probe = sdhci_pci_probe,
  914. .remove = __devexit_p(sdhci_pci_remove),
  915. .suspend = sdhci_pci_suspend,
  916. .resume = sdhci_pci_resume,
  917. };
  918. /*****************************************************************************\
  919. * *
  920. * Driver init/exit *
  921. * *
  922. \*****************************************************************************/
  923. static int __init sdhci_drv_init(void)
  924. {
  925. return pci_register_driver(&sdhci_driver);
  926. }
  927. static void __exit sdhci_drv_exit(void)
  928. {
  929. pci_unregister_driver(&sdhci_driver);
  930. }
  931. module_init(sdhci_drv_init);
  932. module_exit(sdhci_drv_exit);
  933. MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
  934. MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
  935. MODULE_LICENSE("GPL");