mce_amd.c 15 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kobject.h>
  21. #include <linux/notifier.h>
  22. #include <linux/sched.h>
  23. #include <linux/smp.h>
  24. #include <linux/sysdev.h>
  25. #include <linux/sysfs.h>
  26. #include <asm/apic.h>
  27. #include <asm/mce.h>
  28. #include <asm/msr.h>
  29. #include <asm/percpu.h>
  30. #include <asm/idle.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_CNTP_HI 0x40000000
  39. #define MASK_LOCKED_HI 0x20000000
  40. #define MASK_LVTOFF_HI 0x00F00000
  41. #define MASK_COUNT_EN_HI 0x00080000
  42. #define MASK_INT_TYPE_HI 0x00060000
  43. #define MASK_OVERFLOW_HI 0x00010000
  44. #define MASK_ERR_COUNT_HI 0x00000FFF
  45. #define MASK_BLKPTR_LO 0xFF000000
  46. #define MCG_XBLK_ADDR 0xC0000400
  47. struct threshold_block {
  48. unsigned int block;
  49. unsigned int bank;
  50. unsigned int cpu;
  51. u32 address;
  52. u16 interrupt_enable;
  53. u16 threshold_limit;
  54. struct kobject kobj;
  55. struct list_head miscj;
  56. };
  57. /* defaults used early on boot */
  58. static struct threshold_block threshold_defaults = {
  59. .interrupt_enable = 0,
  60. .threshold_limit = THRESHOLD_MAX,
  61. };
  62. struct threshold_bank {
  63. struct kobject kobj;
  64. struct threshold_block *blocks;
  65. cpumask_t cpus;
  66. };
  67. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  68. #ifdef CONFIG_SMP
  69. static unsigned char shared_bank[NR_BANKS] = {
  70. 0, 0, 0, 0, 1
  71. };
  72. #endif
  73. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  74. /*
  75. * CPU Initialization
  76. */
  77. /* must be called with correct cpu affinity */
  78. static void threshold_restart_bank(struct threshold_block *b,
  79. int reset, u16 old_limit)
  80. {
  81. u32 mci_misc_hi, mci_misc_lo;
  82. rdmsr(b->address, mci_misc_lo, mci_misc_hi);
  83. if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  84. reset = 1; /* limit cannot be lower than err count */
  85. if (reset) { /* reset err count and overflow bit */
  86. mci_misc_hi =
  87. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  88. (THRESHOLD_MAX - b->threshold_limit);
  89. } else if (old_limit) { /* change limit w/o reset */
  90. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  91. (old_limit - b->threshold_limit);
  92. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  93. (new_count & THRESHOLD_MAX);
  94. }
  95. b->interrupt_enable ?
  96. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  97. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  98. mci_misc_hi |= MASK_COUNT_EN_HI;
  99. wrmsr(b->address, mci_misc_lo, mci_misc_hi);
  100. }
  101. /* cpu init entry point, called from mce.c with preempt off */
  102. void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
  103. {
  104. unsigned int bank, block;
  105. unsigned int cpu = smp_processor_id();
  106. u32 low = 0, high = 0, address = 0;
  107. for (bank = 0; bank < NR_BANKS; ++bank) {
  108. for (block = 0; block < NR_BLOCKS; ++block) {
  109. if (block == 0)
  110. address = MSR_IA32_MC0_MISC + bank * 4;
  111. else if (block == 1) {
  112. address = (low & MASK_BLKPTR_LO) >> 21;
  113. if (!address)
  114. break;
  115. address += MCG_XBLK_ADDR;
  116. }
  117. else
  118. ++address;
  119. if (rdmsr_safe(address, &low, &high))
  120. break;
  121. if (!(high & MASK_VALID_HI)) {
  122. if (block)
  123. continue;
  124. else
  125. break;
  126. }
  127. if (!(high & MASK_CNTP_HI) ||
  128. (high & MASK_LOCKED_HI))
  129. continue;
  130. if (!block)
  131. per_cpu(bank_map, cpu) |= (1 << bank);
  132. #ifdef CONFIG_SMP
  133. if (shared_bank[bank] && c->cpu_core_id)
  134. break;
  135. #endif
  136. high &= ~MASK_LVTOFF_HI;
  137. high |= K8_APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
  138. wrmsr(address, low, high);
  139. setup_APIC_extened_lvt(K8_APIC_EXT_LVT_ENTRY_THRESHOLD,
  140. THRESHOLD_APIC_VECTOR,
  141. K8_APIC_EXT_INT_MSG_FIX, 0);
  142. threshold_defaults.address = address;
  143. threshold_restart_bank(&threshold_defaults, 0, 0);
  144. }
  145. }
  146. }
  147. /*
  148. * APIC Interrupt Handler
  149. */
  150. /*
  151. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  152. * the interrupt goes off when error_count reaches threshold_limit.
  153. * the handler will simply log mcelog w/ software defined bank number.
  154. */
  155. asmlinkage void mce_threshold_interrupt(void)
  156. {
  157. unsigned int bank, block;
  158. struct mce m;
  159. u32 low = 0, high = 0, address = 0;
  160. ack_APIC_irq();
  161. exit_idle();
  162. irq_enter();
  163. memset(&m, 0, sizeof(m));
  164. rdtscll(m.tsc);
  165. m.cpu = smp_processor_id();
  166. /* assume first bank caused it */
  167. for (bank = 0; bank < NR_BANKS; ++bank) {
  168. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  169. continue;
  170. for (block = 0; block < NR_BLOCKS; ++block) {
  171. if (block == 0)
  172. address = MSR_IA32_MC0_MISC + bank * 4;
  173. else if (block == 1) {
  174. address = (low & MASK_BLKPTR_LO) >> 21;
  175. if (!address)
  176. break;
  177. address += MCG_XBLK_ADDR;
  178. }
  179. else
  180. ++address;
  181. if (rdmsr_safe(address, &low, &high))
  182. break;
  183. if (!(high & MASK_VALID_HI)) {
  184. if (block)
  185. continue;
  186. else
  187. break;
  188. }
  189. if (!(high & MASK_CNTP_HI) ||
  190. (high & MASK_LOCKED_HI))
  191. continue;
  192. if (high & MASK_OVERFLOW_HI) {
  193. rdmsrl(address, m.misc);
  194. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  195. m.status);
  196. m.bank = K8_MCE_THRESHOLD_BASE
  197. + bank * NR_BLOCKS
  198. + block;
  199. mce_log(&m);
  200. goto out;
  201. }
  202. }
  203. }
  204. out:
  205. irq_exit();
  206. }
  207. /*
  208. * Sysfs Interface
  209. */
  210. struct threshold_attr {
  211. struct attribute attr;
  212. ssize_t(*show) (struct threshold_block *, char *);
  213. ssize_t(*store) (struct threshold_block *, const char *, size_t count);
  214. };
  215. static cpumask_t affinity_set(unsigned int cpu)
  216. {
  217. cpumask_t oldmask = current->cpus_allowed;
  218. cpumask_t newmask = CPU_MASK_NONE;
  219. cpu_set(cpu, newmask);
  220. set_cpus_allowed(current, newmask);
  221. return oldmask;
  222. }
  223. static void affinity_restore(cpumask_t oldmask)
  224. {
  225. set_cpus_allowed(current, oldmask);
  226. }
  227. #define SHOW_FIELDS(name) \
  228. static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
  229. { \
  230. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  231. }
  232. SHOW_FIELDS(interrupt_enable)
  233. SHOW_FIELDS(threshold_limit)
  234. static ssize_t store_interrupt_enable(struct threshold_block *b,
  235. const char *buf, size_t count)
  236. {
  237. char *end;
  238. cpumask_t oldmask;
  239. unsigned long new = simple_strtoul(buf, &end, 0);
  240. if (end == buf)
  241. return -EINVAL;
  242. b->interrupt_enable = !!new;
  243. oldmask = affinity_set(b->cpu);
  244. threshold_restart_bank(b, 0, 0);
  245. affinity_restore(oldmask);
  246. return end - buf;
  247. }
  248. static ssize_t store_threshold_limit(struct threshold_block *b,
  249. const char *buf, size_t count)
  250. {
  251. char *end;
  252. cpumask_t oldmask;
  253. u16 old;
  254. unsigned long new = simple_strtoul(buf, &end, 0);
  255. if (end == buf)
  256. return -EINVAL;
  257. if (new > THRESHOLD_MAX)
  258. new = THRESHOLD_MAX;
  259. if (new < 1)
  260. new = 1;
  261. old = b->threshold_limit;
  262. b->threshold_limit = new;
  263. oldmask = affinity_set(b->cpu);
  264. threshold_restart_bank(b, 0, old);
  265. affinity_restore(oldmask);
  266. return end - buf;
  267. }
  268. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  269. {
  270. u32 high, low;
  271. cpumask_t oldmask;
  272. oldmask = affinity_set(b->cpu);
  273. rdmsr(b->address, low, high);
  274. affinity_restore(oldmask);
  275. return sprintf(buf, "%x\n",
  276. (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
  277. }
  278. static ssize_t store_error_count(struct threshold_block *b,
  279. const char *buf, size_t count)
  280. {
  281. cpumask_t oldmask;
  282. oldmask = affinity_set(b->cpu);
  283. threshold_restart_bank(b, 1, 0);
  284. affinity_restore(oldmask);
  285. return 1;
  286. }
  287. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  288. .attr = {.name = __stringify(_name), .mode = _mode }, \
  289. .show = _show, \
  290. .store = _store, \
  291. };
  292. #define RW_ATTR(name) \
  293. static struct threshold_attr name = \
  294. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  295. RW_ATTR(interrupt_enable);
  296. RW_ATTR(threshold_limit);
  297. RW_ATTR(error_count);
  298. static struct attribute *default_attrs[] = {
  299. &interrupt_enable.attr,
  300. &threshold_limit.attr,
  301. &error_count.attr,
  302. NULL
  303. };
  304. #define to_block(k) container_of(k, struct threshold_block, kobj)
  305. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  306. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  307. {
  308. struct threshold_block *b = to_block(kobj);
  309. struct threshold_attr *a = to_attr(attr);
  310. ssize_t ret;
  311. ret = a->show ? a->show(b, buf) : -EIO;
  312. return ret;
  313. }
  314. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  315. const char *buf, size_t count)
  316. {
  317. struct threshold_block *b = to_block(kobj);
  318. struct threshold_attr *a = to_attr(attr);
  319. ssize_t ret;
  320. ret = a->store ? a->store(b, buf, count) : -EIO;
  321. return ret;
  322. }
  323. static struct sysfs_ops threshold_ops = {
  324. .show = show,
  325. .store = store,
  326. };
  327. static struct kobj_type threshold_ktype = {
  328. .sysfs_ops = &threshold_ops,
  329. .default_attrs = default_attrs,
  330. };
  331. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  332. unsigned int bank,
  333. unsigned int block,
  334. u32 address)
  335. {
  336. int err;
  337. u32 low, high;
  338. struct threshold_block *b = NULL;
  339. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  340. return 0;
  341. if (rdmsr_safe(address, &low, &high))
  342. return 0;
  343. if (!(high & MASK_VALID_HI)) {
  344. if (block)
  345. goto recurse;
  346. else
  347. return 0;
  348. }
  349. if (!(high & MASK_CNTP_HI) ||
  350. (high & MASK_LOCKED_HI))
  351. goto recurse;
  352. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  353. if (!b)
  354. return -ENOMEM;
  355. b->block = block;
  356. b->bank = bank;
  357. b->cpu = cpu;
  358. b->address = address;
  359. b->interrupt_enable = 0;
  360. b->threshold_limit = THRESHOLD_MAX;
  361. INIT_LIST_HEAD(&b->miscj);
  362. if (per_cpu(threshold_banks, cpu)[bank]->blocks)
  363. list_add(&b->miscj,
  364. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  365. else
  366. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  367. kobject_set_name(&b->kobj, "misc%i", block);
  368. b->kobj.parent = &per_cpu(threshold_banks, cpu)[bank]->kobj;
  369. b->kobj.ktype = &threshold_ktype;
  370. err = kobject_register(&b->kobj);
  371. if (err)
  372. goto out_free;
  373. recurse:
  374. if (!block) {
  375. address = (low & MASK_BLKPTR_LO) >> 21;
  376. if (!address)
  377. return 0;
  378. address += MCG_XBLK_ADDR;
  379. } else
  380. ++address;
  381. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  382. if (err)
  383. goto out_free;
  384. return err;
  385. out_free:
  386. if (b) {
  387. kobject_unregister(&b->kobj);
  388. kfree(b);
  389. }
  390. return err;
  391. }
  392. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  393. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  394. {
  395. int i, err = 0;
  396. struct threshold_bank *b = NULL;
  397. cpumask_t oldmask = CPU_MASK_NONE;
  398. char name[32];
  399. sprintf(name, "threshold_bank%i", bank);
  400. #ifdef CONFIG_SMP
  401. if (cpu_data[cpu].cpu_core_id && shared_bank[bank]) { /* symlink */
  402. i = first_cpu(cpu_core_map[cpu]);
  403. /* first core not up yet */
  404. if (cpu_data[i].cpu_core_id)
  405. goto out;
  406. /* already linked */
  407. if (per_cpu(threshold_banks, cpu)[bank])
  408. goto out;
  409. b = per_cpu(threshold_banks, i)[bank];
  410. if (!b)
  411. goto out;
  412. err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
  413. &b->kobj, name);
  414. if (err)
  415. goto out;
  416. b->cpus = cpu_core_map[cpu];
  417. per_cpu(threshold_banks, cpu)[bank] = b;
  418. goto out;
  419. }
  420. #endif
  421. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  422. if (!b) {
  423. err = -ENOMEM;
  424. goto out;
  425. }
  426. kobject_set_name(&b->kobj, "threshold_bank%i", bank);
  427. b->kobj.parent = &per_cpu(device_mce, cpu).kobj;
  428. #ifndef CONFIG_SMP
  429. b->cpus = CPU_MASK_ALL;
  430. #else
  431. b->cpus = cpu_core_map[cpu];
  432. #endif
  433. err = kobject_register(&b->kobj);
  434. if (err)
  435. goto out_free;
  436. per_cpu(threshold_banks, cpu)[bank] = b;
  437. oldmask = affinity_set(cpu);
  438. err = allocate_threshold_blocks(cpu, bank, 0,
  439. MSR_IA32_MC0_MISC + bank * 4);
  440. affinity_restore(oldmask);
  441. if (err)
  442. goto out_free;
  443. for_each_cpu_mask(i, b->cpus) {
  444. if (i == cpu)
  445. continue;
  446. err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
  447. &b->kobj, name);
  448. if (err)
  449. goto out;
  450. per_cpu(threshold_banks, i)[bank] = b;
  451. }
  452. goto out;
  453. out_free:
  454. per_cpu(threshold_banks, cpu)[bank] = NULL;
  455. kfree(b);
  456. out:
  457. return err;
  458. }
  459. /* create dir/files for all valid threshold banks */
  460. static __cpuinit int threshold_create_device(unsigned int cpu)
  461. {
  462. unsigned int bank;
  463. int err = 0;
  464. for (bank = 0; bank < NR_BANKS; ++bank) {
  465. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  466. continue;
  467. err = threshold_create_bank(cpu, bank);
  468. if (err)
  469. goto out;
  470. }
  471. out:
  472. return err;
  473. }
  474. /*
  475. * let's be hotplug friendly.
  476. * in case of multiple core processors, the first core always takes ownership
  477. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  478. */
  479. static void deallocate_threshold_block(unsigned int cpu,
  480. unsigned int bank)
  481. {
  482. struct threshold_block *pos = NULL;
  483. struct threshold_block *tmp = NULL;
  484. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  485. if (!head)
  486. return;
  487. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  488. kobject_unregister(&pos->kobj);
  489. list_del(&pos->miscj);
  490. kfree(pos);
  491. }
  492. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  493. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  494. }
  495. static void threshold_remove_bank(unsigned int cpu, int bank)
  496. {
  497. int i = 0;
  498. struct threshold_bank *b;
  499. char name[32];
  500. b = per_cpu(threshold_banks, cpu)[bank];
  501. if (!b)
  502. return;
  503. if (!b->blocks)
  504. goto free_out;
  505. sprintf(name, "threshold_bank%i", bank);
  506. #ifdef CONFIG_SMP
  507. /* sibling symlink */
  508. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  509. sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
  510. per_cpu(threshold_banks, cpu)[bank] = NULL;
  511. return;
  512. }
  513. #endif
  514. /* remove all sibling symlinks before unregistering */
  515. for_each_cpu_mask(i, b->cpus) {
  516. if (i == cpu)
  517. continue;
  518. sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
  519. per_cpu(threshold_banks, i)[bank] = NULL;
  520. }
  521. deallocate_threshold_block(cpu, bank);
  522. free_out:
  523. kobject_unregister(&b->kobj);
  524. kfree(b);
  525. per_cpu(threshold_banks, cpu)[bank] = NULL;
  526. }
  527. static void threshold_remove_device(unsigned int cpu)
  528. {
  529. unsigned int bank;
  530. for (bank = 0; bank < NR_BANKS; ++bank) {
  531. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  532. continue;
  533. threshold_remove_bank(cpu, bank);
  534. }
  535. }
  536. /* get notified when a cpu comes on/off */
  537. static int threshold_cpu_callback(struct notifier_block *nfb,
  538. unsigned long action, void *hcpu)
  539. {
  540. /* cpu was unsigned int to begin with */
  541. unsigned int cpu = (unsigned long)hcpu;
  542. if (cpu >= NR_CPUS)
  543. goto out;
  544. switch (action) {
  545. case CPU_ONLINE:
  546. threshold_create_device(cpu);
  547. break;
  548. case CPU_DEAD:
  549. threshold_remove_device(cpu);
  550. break;
  551. default:
  552. break;
  553. }
  554. out:
  555. return NOTIFY_OK;
  556. }
  557. static struct notifier_block threshold_cpu_notifier = {
  558. .notifier_call = threshold_cpu_callback,
  559. };
  560. static __init int threshold_init_device(void)
  561. {
  562. unsigned lcpu = 0;
  563. /* to hit CPUs online before the notifier is up */
  564. for_each_online_cpu(lcpu) {
  565. int err = threshold_create_device(lcpu);
  566. if (err)
  567. return err;
  568. }
  569. register_hotcpu_notifier(&threshold_cpu_notifier);
  570. return 0;
  571. }
  572. device_initcall(threshold_init_device);