cputable.c 63 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. struct cpu_spec* cur_cpu_spec = NULL;
  22. EXPORT_SYMBOL(cur_cpu_spec);
  23. /* The platform string corresponding to the real PVR */
  24. const char *powerpc_base_platform;
  25. /* NOTE:
  26. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  27. * the responsibility of the appropriate CPU save/restore functions to
  28. * eventually copy these settings over. Those save/restore aren't yet
  29. * part of the cputable though. That has to be fixed for both ppc32
  30. * and ppc64
  31. */
  32. #ifdef CONFIG_PPC32
  33. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  46. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  55. #endif /* CONFIG_PPC32 */
  56. #ifdef CONFIG_PPC64
  57. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  58. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  60. extern void __restore_cpu_pa6t(void);
  61. extern void __restore_cpu_ppc970(void);
  62. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  63. extern void __restore_cpu_power7(void);
  64. #endif /* CONFIG_PPC64 */
  65. #if defined(CONFIG_E500)
  66. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_e5500(void);
  68. #endif /* CONFIG_E500 */
  69. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  70. * ones as well...
  71. */
  72. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  73. PPC_FEATURE_HAS_MMU)
  74. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  75. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  76. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  77. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  78. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  79. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  80. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  81. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  82. PPC_FEATURE_TRUE_LE | \
  83. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  84. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  85. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  86. PPC_FEATURE_TRUE_LE | \
  87. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  88. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  89. PPC_FEATURE_TRUE_LE | \
  90. PPC_FEATURE_HAS_ALTIVEC_COMP)
  91. #ifdef CONFIG_PPC_BOOK3E_64
  92. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  93. #else
  94. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  95. PPC_FEATURE_BOOKE)
  96. #endif
  97. static struct cpu_spec __initdata cpu_specs[] = {
  98. #ifdef CONFIG_PPC_BOOK3S_64
  99. { /* Power3 */
  100. .pvr_mask = 0xffff0000,
  101. .pvr_value = 0x00400000,
  102. .cpu_name = "POWER3 (630)",
  103. .cpu_features = CPU_FTRS_POWER3,
  104. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  105. .mmu_features = MMU_FTR_HPTE_TABLE,
  106. .icache_bsize = 128,
  107. .dcache_bsize = 128,
  108. .num_pmcs = 8,
  109. .pmc_type = PPC_PMC_IBM,
  110. .oprofile_cpu_type = "ppc64/power3",
  111. .oprofile_type = PPC_OPROFILE_RS64,
  112. .platform = "power3",
  113. },
  114. { /* Power3+ */
  115. .pvr_mask = 0xffff0000,
  116. .pvr_value = 0x00410000,
  117. .cpu_name = "POWER3 (630+)",
  118. .cpu_features = CPU_FTRS_POWER3,
  119. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  120. .mmu_features = MMU_FTR_HPTE_TABLE,
  121. .icache_bsize = 128,
  122. .dcache_bsize = 128,
  123. .num_pmcs = 8,
  124. .pmc_type = PPC_PMC_IBM,
  125. .oprofile_cpu_type = "ppc64/power3",
  126. .oprofile_type = PPC_OPROFILE_RS64,
  127. .platform = "power3",
  128. },
  129. { /* Northstar */
  130. .pvr_mask = 0xffff0000,
  131. .pvr_value = 0x00330000,
  132. .cpu_name = "RS64-II (northstar)",
  133. .cpu_features = CPU_FTRS_RS64,
  134. .cpu_user_features = COMMON_USER_PPC64,
  135. .mmu_features = MMU_FTR_HPTE_TABLE,
  136. .icache_bsize = 128,
  137. .dcache_bsize = 128,
  138. .num_pmcs = 8,
  139. .pmc_type = PPC_PMC_IBM,
  140. .oprofile_cpu_type = "ppc64/rs64",
  141. .oprofile_type = PPC_OPROFILE_RS64,
  142. .platform = "rs64",
  143. },
  144. { /* Pulsar */
  145. .pvr_mask = 0xffff0000,
  146. .pvr_value = 0x00340000,
  147. .cpu_name = "RS64-III (pulsar)",
  148. .cpu_features = CPU_FTRS_RS64,
  149. .cpu_user_features = COMMON_USER_PPC64,
  150. .mmu_features = MMU_FTR_HPTE_TABLE,
  151. .icache_bsize = 128,
  152. .dcache_bsize = 128,
  153. .num_pmcs = 8,
  154. .pmc_type = PPC_PMC_IBM,
  155. .oprofile_cpu_type = "ppc64/rs64",
  156. .oprofile_type = PPC_OPROFILE_RS64,
  157. .platform = "rs64",
  158. },
  159. { /* I-star */
  160. .pvr_mask = 0xffff0000,
  161. .pvr_value = 0x00360000,
  162. .cpu_name = "RS64-III (icestar)",
  163. .cpu_features = CPU_FTRS_RS64,
  164. .cpu_user_features = COMMON_USER_PPC64,
  165. .mmu_features = MMU_FTR_HPTE_TABLE,
  166. .icache_bsize = 128,
  167. .dcache_bsize = 128,
  168. .num_pmcs = 8,
  169. .pmc_type = PPC_PMC_IBM,
  170. .oprofile_cpu_type = "ppc64/rs64",
  171. .oprofile_type = PPC_OPROFILE_RS64,
  172. .platform = "rs64",
  173. },
  174. { /* S-star */
  175. .pvr_mask = 0xffff0000,
  176. .pvr_value = 0x00370000,
  177. .cpu_name = "RS64-IV (sstar)",
  178. .cpu_features = CPU_FTRS_RS64,
  179. .cpu_user_features = COMMON_USER_PPC64,
  180. .mmu_features = MMU_FTR_HPTE_TABLE,
  181. .icache_bsize = 128,
  182. .dcache_bsize = 128,
  183. .num_pmcs = 8,
  184. .pmc_type = PPC_PMC_IBM,
  185. .oprofile_cpu_type = "ppc64/rs64",
  186. .oprofile_type = PPC_OPROFILE_RS64,
  187. .platform = "rs64",
  188. },
  189. { /* Power4 */
  190. .pvr_mask = 0xffff0000,
  191. .pvr_value = 0x00350000,
  192. .cpu_name = "POWER4 (gp)",
  193. .cpu_features = CPU_FTRS_POWER4,
  194. .cpu_user_features = COMMON_USER_POWER4,
  195. .mmu_features = MMU_FTR_HPTE_TABLE,
  196. .icache_bsize = 128,
  197. .dcache_bsize = 128,
  198. .num_pmcs = 8,
  199. .pmc_type = PPC_PMC_IBM,
  200. .oprofile_cpu_type = "ppc64/power4",
  201. .oprofile_type = PPC_OPROFILE_POWER4,
  202. .platform = "power4",
  203. },
  204. { /* Power4+ */
  205. .pvr_mask = 0xffff0000,
  206. .pvr_value = 0x00380000,
  207. .cpu_name = "POWER4+ (gq)",
  208. .cpu_features = CPU_FTRS_POWER4,
  209. .cpu_user_features = COMMON_USER_POWER4,
  210. .mmu_features = MMU_FTR_HPTE_TABLE,
  211. .icache_bsize = 128,
  212. .dcache_bsize = 128,
  213. .num_pmcs = 8,
  214. .pmc_type = PPC_PMC_IBM,
  215. .oprofile_cpu_type = "ppc64/power4",
  216. .oprofile_type = PPC_OPROFILE_POWER4,
  217. .platform = "power4",
  218. },
  219. { /* PPC970 */
  220. .pvr_mask = 0xffff0000,
  221. .pvr_value = 0x00390000,
  222. .cpu_name = "PPC970",
  223. .cpu_features = CPU_FTRS_PPC970,
  224. .cpu_user_features = COMMON_USER_POWER4 |
  225. PPC_FEATURE_HAS_ALTIVEC_COMP,
  226. .mmu_features = MMU_FTR_HPTE_TABLE,
  227. .icache_bsize = 128,
  228. .dcache_bsize = 128,
  229. .num_pmcs = 8,
  230. .pmc_type = PPC_PMC_IBM,
  231. .cpu_setup = __setup_cpu_ppc970,
  232. .cpu_restore = __restore_cpu_ppc970,
  233. .oprofile_cpu_type = "ppc64/970",
  234. .oprofile_type = PPC_OPROFILE_POWER4,
  235. .platform = "ppc970",
  236. },
  237. { /* PPC970FX */
  238. .pvr_mask = 0xffff0000,
  239. .pvr_value = 0x003c0000,
  240. .cpu_name = "PPC970FX",
  241. .cpu_features = CPU_FTRS_PPC970,
  242. .cpu_user_features = COMMON_USER_POWER4 |
  243. PPC_FEATURE_HAS_ALTIVEC_COMP,
  244. .mmu_features = MMU_FTR_HPTE_TABLE,
  245. .icache_bsize = 128,
  246. .dcache_bsize = 128,
  247. .num_pmcs = 8,
  248. .pmc_type = PPC_PMC_IBM,
  249. .cpu_setup = __setup_cpu_ppc970,
  250. .cpu_restore = __restore_cpu_ppc970,
  251. .oprofile_cpu_type = "ppc64/970",
  252. .oprofile_type = PPC_OPROFILE_POWER4,
  253. .platform = "ppc970",
  254. },
  255. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  256. .pvr_mask = 0xffffffff,
  257. .pvr_value = 0x00440100,
  258. .cpu_name = "PPC970MP",
  259. .cpu_features = CPU_FTRS_PPC970,
  260. .cpu_user_features = COMMON_USER_POWER4 |
  261. PPC_FEATURE_HAS_ALTIVEC_COMP,
  262. .mmu_features = MMU_FTR_HPTE_TABLE,
  263. .icache_bsize = 128,
  264. .dcache_bsize = 128,
  265. .num_pmcs = 8,
  266. .pmc_type = PPC_PMC_IBM,
  267. .cpu_setup = __setup_cpu_ppc970,
  268. .cpu_restore = __restore_cpu_ppc970,
  269. .oprofile_cpu_type = "ppc64/970MP",
  270. .oprofile_type = PPC_OPROFILE_POWER4,
  271. .platform = "ppc970",
  272. },
  273. { /* PPC970MP */
  274. .pvr_mask = 0xffff0000,
  275. .pvr_value = 0x00440000,
  276. .cpu_name = "PPC970MP",
  277. .cpu_features = CPU_FTRS_PPC970,
  278. .cpu_user_features = COMMON_USER_POWER4 |
  279. PPC_FEATURE_HAS_ALTIVEC_COMP,
  280. .mmu_features = MMU_FTR_HPTE_TABLE,
  281. .icache_bsize = 128,
  282. .dcache_bsize = 128,
  283. .num_pmcs = 8,
  284. .pmc_type = PPC_PMC_IBM,
  285. .cpu_setup = __setup_cpu_ppc970MP,
  286. .cpu_restore = __restore_cpu_ppc970,
  287. .oprofile_cpu_type = "ppc64/970MP",
  288. .oprofile_type = PPC_OPROFILE_POWER4,
  289. .platform = "ppc970",
  290. },
  291. { /* PPC970GX */
  292. .pvr_mask = 0xffff0000,
  293. .pvr_value = 0x00450000,
  294. .cpu_name = "PPC970GX",
  295. .cpu_features = CPU_FTRS_PPC970,
  296. .cpu_user_features = COMMON_USER_POWER4 |
  297. PPC_FEATURE_HAS_ALTIVEC_COMP,
  298. .mmu_features = MMU_FTR_HPTE_TABLE,
  299. .icache_bsize = 128,
  300. .dcache_bsize = 128,
  301. .num_pmcs = 8,
  302. .pmc_type = PPC_PMC_IBM,
  303. .cpu_setup = __setup_cpu_ppc970,
  304. .oprofile_cpu_type = "ppc64/970",
  305. .oprofile_type = PPC_OPROFILE_POWER4,
  306. .platform = "ppc970",
  307. },
  308. { /* Power5 GR */
  309. .pvr_mask = 0xffff0000,
  310. .pvr_value = 0x003a0000,
  311. .cpu_name = "POWER5 (gr)",
  312. .cpu_features = CPU_FTRS_POWER5,
  313. .cpu_user_features = COMMON_USER_POWER5,
  314. .mmu_features = MMU_FTR_HPTE_TABLE,
  315. .icache_bsize = 128,
  316. .dcache_bsize = 128,
  317. .num_pmcs = 6,
  318. .pmc_type = PPC_PMC_IBM,
  319. .oprofile_cpu_type = "ppc64/power5",
  320. .oprofile_type = PPC_OPROFILE_POWER4,
  321. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  322. * and above but only works on POWER5 and above
  323. */
  324. .oprofile_mmcra_sihv = MMCRA_SIHV,
  325. .oprofile_mmcra_sipr = MMCRA_SIPR,
  326. .platform = "power5",
  327. },
  328. { /* Power5++ */
  329. .pvr_mask = 0xffffff00,
  330. .pvr_value = 0x003b0300,
  331. .cpu_name = "POWER5+ (gs)",
  332. .cpu_features = CPU_FTRS_POWER5,
  333. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  334. .mmu_features = MMU_FTR_HPTE_TABLE,
  335. .icache_bsize = 128,
  336. .dcache_bsize = 128,
  337. .num_pmcs = 6,
  338. .oprofile_cpu_type = "ppc64/power5++",
  339. .oprofile_type = PPC_OPROFILE_POWER4,
  340. .oprofile_mmcra_sihv = MMCRA_SIHV,
  341. .oprofile_mmcra_sipr = MMCRA_SIPR,
  342. .platform = "power5+",
  343. },
  344. { /* Power5 GS */
  345. .pvr_mask = 0xffff0000,
  346. .pvr_value = 0x003b0000,
  347. .cpu_name = "POWER5+ (gs)",
  348. .cpu_features = CPU_FTRS_POWER5,
  349. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  350. .mmu_features = MMU_FTR_HPTE_TABLE,
  351. .icache_bsize = 128,
  352. .dcache_bsize = 128,
  353. .num_pmcs = 6,
  354. .pmc_type = PPC_PMC_IBM,
  355. .oprofile_cpu_type = "ppc64/power5+",
  356. .oprofile_type = PPC_OPROFILE_POWER4,
  357. .oprofile_mmcra_sihv = MMCRA_SIHV,
  358. .oprofile_mmcra_sipr = MMCRA_SIPR,
  359. .platform = "power5+",
  360. },
  361. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  362. .pvr_mask = 0xffffffff,
  363. .pvr_value = 0x0f000001,
  364. .cpu_name = "POWER5+",
  365. .cpu_features = CPU_FTRS_POWER5,
  366. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  367. .mmu_features = MMU_FTR_HPTE_TABLE,
  368. .icache_bsize = 128,
  369. .dcache_bsize = 128,
  370. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  371. .oprofile_type = PPC_OPROFILE_POWER4,
  372. .platform = "power5+",
  373. },
  374. { /* Power6 */
  375. .pvr_mask = 0xffff0000,
  376. .pvr_value = 0x003e0000,
  377. .cpu_name = "POWER6 (raw)",
  378. .cpu_features = CPU_FTRS_POWER6,
  379. .cpu_user_features = COMMON_USER_POWER6 |
  380. PPC_FEATURE_POWER6_EXT,
  381. .mmu_features = MMU_FTR_HPTE_TABLE,
  382. .icache_bsize = 128,
  383. .dcache_bsize = 128,
  384. .num_pmcs = 6,
  385. .pmc_type = PPC_PMC_IBM,
  386. .oprofile_cpu_type = "ppc64/power6",
  387. .oprofile_type = PPC_OPROFILE_POWER4,
  388. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  389. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  390. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  391. POWER6_MMCRA_OTHER,
  392. .platform = "power6x",
  393. },
  394. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  395. .pvr_mask = 0xffffffff,
  396. .pvr_value = 0x0f000002,
  397. .cpu_name = "POWER6 (architected)",
  398. .cpu_features = CPU_FTRS_POWER6,
  399. .cpu_user_features = COMMON_USER_POWER6,
  400. .mmu_features = MMU_FTR_HPTE_TABLE,
  401. .icache_bsize = 128,
  402. .dcache_bsize = 128,
  403. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  404. .oprofile_type = PPC_OPROFILE_POWER4,
  405. .platform = "power6",
  406. },
  407. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  408. .pvr_mask = 0xffffffff,
  409. .pvr_value = 0x0f000003,
  410. .cpu_name = "POWER7 (architected)",
  411. .cpu_features = CPU_FTRS_POWER7,
  412. .cpu_user_features = COMMON_USER_POWER7,
  413. .mmu_features = MMU_FTR_HPTE_TABLE |
  414. MMU_FTR_TLBIE_206,
  415. .icache_bsize = 128,
  416. .dcache_bsize = 128,
  417. .oprofile_type = PPC_OPROFILE_POWER4,
  418. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  419. .cpu_setup = __setup_cpu_power7,
  420. .cpu_restore = __restore_cpu_power7,
  421. .platform = "power7",
  422. },
  423. { /* Power7 */
  424. .pvr_mask = 0xffff0000,
  425. .pvr_value = 0x003f0000,
  426. .cpu_name = "POWER7 (raw)",
  427. .cpu_features = CPU_FTRS_POWER7,
  428. .cpu_user_features = COMMON_USER_POWER7,
  429. .mmu_features = MMU_FTR_HPTE_TABLE |
  430. MMU_FTR_TLBIE_206,
  431. .icache_bsize = 128,
  432. .dcache_bsize = 128,
  433. .num_pmcs = 6,
  434. .pmc_type = PPC_PMC_IBM,
  435. .oprofile_cpu_type = "ppc64/power7",
  436. .oprofile_type = PPC_OPROFILE_POWER4,
  437. .cpu_setup = __setup_cpu_power7,
  438. .cpu_restore = __restore_cpu_power7,
  439. .platform = "power7",
  440. },
  441. { /* Power7+ */
  442. .pvr_mask = 0xffff0000,
  443. .pvr_value = 0x004A0000,
  444. .cpu_name = "POWER7+ (raw)",
  445. .cpu_features = CPU_FTRS_POWER7,
  446. .cpu_user_features = COMMON_USER_POWER7,
  447. .mmu_features = MMU_FTR_HPTE_TABLE |
  448. MMU_FTR_TLBIE_206,
  449. .icache_bsize = 128,
  450. .dcache_bsize = 128,
  451. .num_pmcs = 6,
  452. .pmc_type = PPC_PMC_IBM,
  453. .oprofile_cpu_type = "ppc64/power7",
  454. .oprofile_type = PPC_OPROFILE_POWER4,
  455. .cpu_setup = __setup_cpu_power7,
  456. .cpu_restore = __restore_cpu_power7,
  457. .platform = "power7+",
  458. },
  459. { /* Cell Broadband Engine */
  460. .pvr_mask = 0xffff0000,
  461. .pvr_value = 0x00700000,
  462. .cpu_name = "Cell Broadband Engine",
  463. .cpu_features = CPU_FTRS_CELL,
  464. .cpu_user_features = COMMON_USER_PPC64 |
  465. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  466. PPC_FEATURE_SMT,
  467. .mmu_features = MMU_FTR_HPTE_TABLE,
  468. .icache_bsize = 128,
  469. .dcache_bsize = 128,
  470. .num_pmcs = 4,
  471. .pmc_type = PPC_PMC_IBM,
  472. .oprofile_cpu_type = "ppc64/cell-be",
  473. .oprofile_type = PPC_OPROFILE_CELL,
  474. .platform = "ppc-cell-be",
  475. },
  476. { /* PA Semi PA6T */
  477. .pvr_mask = 0x7fff0000,
  478. .pvr_value = 0x00900000,
  479. .cpu_name = "PA6T",
  480. .cpu_features = CPU_FTRS_PA6T,
  481. .cpu_user_features = COMMON_USER_PA6T,
  482. .mmu_features = MMU_FTR_HPTE_TABLE,
  483. .icache_bsize = 64,
  484. .dcache_bsize = 64,
  485. .num_pmcs = 6,
  486. .pmc_type = PPC_PMC_PA6T,
  487. .cpu_setup = __setup_cpu_pa6t,
  488. .cpu_restore = __restore_cpu_pa6t,
  489. .oprofile_cpu_type = "ppc64/pa6t",
  490. .oprofile_type = PPC_OPROFILE_PA6T,
  491. .platform = "pa6t",
  492. },
  493. { /* default match */
  494. .pvr_mask = 0x00000000,
  495. .pvr_value = 0x00000000,
  496. .cpu_name = "POWER4 (compatible)",
  497. .cpu_features = CPU_FTRS_COMPATIBLE,
  498. .cpu_user_features = COMMON_USER_PPC64,
  499. .mmu_features = MMU_FTR_HPTE_TABLE,
  500. .icache_bsize = 128,
  501. .dcache_bsize = 128,
  502. .num_pmcs = 6,
  503. .pmc_type = PPC_PMC_IBM,
  504. .platform = "power4",
  505. }
  506. #endif /* CONFIG_PPC_BOOK3S_64 */
  507. #ifdef CONFIG_PPC32
  508. #if CLASSIC_PPC
  509. { /* 601 */
  510. .pvr_mask = 0xffff0000,
  511. .pvr_value = 0x00010000,
  512. .cpu_name = "601",
  513. .cpu_features = CPU_FTRS_PPC601,
  514. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  515. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  516. .mmu_features = MMU_FTR_HPTE_TABLE,
  517. .icache_bsize = 32,
  518. .dcache_bsize = 32,
  519. .machine_check = machine_check_generic,
  520. .platform = "ppc601",
  521. },
  522. { /* 603 */
  523. .pvr_mask = 0xffff0000,
  524. .pvr_value = 0x00030000,
  525. .cpu_name = "603",
  526. .cpu_features = CPU_FTRS_603,
  527. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  528. .mmu_features = 0,
  529. .icache_bsize = 32,
  530. .dcache_bsize = 32,
  531. .cpu_setup = __setup_cpu_603,
  532. .machine_check = machine_check_generic,
  533. .platform = "ppc603",
  534. },
  535. { /* 603e */
  536. .pvr_mask = 0xffff0000,
  537. .pvr_value = 0x00060000,
  538. .cpu_name = "603e",
  539. .cpu_features = CPU_FTRS_603,
  540. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  541. .mmu_features = 0,
  542. .icache_bsize = 32,
  543. .dcache_bsize = 32,
  544. .cpu_setup = __setup_cpu_603,
  545. .machine_check = machine_check_generic,
  546. .platform = "ppc603",
  547. },
  548. { /* 603ev */
  549. .pvr_mask = 0xffff0000,
  550. .pvr_value = 0x00070000,
  551. .cpu_name = "603ev",
  552. .cpu_features = CPU_FTRS_603,
  553. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  554. .mmu_features = 0,
  555. .icache_bsize = 32,
  556. .dcache_bsize = 32,
  557. .cpu_setup = __setup_cpu_603,
  558. .machine_check = machine_check_generic,
  559. .platform = "ppc603",
  560. },
  561. { /* 604 */
  562. .pvr_mask = 0xffff0000,
  563. .pvr_value = 0x00040000,
  564. .cpu_name = "604",
  565. .cpu_features = CPU_FTRS_604,
  566. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  567. .mmu_features = MMU_FTR_HPTE_TABLE,
  568. .icache_bsize = 32,
  569. .dcache_bsize = 32,
  570. .num_pmcs = 2,
  571. .cpu_setup = __setup_cpu_604,
  572. .machine_check = machine_check_generic,
  573. .platform = "ppc604",
  574. },
  575. { /* 604e */
  576. .pvr_mask = 0xfffff000,
  577. .pvr_value = 0x00090000,
  578. .cpu_name = "604e",
  579. .cpu_features = CPU_FTRS_604,
  580. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  581. .mmu_features = MMU_FTR_HPTE_TABLE,
  582. .icache_bsize = 32,
  583. .dcache_bsize = 32,
  584. .num_pmcs = 4,
  585. .cpu_setup = __setup_cpu_604,
  586. .machine_check = machine_check_generic,
  587. .platform = "ppc604",
  588. },
  589. { /* 604r */
  590. .pvr_mask = 0xffff0000,
  591. .pvr_value = 0x00090000,
  592. .cpu_name = "604r",
  593. .cpu_features = CPU_FTRS_604,
  594. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  595. .mmu_features = MMU_FTR_HPTE_TABLE,
  596. .icache_bsize = 32,
  597. .dcache_bsize = 32,
  598. .num_pmcs = 4,
  599. .cpu_setup = __setup_cpu_604,
  600. .machine_check = machine_check_generic,
  601. .platform = "ppc604",
  602. },
  603. { /* 604ev */
  604. .pvr_mask = 0xffff0000,
  605. .pvr_value = 0x000a0000,
  606. .cpu_name = "604ev",
  607. .cpu_features = CPU_FTRS_604,
  608. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  609. .mmu_features = MMU_FTR_HPTE_TABLE,
  610. .icache_bsize = 32,
  611. .dcache_bsize = 32,
  612. .num_pmcs = 4,
  613. .cpu_setup = __setup_cpu_604,
  614. .machine_check = machine_check_generic,
  615. .platform = "ppc604",
  616. },
  617. { /* 740/750 (0x4202, don't support TAU ?) */
  618. .pvr_mask = 0xffffffff,
  619. .pvr_value = 0x00084202,
  620. .cpu_name = "740/750",
  621. .cpu_features = CPU_FTRS_740_NOTAU,
  622. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  623. .mmu_features = MMU_FTR_HPTE_TABLE,
  624. .icache_bsize = 32,
  625. .dcache_bsize = 32,
  626. .num_pmcs = 4,
  627. .cpu_setup = __setup_cpu_750,
  628. .machine_check = machine_check_generic,
  629. .platform = "ppc750",
  630. },
  631. { /* 750CX (80100 and 8010x?) */
  632. .pvr_mask = 0xfffffff0,
  633. .pvr_value = 0x00080100,
  634. .cpu_name = "750CX",
  635. .cpu_features = CPU_FTRS_750,
  636. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  637. .mmu_features = MMU_FTR_HPTE_TABLE,
  638. .icache_bsize = 32,
  639. .dcache_bsize = 32,
  640. .num_pmcs = 4,
  641. .cpu_setup = __setup_cpu_750cx,
  642. .machine_check = machine_check_generic,
  643. .platform = "ppc750",
  644. },
  645. { /* 750CX (82201 and 82202) */
  646. .pvr_mask = 0xfffffff0,
  647. .pvr_value = 0x00082200,
  648. .cpu_name = "750CX",
  649. .cpu_features = CPU_FTRS_750,
  650. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  651. .mmu_features = MMU_FTR_HPTE_TABLE,
  652. .icache_bsize = 32,
  653. .dcache_bsize = 32,
  654. .num_pmcs = 4,
  655. .pmc_type = PPC_PMC_IBM,
  656. .cpu_setup = __setup_cpu_750cx,
  657. .machine_check = machine_check_generic,
  658. .platform = "ppc750",
  659. },
  660. { /* 750CXe (82214) */
  661. .pvr_mask = 0xfffffff0,
  662. .pvr_value = 0x00082210,
  663. .cpu_name = "750CXe",
  664. .cpu_features = CPU_FTRS_750,
  665. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  666. .mmu_features = MMU_FTR_HPTE_TABLE,
  667. .icache_bsize = 32,
  668. .dcache_bsize = 32,
  669. .num_pmcs = 4,
  670. .pmc_type = PPC_PMC_IBM,
  671. .cpu_setup = __setup_cpu_750cx,
  672. .machine_check = machine_check_generic,
  673. .platform = "ppc750",
  674. },
  675. { /* 750CXe "Gekko" (83214) */
  676. .pvr_mask = 0xffffffff,
  677. .pvr_value = 0x00083214,
  678. .cpu_name = "750CXe",
  679. .cpu_features = CPU_FTRS_750,
  680. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  681. .mmu_features = MMU_FTR_HPTE_TABLE,
  682. .icache_bsize = 32,
  683. .dcache_bsize = 32,
  684. .num_pmcs = 4,
  685. .pmc_type = PPC_PMC_IBM,
  686. .cpu_setup = __setup_cpu_750cx,
  687. .machine_check = machine_check_generic,
  688. .platform = "ppc750",
  689. },
  690. { /* 750CL (and "Broadway") */
  691. .pvr_mask = 0xfffff0e0,
  692. .pvr_value = 0x00087000,
  693. .cpu_name = "750CL",
  694. .cpu_features = CPU_FTRS_750CL,
  695. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  696. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  697. .icache_bsize = 32,
  698. .dcache_bsize = 32,
  699. .num_pmcs = 4,
  700. .pmc_type = PPC_PMC_IBM,
  701. .cpu_setup = __setup_cpu_750,
  702. .machine_check = machine_check_generic,
  703. .platform = "ppc750",
  704. .oprofile_cpu_type = "ppc/750",
  705. .oprofile_type = PPC_OPROFILE_G4,
  706. },
  707. { /* 745/755 */
  708. .pvr_mask = 0xfffff000,
  709. .pvr_value = 0x00083000,
  710. .cpu_name = "745/755",
  711. .cpu_features = CPU_FTRS_750,
  712. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  713. .mmu_features = MMU_FTR_HPTE_TABLE,
  714. .icache_bsize = 32,
  715. .dcache_bsize = 32,
  716. .num_pmcs = 4,
  717. .pmc_type = PPC_PMC_IBM,
  718. .cpu_setup = __setup_cpu_750,
  719. .machine_check = machine_check_generic,
  720. .platform = "ppc750",
  721. },
  722. { /* 750FX rev 1.x */
  723. .pvr_mask = 0xffffff00,
  724. .pvr_value = 0x70000100,
  725. .cpu_name = "750FX",
  726. .cpu_features = CPU_FTRS_750FX1,
  727. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  728. .mmu_features = MMU_FTR_HPTE_TABLE,
  729. .icache_bsize = 32,
  730. .dcache_bsize = 32,
  731. .num_pmcs = 4,
  732. .pmc_type = PPC_PMC_IBM,
  733. .cpu_setup = __setup_cpu_750,
  734. .machine_check = machine_check_generic,
  735. .platform = "ppc750",
  736. .oprofile_cpu_type = "ppc/750",
  737. .oprofile_type = PPC_OPROFILE_G4,
  738. },
  739. { /* 750FX rev 2.0 must disable HID0[DPM] */
  740. .pvr_mask = 0xffffffff,
  741. .pvr_value = 0x70000200,
  742. .cpu_name = "750FX",
  743. .cpu_features = CPU_FTRS_750FX2,
  744. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  745. .mmu_features = MMU_FTR_HPTE_TABLE,
  746. .icache_bsize = 32,
  747. .dcache_bsize = 32,
  748. .num_pmcs = 4,
  749. .pmc_type = PPC_PMC_IBM,
  750. .cpu_setup = __setup_cpu_750,
  751. .machine_check = machine_check_generic,
  752. .platform = "ppc750",
  753. .oprofile_cpu_type = "ppc/750",
  754. .oprofile_type = PPC_OPROFILE_G4,
  755. },
  756. { /* 750FX (All revs except 2.0) */
  757. .pvr_mask = 0xffff0000,
  758. .pvr_value = 0x70000000,
  759. .cpu_name = "750FX",
  760. .cpu_features = CPU_FTRS_750FX,
  761. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  762. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  763. .icache_bsize = 32,
  764. .dcache_bsize = 32,
  765. .num_pmcs = 4,
  766. .pmc_type = PPC_PMC_IBM,
  767. .cpu_setup = __setup_cpu_750fx,
  768. .machine_check = machine_check_generic,
  769. .platform = "ppc750",
  770. .oprofile_cpu_type = "ppc/750",
  771. .oprofile_type = PPC_OPROFILE_G4,
  772. },
  773. { /* 750GX */
  774. .pvr_mask = 0xffff0000,
  775. .pvr_value = 0x70020000,
  776. .cpu_name = "750GX",
  777. .cpu_features = CPU_FTRS_750GX,
  778. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  779. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  780. .icache_bsize = 32,
  781. .dcache_bsize = 32,
  782. .num_pmcs = 4,
  783. .pmc_type = PPC_PMC_IBM,
  784. .cpu_setup = __setup_cpu_750fx,
  785. .machine_check = machine_check_generic,
  786. .platform = "ppc750",
  787. .oprofile_cpu_type = "ppc/750",
  788. .oprofile_type = PPC_OPROFILE_G4,
  789. },
  790. { /* 740/750 (L2CR bit need fixup for 740) */
  791. .pvr_mask = 0xffff0000,
  792. .pvr_value = 0x00080000,
  793. .cpu_name = "740/750",
  794. .cpu_features = CPU_FTRS_740,
  795. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  796. .mmu_features = MMU_FTR_HPTE_TABLE,
  797. .icache_bsize = 32,
  798. .dcache_bsize = 32,
  799. .num_pmcs = 4,
  800. .pmc_type = PPC_PMC_IBM,
  801. .cpu_setup = __setup_cpu_750,
  802. .machine_check = machine_check_generic,
  803. .platform = "ppc750",
  804. },
  805. { /* 7400 rev 1.1 ? (no TAU) */
  806. .pvr_mask = 0xffffffff,
  807. .pvr_value = 0x000c1101,
  808. .cpu_name = "7400 (1.1)",
  809. .cpu_features = CPU_FTRS_7400_NOTAU,
  810. .cpu_user_features = COMMON_USER |
  811. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  812. .mmu_features = MMU_FTR_HPTE_TABLE,
  813. .icache_bsize = 32,
  814. .dcache_bsize = 32,
  815. .num_pmcs = 4,
  816. .pmc_type = PPC_PMC_G4,
  817. .cpu_setup = __setup_cpu_7400,
  818. .machine_check = machine_check_generic,
  819. .platform = "ppc7400",
  820. },
  821. { /* 7400 */
  822. .pvr_mask = 0xffff0000,
  823. .pvr_value = 0x000c0000,
  824. .cpu_name = "7400",
  825. .cpu_features = CPU_FTRS_7400,
  826. .cpu_user_features = COMMON_USER |
  827. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  828. .mmu_features = MMU_FTR_HPTE_TABLE,
  829. .icache_bsize = 32,
  830. .dcache_bsize = 32,
  831. .num_pmcs = 4,
  832. .pmc_type = PPC_PMC_G4,
  833. .cpu_setup = __setup_cpu_7400,
  834. .machine_check = machine_check_generic,
  835. .platform = "ppc7400",
  836. },
  837. { /* 7410 */
  838. .pvr_mask = 0xffff0000,
  839. .pvr_value = 0x800c0000,
  840. .cpu_name = "7410",
  841. .cpu_features = CPU_FTRS_7400,
  842. .cpu_user_features = COMMON_USER |
  843. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  844. .mmu_features = MMU_FTR_HPTE_TABLE,
  845. .icache_bsize = 32,
  846. .dcache_bsize = 32,
  847. .num_pmcs = 4,
  848. .pmc_type = PPC_PMC_G4,
  849. .cpu_setup = __setup_cpu_7410,
  850. .machine_check = machine_check_generic,
  851. .platform = "ppc7400",
  852. },
  853. { /* 7450 2.0 - no doze/nap */
  854. .pvr_mask = 0xffffffff,
  855. .pvr_value = 0x80000200,
  856. .cpu_name = "7450",
  857. .cpu_features = CPU_FTRS_7450_20,
  858. .cpu_user_features = COMMON_USER |
  859. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  860. .mmu_features = MMU_FTR_HPTE_TABLE,
  861. .icache_bsize = 32,
  862. .dcache_bsize = 32,
  863. .num_pmcs = 6,
  864. .pmc_type = PPC_PMC_G4,
  865. .cpu_setup = __setup_cpu_745x,
  866. .oprofile_cpu_type = "ppc/7450",
  867. .oprofile_type = PPC_OPROFILE_G4,
  868. .machine_check = machine_check_generic,
  869. .platform = "ppc7450",
  870. },
  871. { /* 7450 2.1 */
  872. .pvr_mask = 0xffffffff,
  873. .pvr_value = 0x80000201,
  874. .cpu_name = "7450",
  875. .cpu_features = CPU_FTRS_7450_21,
  876. .cpu_user_features = COMMON_USER |
  877. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  878. .mmu_features = MMU_FTR_HPTE_TABLE,
  879. .icache_bsize = 32,
  880. .dcache_bsize = 32,
  881. .num_pmcs = 6,
  882. .pmc_type = PPC_PMC_G4,
  883. .cpu_setup = __setup_cpu_745x,
  884. .oprofile_cpu_type = "ppc/7450",
  885. .oprofile_type = PPC_OPROFILE_G4,
  886. .machine_check = machine_check_generic,
  887. .platform = "ppc7450",
  888. },
  889. { /* 7450 2.3 and newer */
  890. .pvr_mask = 0xffff0000,
  891. .pvr_value = 0x80000000,
  892. .cpu_name = "7450",
  893. .cpu_features = CPU_FTRS_7450_23,
  894. .cpu_user_features = COMMON_USER |
  895. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  896. .mmu_features = MMU_FTR_HPTE_TABLE,
  897. .icache_bsize = 32,
  898. .dcache_bsize = 32,
  899. .num_pmcs = 6,
  900. .pmc_type = PPC_PMC_G4,
  901. .cpu_setup = __setup_cpu_745x,
  902. .oprofile_cpu_type = "ppc/7450",
  903. .oprofile_type = PPC_OPROFILE_G4,
  904. .machine_check = machine_check_generic,
  905. .platform = "ppc7450",
  906. },
  907. { /* 7455 rev 1.x */
  908. .pvr_mask = 0xffffff00,
  909. .pvr_value = 0x80010100,
  910. .cpu_name = "7455",
  911. .cpu_features = CPU_FTRS_7455_1,
  912. .cpu_user_features = COMMON_USER |
  913. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  914. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  915. .icache_bsize = 32,
  916. .dcache_bsize = 32,
  917. .num_pmcs = 6,
  918. .pmc_type = PPC_PMC_G4,
  919. .cpu_setup = __setup_cpu_745x,
  920. .oprofile_cpu_type = "ppc/7450",
  921. .oprofile_type = PPC_OPROFILE_G4,
  922. .machine_check = machine_check_generic,
  923. .platform = "ppc7450",
  924. },
  925. { /* 7455 rev 2.0 */
  926. .pvr_mask = 0xffffffff,
  927. .pvr_value = 0x80010200,
  928. .cpu_name = "7455",
  929. .cpu_features = CPU_FTRS_7455_20,
  930. .cpu_user_features = COMMON_USER |
  931. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  932. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  933. .icache_bsize = 32,
  934. .dcache_bsize = 32,
  935. .num_pmcs = 6,
  936. .pmc_type = PPC_PMC_G4,
  937. .cpu_setup = __setup_cpu_745x,
  938. .oprofile_cpu_type = "ppc/7450",
  939. .oprofile_type = PPC_OPROFILE_G4,
  940. .machine_check = machine_check_generic,
  941. .platform = "ppc7450",
  942. },
  943. { /* 7455 others */
  944. .pvr_mask = 0xffff0000,
  945. .pvr_value = 0x80010000,
  946. .cpu_name = "7455",
  947. .cpu_features = CPU_FTRS_7455,
  948. .cpu_user_features = COMMON_USER |
  949. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  950. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  951. .icache_bsize = 32,
  952. .dcache_bsize = 32,
  953. .num_pmcs = 6,
  954. .pmc_type = PPC_PMC_G4,
  955. .cpu_setup = __setup_cpu_745x,
  956. .oprofile_cpu_type = "ppc/7450",
  957. .oprofile_type = PPC_OPROFILE_G4,
  958. .machine_check = machine_check_generic,
  959. .platform = "ppc7450",
  960. },
  961. { /* 7447/7457 Rev 1.0 */
  962. .pvr_mask = 0xffffffff,
  963. .pvr_value = 0x80020100,
  964. .cpu_name = "7447/7457",
  965. .cpu_features = CPU_FTRS_7447_10,
  966. .cpu_user_features = COMMON_USER |
  967. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  968. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  969. .icache_bsize = 32,
  970. .dcache_bsize = 32,
  971. .num_pmcs = 6,
  972. .pmc_type = PPC_PMC_G4,
  973. .cpu_setup = __setup_cpu_745x,
  974. .oprofile_cpu_type = "ppc/7450",
  975. .oprofile_type = PPC_OPROFILE_G4,
  976. .machine_check = machine_check_generic,
  977. .platform = "ppc7450",
  978. },
  979. { /* 7447/7457 Rev 1.1 */
  980. .pvr_mask = 0xffffffff,
  981. .pvr_value = 0x80020101,
  982. .cpu_name = "7447/7457",
  983. .cpu_features = CPU_FTRS_7447_10,
  984. .cpu_user_features = COMMON_USER |
  985. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  986. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  987. .icache_bsize = 32,
  988. .dcache_bsize = 32,
  989. .num_pmcs = 6,
  990. .pmc_type = PPC_PMC_G4,
  991. .cpu_setup = __setup_cpu_745x,
  992. .oprofile_cpu_type = "ppc/7450",
  993. .oprofile_type = PPC_OPROFILE_G4,
  994. .machine_check = machine_check_generic,
  995. .platform = "ppc7450",
  996. },
  997. { /* 7447/7457 Rev 1.2 and later */
  998. .pvr_mask = 0xffff0000,
  999. .pvr_value = 0x80020000,
  1000. .cpu_name = "7447/7457",
  1001. .cpu_features = CPU_FTRS_7447,
  1002. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1003. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1004. .icache_bsize = 32,
  1005. .dcache_bsize = 32,
  1006. .num_pmcs = 6,
  1007. .pmc_type = PPC_PMC_G4,
  1008. .cpu_setup = __setup_cpu_745x,
  1009. .oprofile_cpu_type = "ppc/7450",
  1010. .oprofile_type = PPC_OPROFILE_G4,
  1011. .machine_check = machine_check_generic,
  1012. .platform = "ppc7450",
  1013. },
  1014. { /* 7447A */
  1015. .pvr_mask = 0xffff0000,
  1016. .pvr_value = 0x80030000,
  1017. .cpu_name = "7447A",
  1018. .cpu_features = CPU_FTRS_7447A,
  1019. .cpu_user_features = COMMON_USER |
  1020. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1021. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1022. .icache_bsize = 32,
  1023. .dcache_bsize = 32,
  1024. .num_pmcs = 6,
  1025. .pmc_type = PPC_PMC_G4,
  1026. .cpu_setup = __setup_cpu_745x,
  1027. .oprofile_cpu_type = "ppc/7450",
  1028. .oprofile_type = PPC_OPROFILE_G4,
  1029. .machine_check = machine_check_generic,
  1030. .platform = "ppc7450",
  1031. },
  1032. { /* 7448 */
  1033. .pvr_mask = 0xffff0000,
  1034. .pvr_value = 0x80040000,
  1035. .cpu_name = "7448",
  1036. .cpu_features = CPU_FTRS_7448,
  1037. .cpu_user_features = COMMON_USER |
  1038. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1039. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1040. .icache_bsize = 32,
  1041. .dcache_bsize = 32,
  1042. .num_pmcs = 6,
  1043. .pmc_type = PPC_PMC_G4,
  1044. .cpu_setup = __setup_cpu_745x,
  1045. .oprofile_cpu_type = "ppc/7450",
  1046. .oprofile_type = PPC_OPROFILE_G4,
  1047. .machine_check = machine_check_generic,
  1048. .platform = "ppc7450",
  1049. },
  1050. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1051. .pvr_mask = 0x7fff0000,
  1052. .pvr_value = 0x00810000,
  1053. .cpu_name = "82xx",
  1054. .cpu_features = CPU_FTRS_82XX,
  1055. .cpu_user_features = COMMON_USER,
  1056. .mmu_features = 0,
  1057. .icache_bsize = 32,
  1058. .dcache_bsize = 32,
  1059. .cpu_setup = __setup_cpu_603,
  1060. .machine_check = machine_check_generic,
  1061. .platform = "ppc603",
  1062. },
  1063. { /* All G2_LE (603e core, plus some) have the same pvr */
  1064. .pvr_mask = 0x7fff0000,
  1065. .pvr_value = 0x00820000,
  1066. .cpu_name = "G2_LE",
  1067. .cpu_features = CPU_FTRS_G2_LE,
  1068. .cpu_user_features = COMMON_USER,
  1069. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1070. .icache_bsize = 32,
  1071. .dcache_bsize = 32,
  1072. .cpu_setup = __setup_cpu_603,
  1073. .machine_check = machine_check_generic,
  1074. .platform = "ppc603",
  1075. },
  1076. { /* e300c1 (a 603e core, plus some) on 83xx */
  1077. .pvr_mask = 0x7fff0000,
  1078. .pvr_value = 0x00830000,
  1079. .cpu_name = "e300c1",
  1080. .cpu_features = CPU_FTRS_E300,
  1081. .cpu_user_features = COMMON_USER,
  1082. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1083. .icache_bsize = 32,
  1084. .dcache_bsize = 32,
  1085. .cpu_setup = __setup_cpu_603,
  1086. .machine_check = machine_check_generic,
  1087. .platform = "ppc603",
  1088. },
  1089. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1090. .pvr_mask = 0x7fff0000,
  1091. .pvr_value = 0x00840000,
  1092. .cpu_name = "e300c2",
  1093. .cpu_features = CPU_FTRS_E300C2,
  1094. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1095. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1096. MMU_FTR_NEED_DTLB_SW_LRU,
  1097. .icache_bsize = 32,
  1098. .dcache_bsize = 32,
  1099. .cpu_setup = __setup_cpu_603,
  1100. .machine_check = machine_check_generic,
  1101. .platform = "ppc603",
  1102. },
  1103. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1104. .pvr_mask = 0x7fff0000,
  1105. .pvr_value = 0x00850000,
  1106. .cpu_name = "e300c3",
  1107. .cpu_features = CPU_FTRS_E300,
  1108. .cpu_user_features = COMMON_USER,
  1109. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1110. MMU_FTR_NEED_DTLB_SW_LRU,
  1111. .icache_bsize = 32,
  1112. .dcache_bsize = 32,
  1113. .cpu_setup = __setup_cpu_603,
  1114. .num_pmcs = 4,
  1115. .oprofile_cpu_type = "ppc/e300",
  1116. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1117. .platform = "ppc603",
  1118. },
  1119. { /* e300c4 (e300c1, plus one IU) */
  1120. .pvr_mask = 0x7fff0000,
  1121. .pvr_value = 0x00860000,
  1122. .cpu_name = "e300c4",
  1123. .cpu_features = CPU_FTRS_E300,
  1124. .cpu_user_features = COMMON_USER,
  1125. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1126. MMU_FTR_NEED_DTLB_SW_LRU,
  1127. .icache_bsize = 32,
  1128. .dcache_bsize = 32,
  1129. .cpu_setup = __setup_cpu_603,
  1130. .machine_check = machine_check_generic,
  1131. .num_pmcs = 4,
  1132. .oprofile_cpu_type = "ppc/e300",
  1133. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1134. .platform = "ppc603",
  1135. },
  1136. { /* default match, we assume split I/D cache & TB (non-601)... */
  1137. .pvr_mask = 0x00000000,
  1138. .pvr_value = 0x00000000,
  1139. .cpu_name = "(generic PPC)",
  1140. .cpu_features = CPU_FTRS_CLASSIC32,
  1141. .cpu_user_features = COMMON_USER,
  1142. .mmu_features = MMU_FTR_HPTE_TABLE,
  1143. .icache_bsize = 32,
  1144. .dcache_bsize = 32,
  1145. .machine_check = machine_check_generic,
  1146. .platform = "ppc603",
  1147. },
  1148. #endif /* CLASSIC_PPC */
  1149. #ifdef CONFIG_8xx
  1150. { /* 8xx */
  1151. .pvr_mask = 0xffff0000,
  1152. .pvr_value = 0x00500000,
  1153. .cpu_name = "8xx",
  1154. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1155. * if the 8xx code is there.... */
  1156. .cpu_features = CPU_FTRS_8XX,
  1157. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1158. .mmu_features = MMU_FTR_TYPE_8xx,
  1159. .icache_bsize = 16,
  1160. .dcache_bsize = 16,
  1161. .platform = "ppc823",
  1162. },
  1163. #endif /* CONFIG_8xx */
  1164. #ifdef CONFIG_40x
  1165. { /* 403GC */
  1166. .pvr_mask = 0xffffff00,
  1167. .pvr_value = 0x00200200,
  1168. .cpu_name = "403GC",
  1169. .cpu_features = CPU_FTRS_40X,
  1170. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1171. .mmu_features = MMU_FTR_TYPE_40x,
  1172. .icache_bsize = 16,
  1173. .dcache_bsize = 16,
  1174. .machine_check = machine_check_4xx,
  1175. .platform = "ppc403",
  1176. },
  1177. { /* 403GCX */
  1178. .pvr_mask = 0xffffff00,
  1179. .pvr_value = 0x00201400,
  1180. .cpu_name = "403GCX",
  1181. .cpu_features = CPU_FTRS_40X,
  1182. .cpu_user_features = PPC_FEATURE_32 |
  1183. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1184. .mmu_features = MMU_FTR_TYPE_40x,
  1185. .icache_bsize = 16,
  1186. .dcache_bsize = 16,
  1187. .machine_check = machine_check_4xx,
  1188. .platform = "ppc403",
  1189. },
  1190. { /* 403G ?? */
  1191. .pvr_mask = 0xffff0000,
  1192. .pvr_value = 0x00200000,
  1193. .cpu_name = "403G ??",
  1194. .cpu_features = CPU_FTRS_40X,
  1195. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1196. .mmu_features = MMU_FTR_TYPE_40x,
  1197. .icache_bsize = 16,
  1198. .dcache_bsize = 16,
  1199. .machine_check = machine_check_4xx,
  1200. .platform = "ppc403",
  1201. },
  1202. { /* 405GP */
  1203. .pvr_mask = 0xffff0000,
  1204. .pvr_value = 0x40110000,
  1205. .cpu_name = "405GP",
  1206. .cpu_features = CPU_FTRS_40X,
  1207. .cpu_user_features = PPC_FEATURE_32 |
  1208. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1209. .mmu_features = MMU_FTR_TYPE_40x,
  1210. .icache_bsize = 32,
  1211. .dcache_bsize = 32,
  1212. .machine_check = machine_check_4xx,
  1213. .platform = "ppc405",
  1214. },
  1215. { /* STB 03xxx */
  1216. .pvr_mask = 0xffff0000,
  1217. .pvr_value = 0x40130000,
  1218. .cpu_name = "STB03xxx",
  1219. .cpu_features = CPU_FTRS_40X,
  1220. .cpu_user_features = PPC_FEATURE_32 |
  1221. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1222. .mmu_features = MMU_FTR_TYPE_40x,
  1223. .icache_bsize = 32,
  1224. .dcache_bsize = 32,
  1225. .machine_check = machine_check_4xx,
  1226. .platform = "ppc405",
  1227. },
  1228. { /* STB 04xxx */
  1229. .pvr_mask = 0xffff0000,
  1230. .pvr_value = 0x41810000,
  1231. .cpu_name = "STB04xxx",
  1232. .cpu_features = CPU_FTRS_40X,
  1233. .cpu_user_features = PPC_FEATURE_32 |
  1234. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1235. .mmu_features = MMU_FTR_TYPE_40x,
  1236. .icache_bsize = 32,
  1237. .dcache_bsize = 32,
  1238. .machine_check = machine_check_4xx,
  1239. .platform = "ppc405",
  1240. },
  1241. { /* NP405L */
  1242. .pvr_mask = 0xffff0000,
  1243. .pvr_value = 0x41610000,
  1244. .cpu_name = "NP405L",
  1245. .cpu_features = CPU_FTRS_40X,
  1246. .cpu_user_features = PPC_FEATURE_32 |
  1247. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1248. .mmu_features = MMU_FTR_TYPE_40x,
  1249. .icache_bsize = 32,
  1250. .dcache_bsize = 32,
  1251. .machine_check = machine_check_4xx,
  1252. .platform = "ppc405",
  1253. },
  1254. { /* NP4GS3 */
  1255. .pvr_mask = 0xffff0000,
  1256. .pvr_value = 0x40B10000,
  1257. .cpu_name = "NP4GS3",
  1258. .cpu_features = CPU_FTRS_40X,
  1259. .cpu_user_features = PPC_FEATURE_32 |
  1260. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1261. .mmu_features = MMU_FTR_TYPE_40x,
  1262. .icache_bsize = 32,
  1263. .dcache_bsize = 32,
  1264. .machine_check = machine_check_4xx,
  1265. .platform = "ppc405",
  1266. },
  1267. { /* NP405H */
  1268. .pvr_mask = 0xffff0000,
  1269. .pvr_value = 0x41410000,
  1270. .cpu_name = "NP405H",
  1271. .cpu_features = CPU_FTRS_40X,
  1272. .cpu_user_features = PPC_FEATURE_32 |
  1273. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1274. .mmu_features = MMU_FTR_TYPE_40x,
  1275. .icache_bsize = 32,
  1276. .dcache_bsize = 32,
  1277. .machine_check = machine_check_4xx,
  1278. .platform = "ppc405",
  1279. },
  1280. { /* 405GPr */
  1281. .pvr_mask = 0xffff0000,
  1282. .pvr_value = 0x50910000,
  1283. .cpu_name = "405GPr",
  1284. .cpu_features = CPU_FTRS_40X,
  1285. .cpu_user_features = PPC_FEATURE_32 |
  1286. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1287. .mmu_features = MMU_FTR_TYPE_40x,
  1288. .icache_bsize = 32,
  1289. .dcache_bsize = 32,
  1290. .machine_check = machine_check_4xx,
  1291. .platform = "ppc405",
  1292. },
  1293. { /* STBx25xx */
  1294. .pvr_mask = 0xffff0000,
  1295. .pvr_value = 0x51510000,
  1296. .cpu_name = "STBx25xx",
  1297. .cpu_features = CPU_FTRS_40X,
  1298. .cpu_user_features = PPC_FEATURE_32 |
  1299. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1300. .mmu_features = MMU_FTR_TYPE_40x,
  1301. .icache_bsize = 32,
  1302. .dcache_bsize = 32,
  1303. .machine_check = machine_check_4xx,
  1304. .platform = "ppc405",
  1305. },
  1306. { /* 405LP */
  1307. .pvr_mask = 0xffff0000,
  1308. .pvr_value = 0x41F10000,
  1309. .cpu_name = "405LP",
  1310. .cpu_features = CPU_FTRS_40X,
  1311. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1312. .mmu_features = MMU_FTR_TYPE_40x,
  1313. .icache_bsize = 32,
  1314. .dcache_bsize = 32,
  1315. .machine_check = machine_check_4xx,
  1316. .platform = "ppc405",
  1317. },
  1318. { /* Xilinx Virtex-II Pro */
  1319. .pvr_mask = 0xfffff000,
  1320. .pvr_value = 0x20010000,
  1321. .cpu_name = "Virtex-II Pro",
  1322. .cpu_features = CPU_FTRS_40X,
  1323. .cpu_user_features = PPC_FEATURE_32 |
  1324. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1325. .mmu_features = MMU_FTR_TYPE_40x,
  1326. .icache_bsize = 32,
  1327. .dcache_bsize = 32,
  1328. .machine_check = machine_check_4xx,
  1329. .platform = "ppc405",
  1330. },
  1331. { /* Xilinx Virtex-4 FX */
  1332. .pvr_mask = 0xfffff000,
  1333. .pvr_value = 0x20011000,
  1334. .cpu_name = "Virtex-4 FX",
  1335. .cpu_features = CPU_FTRS_40X,
  1336. .cpu_user_features = PPC_FEATURE_32 |
  1337. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1338. .mmu_features = MMU_FTR_TYPE_40x,
  1339. .icache_bsize = 32,
  1340. .dcache_bsize = 32,
  1341. .machine_check = machine_check_4xx,
  1342. .platform = "ppc405",
  1343. },
  1344. { /* 405EP */
  1345. .pvr_mask = 0xffff0000,
  1346. .pvr_value = 0x51210000,
  1347. .cpu_name = "405EP",
  1348. .cpu_features = CPU_FTRS_40X,
  1349. .cpu_user_features = PPC_FEATURE_32 |
  1350. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1351. .mmu_features = MMU_FTR_TYPE_40x,
  1352. .icache_bsize = 32,
  1353. .dcache_bsize = 32,
  1354. .machine_check = machine_check_4xx,
  1355. .platform = "ppc405",
  1356. },
  1357. { /* 405EX Rev. A/B with Security */
  1358. .pvr_mask = 0xffff000f,
  1359. .pvr_value = 0x12910007,
  1360. .cpu_name = "405EX Rev. A/B",
  1361. .cpu_features = CPU_FTRS_40X,
  1362. .cpu_user_features = PPC_FEATURE_32 |
  1363. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1364. .mmu_features = MMU_FTR_TYPE_40x,
  1365. .icache_bsize = 32,
  1366. .dcache_bsize = 32,
  1367. .machine_check = machine_check_4xx,
  1368. .platform = "ppc405",
  1369. },
  1370. { /* 405EX Rev. C without Security */
  1371. .pvr_mask = 0xffff000f,
  1372. .pvr_value = 0x1291000d,
  1373. .cpu_name = "405EX Rev. C",
  1374. .cpu_features = CPU_FTRS_40X,
  1375. .cpu_user_features = PPC_FEATURE_32 |
  1376. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1377. .mmu_features = MMU_FTR_TYPE_40x,
  1378. .icache_bsize = 32,
  1379. .dcache_bsize = 32,
  1380. .machine_check = machine_check_4xx,
  1381. .platform = "ppc405",
  1382. },
  1383. { /* 405EX Rev. C with Security */
  1384. .pvr_mask = 0xffff000f,
  1385. .pvr_value = 0x1291000f,
  1386. .cpu_name = "405EX Rev. C",
  1387. .cpu_features = CPU_FTRS_40X,
  1388. .cpu_user_features = PPC_FEATURE_32 |
  1389. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1390. .mmu_features = MMU_FTR_TYPE_40x,
  1391. .icache_bsize = 32,
  1392. .dcache_bsize = 32,
  1393. .machine_check = machine_check_4xx,
  1394. .platform = "ppc405",
  1395. },
  1396. { /* 405EX Rev. D without Security */
  1397. .pvr_mask = 0xffff000f,
  1398. .pvr_value = 0x12910003,
  1399. .cpu_name = "405EX Rev. D",
  1400. .cpu_features = CPU_FTRS_40X,
  1401. .cpu_user_features = PPC_FEATURE_32 |
  1402. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1403. .mmu_features = MMU_FTR_TYPE_40x,
  1404. .icache_bsize = 32,
  1405. .dcache_bsize = 32,
  1406. .machine_check = machine_check_4xx,
  1407. .platform = "ppc405",
  1408. },
  1409. { /* 405EX Rev. D with Security */
  1410. .pvr_mask = 0xffff000f,
  1411. .pvr_value = 0x12910005,
  1412. .cpu_name = "405EX Rev. D",
  1413. .cpu_features = CPU_FTRS_40X,
  1414. .cpu_user_features = PPC_FEATURE_32 |
  1415. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1416. .mmu_features = MMU_FTR_TYPE_40x,
  1417. .icache_bsize = 32,
  1418. .dcache_bsize = 32,
  1419. .machine_check = machine_check_4xx,
  1420. .platform = "ppc405",
  1421. },
  1422. { /* 405EXr Rev. A/B without Security */
  1423. .pvr_mask = 0xffff000f,
  1424. .pvr_value = 0x12910001,
  1425. .cpu_name = "405EXr Rev. A/B",
  1426. .cpu_features = CPU_FTRS_40X,
  1427. .cpu_user_features = PPC_FEATURE_32 |
  1428. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1429. .mmu_features = MMU_FTR_TYPE_40x,
  1430. .icache_bsize = 32,
  1431. .dcache_bsize = 32,
  1432. .machine_check = machine_check_4xx,
  1433. .platform = "ppc405",
  1434. },
  1435. { /* 405EXr Rev. C without Security */
  1436. .pvr_mask = 0xffff000f,
  1437. .pvr_value = 0x12910009,
  1438. .cpu_name = "405EXr Rev. C",
  1439. .cpu_features = CPU_FTRS_40X,
  1440. .cpu_user_features = PPC_FEATURE_32 |
  1441. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1442. .mmu_features = MMU_FTR_TYPE_40x,
  1443. .icache_bsize = 32,
  1444. .dcache_bsize = 32,
  1445. .machine_check = machine_check_4xx,
  1446. .platform = "ppc405",
  1447. },
  1448. { /* 405EXr Rev. C with Security */
  1449. .pvr_mask = 0xffff000f,
  1450. .pvr_value = 0x1291000b,
  1451. .cpu_name = "405EXr Rev. C",
  1452. .cpu_features = CPU_FTRS_40X,
  1453. .cpu_user_features = PPC_FEATURE_32 |
  1454. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1455. .mmu_features = MMU_FTR_TYPE_40x,
  1456. .icache_bsize = 32,
  1457. .dcache_bsize = 32,
  1458. .machine_check = machine_check_4xx,
  1459. .platform = "ppc405",
  1460. },
  1461. { /* 405EXr Rev. D without Security */
  1462. .pvr_mask = 0xffff000f,
  1463. .pvr_value = 0x12910000,
  1464. .cpu_name = "405EXr Rev. D",
  1465. .cpu_features = CPU_FTRS_40X,
  1466. .cpu_user_features = PPC_FEATURE_32 |
  1467. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1468. .mmu_features = MMU_FTR_TYPE_40x,
  1469. .icache_bsize = 32,
  1470. .dcache_bsize = 32,
  1471. .machine_check = machine_check_4xx,
  1472. .platform = "ppc405",
  1473. },
  1474. { /* 405EXr Rev. D with Security */
  1475. .pvr_mask = 0xffff000f,
  1476. .pvr_value = 0x12910002,
  1477. .cpu_name = "405EXr Rev. D",
  1478. .cpu_features = CPU_FTRS_40X,
  1479. .cpu_user_features = PPC_FEATURE_32 |
  1480. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1481. .mmu_features = MMU_FTR_TYPE_40x,
  1482. .icache_bsize = 32,
  1483. .dcache_bsize = 32,
  1484. .machine_check = machine_check_4xx,
  1485. .platform = "ppc405",
  1486. },
  1487. {
  1488. /* 405EZ */
  1489. .pvr_mask = 0xffff0000,
  1490. .pvr_value = 0x41510000,
  1491. .cpu_name = "405EZ",
  1492. .cpu_features = CPU_FTRS_40X,
  1493. .cpu_user_features = PPC_FEATURE_32 |
  1494. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1495. .mmu_features = MMU_FTR_TYPE_40x,
  1496. .icache_bsize = 32,
  1497. .dcache_bsize = 32,
  1498. .machine_check = machine_check_4xx,
  1499. .platform = "ppc405",
  1500. },
  1501. { /* default match */
  1502. .pvr_mask = 0x00000000,
  1503. .pvr_value = 0x00000000,
  1504. .cpu_name = "(generic 40x PPC)",
  1505. .cpu_features = CPU_FTRS_40X,
  1506. .cpu_user_features = PPC_FEATURE_32 |
  1507. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1508. .mmu_features = MMU_FTR_TYPE_40x,
  1509. .icache_bsize = 32,
  1510. .dcache_bsize = 32,
  1511. .machine_check = machine_check_4xx,
  1512. .platform = "ppc405",
  1513. }
  1514. #endif /* CONFIG_40x */
  1515. #ifdef CONFIG_44x
  1516. {
  1517. .pvr_mask = 0xf0000fff,
  1518. .pvr_value = 0x40000850,
  1519. .cpu_name = "440GR Rev. A",
  1520. .cpu_features = CPU_FTRS_44X,
  1521. .cpu_user_features = COMMON_USER_BOOKE,
  1522. .mmu_features = MMU_FTR_TYPE_44x,
  1523. .icache_bsize = 32,
  1524. .dcache_bsize = 32,
  1525. .machine_check = machine_check_4xx,
  1526. .platform = "ppc440",
  1527. },
  1528. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1529. .pvr_mask = 0xf0000fff,
  1530. .pvr_value = 0x40000858,
  1531. .cpu_name = "440EP Rev. A",
  1532. .cpu_features = CPU_FTRS_44X,
  1533. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1534. .mmu_features = MMU_FTR_TYPE_44x,
  1535. .icache_bsize = 32,
  1536. .dcache_bsize = 32,
  1537. .cpu_setup = __setup_cpu_440ep,
  1538. .machine_check = machine_check_4xx,
  1539. .platform = "ppc440",
  1540. },
  1541. {
  1542. .pvr_mask = 0xf0000fff,
  1543. .pvr_value = 0x400008d3,
  1544. .cpu_name = "440GR Rev. B",
  1545. .cpu_features = CPU_FTRS_44X,
  1546. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1547. .mmu_features = MMU_FTR_TYPE_44x,
  1548. .icache_bsize = 32,
  1549. .dcache_bsize = 32,
  1550. .machine_check = machine_check_4xx,
  1551. .platform = "ppc440",
  1552. },
  1553. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1554. .pvr_mask = 0xf0000ff7,
  1555. .pvr_value = 0x400008d4,
  1556. .cpu_name = "440EP Rev. C",
  1557. .cpu_features = CPU_FTRS_44X,
  1558. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1559. .mmu_features = MMU_FTR_TYPE_44x,
  1560. .icache_bsize = 32,
  1561. .dcache_bsize = 32,
  1562. .cpu_setup = __setup_cpu_440ep,
  1563. .machine_check = machine_check_4xx,
  1564. .platform = "ppc440",
  1565. },
  1566. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1567. .pvr_mask = 0xf0000fff,
  1568. .pvr_value = 0x400008db,
  1569. .cpu_name = "440EP Rev. B",
  1570. .cpu_features = CPU_FTRS_44X,
  1571. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1572. .mmu_features = MMU_FTR_TYPE_44x,
  1573. .icache_bsize = 32,
  1574. .dcache_bsize = 32,
  1575. .cpu_setup = __setup_cpu_440ep,
  1576. .machine_check = machine_check_4xx,
  1577. .platform = "ppc440",
  1578. },
  1579. { /* 440GRX */
  1580. .pvr_mask = 0xf0000ffb,
  1581. .pvr_value = 0x200008D0,
  1582. .cpu_name = "440GRX",
  1583. .cpu_features = CPU_FTRS_44X,
  1584. .cpu_user_features = COMMON_USER_BOOKE,
  1585. .mmu_features = MMU_FTR_TYPE_44x,
  1586. .icache_bsize = 32,
  1587. .dcache_bsize = 32,
  1588. .cpu_setup = __setup_cpu_440grx,
  1589. .machine_check = machine_check_440A,
  1590. .platform = "ppc440",
  1591. },
  1592. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1593. .pvr_mask = 0xf0000ffb,
  1594. .pvr_value = 0x200008D8,
  1595. .cpu_name = "440EPX",
  1596. .cpu_features = CPU_FTRS_44X,
  1597. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1598. .mmu_features = MMU_FTR_TYPE_44x,
  1599. .icache_bsize = 32,
  1600. .dcache_bsize = 32,
  1601. .cpu_setup = __setup_cpu_440epx,
  1602. .machine_check = machine_check_440A,
  1603. .platform = "ppc440",
  1604. },
  1605. { /* 440GP Rev. B */
  1606. .pvr_mask = 0xf0000fff,
  1607. .pvr_value = 0x40000440,
  1608. .cpu_name = "440GP Rev. B",
  1609. .cpu_features = CPU_FTRS_44X,
  1610. .cpu_user_features = COMMON_USER_BOOKE,
  1611. .mmu_features = MMU_FTR_TYPE_44x,
  1612. .icache_bsize = 32,
  1613. .dcache_bsize = 32,
  1614. .machine_check = machine_check_4xx,
  1615. .platform = "ppc440gp",
  1616. },
  1617. { /* 440GP Rev. C */
  1618. .pvr_mask = 0xf0000fff,
  1619. .pvr_value = 0x40000481,
  1620. .cpu_name = "440GP Rev. C",
  1621. .cpu_features = CPU_FTRS_44X,
  1622. .cpu_user_features = COMMON_USER_BOOKE,
  1623. .mmu_features = MMU_FTR_TYPE_44x,
  1624. .icache_bsize = 32,
  1625. .dcache_bsize = 32,
  1626. .machine_check = machine_check_4xx,
  1627. .platform = "ppc440gp",
  1628. },
  1629. { /* 440GX Rev. A */
  1630. .pvr_mask = 0xf0000fff,
  1631. .pvr_value = 0x50000850,
  1632. .cpu_name = "440GX Rev. A",
  1633. .cpu_features = CPU_FTRS_44X,
  1634. .cpu_user_features = COMMON_USER_BOOKE,
  1635. .mmu_features = MMU_FTR_TYPE_44x,
  1636. .icache_bsize = 32,
  1637. .dcache_bsize = 32,
  1638. .cpu_setup = __setup_cpu_440gx,
  1639. .machine_check = machine_check_440A,
  1640. .platform = "ppc440",
  1641. },
  1642. { /* 440GX Rev. B */
  1643. .pvr_mask = 0xf0000fff,
  1644. .pvr_value = 0x50000851,
  1645. .cpu_name = "440GX Rev. B",
  1646. .cpu_features = CPU_FTRS_44X,
  1647. .cpu_user_features = COMMON_USER_BOOKE,
  1648. .mmu_features = MMU_FTR_TYPE_44x,
  1649. .icache_bsize = 32,
  1650. .dcache_bsize = 32,
  1651. .cpu_setup = __setup_cpu_440gx,
  1652. .machine_check = machine_check_440A,
  1653. .platform = "ppc440",
  1654. },
  1655. { /* 440GX Rev. C */
  1656. .pvr_mask = 0xf0000fff,
  1657. .pvr_value = 0x50000892,
  1658. .cpu_name = "440GX Rev. C",
  1659. .cpu_features = CPU_FTRS_44X,
  1660. .cpu_user_features = COMMON_USER_BOOKE,
  1661. .mmu_features = MMU_FTR_TYPE_44x,
  1662. .icache_bsize = 32,
  1663. .dcache_bsize = 32,
  1664. .cpu_setup = __setup_cpu_440gx,
  1665. .machine_check = machine_check_440A,
  1666. .platform = "ppc440",
  1667. },
  1668. { /* 440GX Rev. F */
  1669. .pvr_mask = 0xf0000fff,
  1670. .pvr_value = 0x50000894,
  1671. .cpu_name = "440GX Rev. F",
  1672. .cpu_features = CPU_FTRS_44X,
  1673. .cpu_user_features = COMMON_USER_BOOKE,
  1674. .mmu_features = MMU_FTR_TYPE_44x,
  1675. .icache_bsize = 32,
  1676. .dcache_bsize = 32,
  1677. .cpu_setup = __setup_cpu_440gx,
  1678. .machine_check = machine_check_440A,
  1679. .platform = "ppc440",
  1680. },
  1681. { /* 440SP Rev. A */
  1682. .pvr_mask = 0xfff00fff,
  1683. .pvr_value = 0x53200891,
  1684. .cpu_name = "440SP Rev. A",
  1685. .cpu_features = CPU_FTRS_44X,
  1686. .cpu_user_features = COMMON_USER_BOOKE,
  1687. .mmu_features = MMU_FTR_TYPE_44x,
  1688. .icache_bsize = 32,
  1689. .dcache_bsize = 32,
  1690. .machine_check = machine_check_4xx,
  1691. .platform = "ppc440",
  1692. },
  1693. { /* 440SPe Rev. A */
  1694. .pvr_mask = 0xfff00fff,
  1695. .pvr_value = 0x53400890,
  1696. .cpu_name = "440SPe Rev. A",
  1697. .cpu_features = CPU_FTRS_44X,
  1698. .cpu_user_features = COMMON_USER_BOOKE,
  1699. .mmu_features = MMU_FTR_TYPE_44x,
  1700. .icache_bsize = 32,
  1701. .dcache_bsize = 32,
  1702. .cpu_setup = __setup_cpu_440spe,
  1703. .machine_check = machine_check_440A,
  1704. .platform = "ppc440",
  1705. },
  1706. { /* 440SPe Rev. B */
  1707. .pvr_mask = 0xfff00fff,
  1708. .pvr_value = 0x53400891,
  1709. .cpu_name = "440SPe Rev. B",
  1710. .cpu_features = CPU_FTRS_44X,
  1711. .cpu_user_features = COMMON_USER_BOOKE,
  1712. .mmu_features = MMU_FTR_TYPE_44x,
  1713. .icache_bsize = 32,
  1714. .dcache_bsize = 32,
  1715. .cpu_setup = __setup_cpu_440spe,
  1716. .machine_check = machine_check_440A,
  1717. .platform = "ppc440",
  1718. },
  1719. { /* 440 in Xilinx Virtex-5 FXT */
  1720. .pvr_mask = 0xfffffff0,
  1721. .pvr_value = 0x7ff21910,
  1722. .cpu_name = "440 in Virtex-5 FXT",
  1723. .cpu_features = CPU_FTRS_44X,
  1724. .cpu_user_features = COMMON_USER_BOOKE,
  1725. .mmu_features = MMU_FTR_TYPE_44x,
  1726. .icache_bsize = 32,
  1727. .dcache_bsize = 32,
  1728. .cpu_setup = __setup_cpu_440x5,
  1729. .machine_check = machine_check_440A,
  1730. .platform = "ppc440",
  1731. },
  1732. { /* 460EX */
  1733. .pvr_mask = 0xffff0006,
  1734. .pvr_value = 0x13020002,
  1735. .cpu_name = "460EX",
  1736. .cpu_features = CPU_FTRS_440x6,
  1737. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1738. .mmu_features = MMU_FTR_TYPE_44x,
  1739. .icache_bsize = 32,
  1740. .dcache_bsize = 32,
  1741. .cpu_setup = __setup_cpu_460ex,
  1742. .machine_check = machine_check_440A,
  1743. .platform = "ppc440",
  1744. },
  1745. { /* 460EX Rev B */
  1746. .pvr_mask = 0xffff0007,
  1747. .pvr_value = 0x13020004,
  1748. .cpu_name = "460EX Rev. B",
  1749. .cpu_features = CPU_FTRS_440x6,
  1750. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1751. .mmu_features = MMU_FTR_TYPE_44x,
  1752. .icache_bsize = 32,
  1753. .dcache_bsize = 32,
  1754. .cpu_setup = __setup_cpu_460ex,
  1755. .machine_check = machine_check_440A,
  1756. .platform = "ppc440",
  1757. },
  1758. { /* 460GT */
  1759. .pvr_mask = 0xffff0006,
  1760. .pvr_value = 0x13020000,
  1761. .cpu_name = "460GT",
  1762. .cpu_features = CPU_FTRS_440x6,
  1763. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1764. .mmu_features = MMU_FTR_TYPE_44x,
  1765. .icache_bsize = 32,
  1766. .dcache_bsize = 32,
  1767. .cpu_setup = __setup_cpu_460gt,
  1768. .machine_check = machine_check_440A,
  1769. .platform = "ppc440",
  1770. },
  1771. { /* 460GT Rev B */
  1772. .pvr_mask = 0xffff0007,
  1773. .pvr_value = 0x13020005,
  1774. .cpu_name = "460GT Rev. B",
  1775. .cpu_features = CPU_FTRS_440x6,
  1776. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1777. .mmu_features = MMU_FTR_TYPE_44x,
  1778. .icache_bsize = 32,
  1779. .dcache_bsize = 32,
  1780. .cpu_setup = __setup_cpu_460gt,
  1781. .machine_check = machine_check_440A,
  1782. .platform = "ppc440",
  1783. },
  1784. { /* 460SX */
  1785. .pvr_mask = 0xffffff00,
  1786. .pvr_value = 0x13541800,
  1787. .cpu_name = "460SX",
  1788. .cpu_features = CPU_FTRS_44X,
  1789. .cpu_user_features = COMMON_USER_BOOKE,
  1790. .mmu_features = MMU_FTR_TYPE_44x,
  1791. .icache_bsize = 32,
  1792. .dcache_bsize = 32,
  1793. .cpu_setup = __setup_cpu_460sx,
  1794. .machine_check = machine_check_440A,
  1795. .platform = "ppc440",
  1796. },
  1797. { /* 464 in APM821xx */
  1798. .pvr_mask = 0xffffff00,
  1799. .pvr_value = 0x12C41C80,
  1800. .cpu_name = "APM821XX",
  1801. .cpu_features = CPU_FTRS_44X,
  1802. .cpu_user_features = COMMON_USER_BOOKE |
  1803. PPC_FEATURE_HAS_FPU,
  1804. .mmu_features = MMU_FTR_TYPE_44x,
  1805. .icache_bsize = 32,
  1806. .dcache_bsize = 32,
  1807. .cpu_setup = __setup_cpu_apm821xx,
  1808. .machine_check = machine_check_440A,
  1809. .platform = "ppc440",
  1810. },
  1811. { /* 476 DD2 core */
  1812. .pvr_mask = 0xffffffff,
  1813. .pvr_value = 0x11a52080,
  1814. .cpu_name = "476",
  1815. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1816. .cpu_user_features = COMMON_USER_BOOKE |
  1817. PPC_FEATURE_HAS_FPU,
  1818. .mmu_features = MMU_FTR_TYPE_47x |
  1819. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1820. .icache_bsize = 32,
  1821. .dcache_bsize = 128,
  1822. .machine_check = machine_check_47x,
  1823. .platform = "ppc470",
  1824. },
  1825. { /* 476 iss */
  1826. .pvr_mask = 0xffff0000,
  1827. .pvr_value = 0x00050000,
  1828. .cpu_name = "476",
  1829. .cpu_features = CPU_FTRS_47X,
  1830. .cpu_user_features = COMMON_USER_BOOKE |
  1831. PPC_FEATURE_HAS_FPU,
  1832. .mmu_features = MMU_FTR_TYPE_47x |
  1833. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1834. .icache_bsize = 32,
  1835. .dcache_bsize = 128,
  1836. .machine_check = machine_check_47x,
  1837. .platform = "ppc470",
  1838. },
  1839. { /* 476 others */
  1840. .pvr_mask = 0xffff0000,
  1841. .pvr_value = 0x11a50000,
  1842. .cpu_name = "476",
  1843. .cpu_features = CPU_FTRS_47X,
  1844. .cpu_user_features = COMMON_USER_BOOKE |
  1845. PPC_FEATURE_HAS_FPU,
  1846. .mmu_features = MMU_FTR_TYPE_47x |
  1847. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1848. .icache_bsize = 32,
  1849. .dcache_bsize = 128,
  1850. .machine_check = machine_check_47x,
  1851. .platform = "ppc470",
  1852. },
  1853. { /* default match */
  1854. .pvr_mask = 0x00000000,
  1855. .pvr_value = 0x00000000,
  1856. .cpu_name = "(generic 44x PPC)",
  1857. .cpu_features = CPU_FTRS_44X,
  1858. .cpu_user_features = COMMON_USER_BOOKE,
  1859. .mmu_features = MMU_FTR_TYPE_44x,
  1860. .icache_bsize = 32,
  1861. .dcache_bsize = 32,
  1862. .machine_check = machine_check_4xx,
  1863. .platform = "ppc440",
  1864. }
  1865. #endif /* CONFIG_44x */
  1866. #ifdef CONFIG_E200
  1867. { /* e200z5 */
  1868. .pvr_mask = 0xfff00000,
  1869. .pvr_value = 0x81000000,
  1870. .cpu_name = "e200z5",
  1871. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1872. .cpu_features = CPU_FTRS_E200,
  1873. .cpu_user_features = COMMON_USER_BOOKE |
  1874. PPC_FEATURE_HAS_EFP_SINGLE |
  1875. PPC_FEATURE_UNIFIED_CACHE,
  1876. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1877. .dcache_bsize = 32,
  1878. .machine_check = machine_check_e200,
  1879. .platform = "ppc5554",
  1880. },
  1881. { /* e200z6 */
  1882. .pvr_mask = 0xfff00000,
  1883. .pvr_value = 0x81100000,
  1884. .cpu_name = "e200z6",
  1885. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1886. .cpu_features = CPU_FTRS_E200,
  1887. .cpu_user_features = COMMON_USER_BOOKE |
  1888. PPC_FEATURE_HAS_SPE_COMP |
  1889. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1890. PPC_FEATURE_UNIFIED_CACHE,
  1891. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1892. .dcache_bsize = 32,
  1893. .machine_check = machine_check_e200,
  1894. .platform = "ppc5554",
  1895. },
  1896. { /* default match */
  1897. .pvr_mask = 0x00000000,
  1898. .pvr_value = 0x00000000,
  1899. .cpu_name = "(generic E200 PPC)",
  1900. .cpu_features = CPU_FTRS_E200,
  1901. .cpu_user_features = COMMON_USER_BOOKE |
  1902. PPC_FEATURE_HAS_EFP_SINGLE |
  1903. PPC_FEATURE_UNIFIED_CACHE,
  1904. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1905. .dcache_bsize = 32,
  1906. .cpu_setup = __setup_cpu_e200,
  1907. .machine_check = machine_check_e200,
  1908. .platform = "ppc5554",
  1909. }
  1910. #endif /* CONFIG_E200 */
  1911. #endif /* CONFIG_PPC32 */
  1912. #ifdef CONFIG_E500
  1913. #ifdef CONFIG_PPC32
  1914. { /* e500 */
  1915. .pvr_mask = 0xffff0000,
  1916. .pvr_value = 0x80200000,
  1917. .cpu_name = "e500",
  1918. .cpu_features = CPU_FTRS_E500,
  1919. .cpu_user_features = COMMON_USER_BOOKE |
  1920. PPC_FEATURE_HAS_SPE_COMP |
  1921. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1922. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1923. .icache_bsize = 32,
  1924. .dcache_bsize = 32,
  1925. .num_pmcs = 4,
  1926. .oprofile_cpu_type = "ppc/e500",
  1927. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1928. .cpu_setup = __setup_cpu_e500v1,
  1929. .machine_check = machine_check_e500,
  1930. .platform = "ppc8540",
  1931. },
  1932. { /* e500v2 */
  1933. .pvr_mask = 0xffff0000,
  1934. .pvr_value = 0x80210000,
  1935. .cpu_name = "e500v2",
  1936. .cpu_features = CPU_FTRS_E500_2,
  1937. .cpu_user_features = COMMON_USER_BOOKE |
  1938. PPC_FEATURE_HAS_SPE_COMP |
  1939. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1940. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1941. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  1942. .icache_bsize = 32,
  1943. .dcache_bsize = 32,
  1944. .num_pmcs = 4,
  1945. .oprofile_cpu_type = "ppc/e500",
  1946. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1947. .cpu_setup = __setup_cpu_e500v2,
  1948. .machine_check = machine_check_e500,
  1949. .platform = "ppc8548",
  1950. },
  1951. { /* e500mc */
  1952. .pvr_mask = 0xffff0000,
  1953. .pvr_value = 0x80230000,
  1954. .cpu_name = "e500mc",
  1955. .cpu_features = CPU_FTRS_E500MC,
  1956. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1957. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1958. MMU_FTR_USE_TLBILX,
  1959. .icache_bsize = 64,
  1960. .dcache_bsize = 64,
  1961. .num_pmcs = 4,
  1962. .oprofile_cpu_type = "ppc/e500mc",
  1963. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1964. .cpu_setup = __setup_cpu_e500mc,
  1965. .machine_check = machine_check_e500mc,
  1966. .platform = "ppce500mc",
  1967. },
  1968. #endif /* CONFIG_PPC32 */
  1969. { /* e5500 */
  1970. .pvr_mask = 0xffff0000,
  1971. .pvr_value = 0x80240000,
  1972. .cpu_name = "e5500",
  1973. .cpu_features = CPU_FTRS_E5500,
  1974. .cpu_user_features = COMMON_USER_BOOKE,
  1975. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1976. MMU_FTR_USE_TLBILX,
  1977. .icache_bsize = 64,
  1978. .dcache_bsize = 64,
  1979. .num_pmcs = 4,
  1980. .oprofile_cpu_type = "ppc/e500mc",
  1981. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1982. .cpu_setup = __setup_cpu_e5500,
  1983. .cpu_restore = __restore_cpu_e5500,
  1984. .machine_check = machine_check_e500mc,
  1985. .platform = "ppce5500",
  1986. },
  1987. #ifdef CONFIG_PPC32
  1988. { /* default match */
  1989. .pvr_mask = 0x00000000,
  1990. .pvr_value = 0x00000000,
  1991. .cpu_name = "(generic E500 PPC)",
  1992. .cpu_features = CPU_FTRS_E500,
  1993. .cpu_user_features = COMMON_USER_BOOKE |
  1994. PPC_FEATURE_HAS_SPE_COMP |
  1995. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1996. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1997. .icache_bsize = 32,
  1998. .dcache_bsize = 32,
  1999. .machine_check = machine_check_e500,
  2000. .platform = "powerpc",
  2001. }
  2002. #endif /* CONFIG_PPC32 */
  2003. #endif /* CONFIG_E500 */
  2004. #ifdef CONFIG_PPC_BOOK3E_64
  2005. { /* This is a default entry to get going, to be replaced by
  2006. * a real one at some stage
  2007. */
  2008. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  2009. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  2010. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  2011. .pvr_mask = 0x00000000,
  2012. .pvr_value = 0x00000000,
  2013. .cpu_name = "Book3E",
  2014. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2015. .cpu_user_features = COMMON_USER_PPC64,
  2016. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2017. MMU_FTR_USE_TLBIVAX_BCAST |
  2018. MMU_FTR_LOCK_BCAST_INVAL,
  2019. .icache_bsize = 64,
  2020. .dcache_bsize = 64,
  2021. .num_pmcs = 0,
  2022. .machine_check = machine_check_generic,
  2023. .platform = "power6",
  2024. },
  2025. #endif
  2026. };
  2027. static struct cpu_spec the_cpu_spec;
  2028. static void __init setup_cpu_spec(unsigned long offset, struct cpu_spec *s)
  2029. {
  2030. struct cpu_spec *t = &the_cpu_spec;
  2031. struct cpu_spec old;
  2032. t = PTRRELOC(t);
  2033. old = *t;
  2034. /* Copy everything, then do fixups */
  2035. *t = *s;
  2036. /*
  2037. * If we are overriding a previous value derived from the real
  2038. * PVR with a new value obtained using a logical PVR value,
  2039. * don't modify the performance monitor fields.
  2040. */
  2041. if (old.num_pmcs && !s->num_pmcs) {
  2042. t->num_pmcs = old.num_pmcs;
  2043. t->pmc_type = old.pmc_type;
  2044. t->oprofile_type = old.oprofile_type;
  2045. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2046. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2047. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2048. /*
  2049. * If we have passed through this logic once before and
  2050. * have pulled the default case because the real PVR was
  2051. * not found inside cpu_specs[], then we are possibly
  2052. * running in compatibility mode. In that case, let the
  2053. * oprofiler know which set of compatibility counters to
  2054. * pull from by making sure the oprofile_cpu_type string
  2055. * is set to that of compatibility mode. If the
  2056. * oprofile_cpu_type already has a value, then we are
  2057. * possibly overriding a real PVR with a logical one,
  2058. * and, in that case, keep the current value for
  2059. * oprofile_cpu_type.
  2060. */
  2061. if (old.oprofile_cpu_type != NULL) {
  2062. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2063. t->oprofile_type = old.oprofile_type;
  2064. }
  2065. }
  2066. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2067. /*
  2068. * Set the base platform string once; assumes
  2069. * we're called with real pvr first.
  2070. */
  2071. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2072. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2073. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2074. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2075. * that processor. I will consolidate that at a later time, for now,
  2076. * just use #ifdef. We also don't need to PTRRELOC the function
  2077. * pointer on ppc64 and booke as we are running at 0 in real mode
  2078. * on ppc64 and reloc_offset is always 0 on booke.
  2079. */
  2080. if (t->cpu_setup) {
  2081. t->cpu_setup(offset, t);
  2082. }
  2083. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2084. }
  2085. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2086. {
  2087. struct cpu_spec *s = cpu_specs;
  2088. int i;
  2089. s = PTRRELOC(s);
  2090. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2091. if ((pvr & s->pvr_mask) == s->pvr_value) {
  2092. setup_cpu_spec(offset, s);
  2093. return s;
  2094. }
  2095. }
  2096. BUG();
  2097. return NULL;
  2098. }