i915_debugfs.c 47 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. FLUSHING_LIST,
  43. INACTIVE_LIST,
  44. PINNED_LIST,
  45. DEFERRED_FREE_LIST,
  46. };
  47. static const char *yesno(int v)
  48. {
  49. return v ? "yes" : "no";
  50. }
  51. static int i915_capabilities(struct seq_file *m, void *data)
  52. {
  53. struct drm_info_node *node = (struct drm_info_node *) m->private;
  54. struct drm_device *dev = node->minor->dev;
  55. const struct intel_device_info *info = INTEL_INFO(dev);
  56. seq_printf(m, "gen: %d\n", info->gen);
  57. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  58. B(is_mobile);
  59. B(is_i85x);
  60. B(is_i915g);
  61. B(is_i945gm);
  62. B(is_g33);
  63. B(need_gfx_hws);
  64. B(is_g4x);
  65. B(is_pineview);
  66. B(is_broadwater);
  67. B(is_crestline);
  68. B(has_fbc);
  69. B(has_pipe_cxsr);
  70. B(has_hotplug);
  71. B(cursor_needs_physical);
  72. B(has_overlay);
  73. B(overlay_needs_physical);
  74. B(supports_tv);
  75. B(has_bsd_ring);
  76. B(has_blt_ring);
  77. #undef B
  78. return 0;
  79. }
  80. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  81. {
  82. if (obj->user_pin_count > 0)
  83. return "P";
  84. else if (obj->pin_count > 0)
  85. return "p";
  86. else
  87. return " ";
  88. }
  89. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  90. {
  91. switch (obj->tiling_mode) {
  92. default:
  93. case I915_TILING_NONE: return " ";
  94. case I915_TILING_X: return "X";
  95. case I915_TILING_Y: return "Y";
  96. }
  97. }
  98. static const char *cache_level_str(int type)
  99. {
  100. switch (type) {
  101. case I915_CACHE_NONE: return " uncached";
  102. case I915_CACHE_LLC: return " snooped (LLC)";
  103. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  104. default: return "";
  105. }
  106. }
  107. static void
  108. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  109. {
  110. seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
  111. &obj->base,
  112. get_pin_flag(obj),
  113. get_tiling_flag(obj),
  114. obj->base.size,
  115. obj->base.read_domains,
  116. obj->base.write_domain,
  117. obj->last_rendering_seqno,
  118. obj->last_fenced_seqno,
  119. cache_level_str(obj->cache_level),
  120. obj->dirty ? " dirty" : "",
  121. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  122. if (obj->base.name)
  123. seq_printf(m, " (name: %d)", obj->base.name);
  124. if (obj->fence_reg != I915_FENCE_REG_NONE)
  125. seq_printf(m, " (fence: %d)", obj->fence_reg);
  126. if (obj->gtt_space != NULL)
  127. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  128. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  129. if (obj->pin_mappable || obj->fault_mappable) {
  130. char s[3], *t = s;
  131. if (obj->pin_mappable)
  132. *t++ = 'p';
  133. if (obj->fault_mappable)
  134. *t++ = 'f';
  135. *t = '\0';
  136. seq_printf(m, " (%s mappable)", s);
  137. }
  138. if (obj->ring != NULL)
  139. seq_printf(m, " (%s)", obj->ring->name);
  140. }
  141. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  142. {
  143. struct drm_info_node *node = (struct drm_info_node *) m->private;
  144. uintptr_t list = (uintptr_t) node->info_ent->data;
  145. struct list_head *head;
  146. struct drm_device *dev = node->minor->dev;
  147. drm_i915_private_t *dev_priv = dev->dev_private;
  148. struct drm_i915_gem_object *obj;
  149. size_t total_obj_size, total_gtt_size;
  150. int count, ret;
  151. ret = mutex_lock_interruptible(&dev->struct_mutex);
  152. if (ret)
  153. return ret;
  154. switch (list) {
  155. case ACTIVE_LIST:
  156. seq_printf(m, "Active:\n");
  157. head = &dev_priv->mm.active_list;
  158. break;
  159. case INACTIVE_LIST:
  160. seq_printf(m, "Inactive:\n");
  161. head = &dev_priv->mm.inactive_list;
  162. break;
  163. case PINNED_LIST:
  164. seq_printf(m, "Pinned:\n");
  165. head = &dev_priv->mm.pinned_list;
  166. break;
  167. case FLUSHING_LIST:
  168. seq_printf(m, "Flushing:\n");
  169. head = &dev_priv->mm.flushing_list;
  170. break;
  171. case DEFERRED_FREE_LIST:
  172. seq_printf(m, "Deferred free:\n");
  173. head = &dev_priv->mm.deferred_free_list;
  174. break;
  175. default:
  176. mutex_unlock(&dev->struct_mutex);
  177. return -EINVAL;
  178. }
  179. total_obj_size = total_gtt_size = count = 0;
  180. list_for_each_entry(obj, head, mm_list) {
  181. seq_printf(m, " ");
  182. describe_obj(m, obj);
  183. seq_printf(m, "\n");
  184. total_obj_size += obj->base.size;
  185. total_gtt_size += obj->gtt_space->size;
  186. count++;
  187. }
  188. mutex_unlock(&dev->struct_mutex);
  189. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  190. count, total_obj_size, total_gtt_size);
  191. return 0;
  192. }
  193. #define count_objects(list, member) do { \
  194. list_for_each_entry(obj, list, member) { \
  195. size += obj->gtt_space->size; \
  196. ++count; \
  197. if (obj->map_and_fenceable) { \
  198. mappable_size += obj->gtt_space->size; \
  199. ++mappable_count; \
  200. } \
  201. } \
  202. } while (0)
  203. static int i915_gem_object_info(struct seq_file *m, void* data)
  204. {
  205. struct drm_info_node *node = (struct drm_info_node *) m->private;
  206. struct drm_device *dev = node->minor->dev;
  207. struct drm_i915_private *dev_priv = dev->dev_private;
  208. u32 count, mappable_count;
  209. size_t size, mappable_size;
  210. struct drm_i915_gem_object *obj;
  211. int ret;
  212. ret = mutex_lock_interruptible(&dev->struct_mutex);
  213. if (ret)
  214. return ret;
  215. seq_printf(m, "%u objects, %zu bytes\n",
  216. dev_priv->mm.object_count,
  217. dev_priv->mm.object_memory);
  218. size = count = mappable_size = mappable_count = 0;
  219. count_objects(&dev_priv->mm.gtt_list, gtt_list);
  220. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  221. count, mappable_count, size, mappable_size);
  222. size = count = mappable_size = mappable_count = 0;
  223. count_objects(&dev_priv->mm.active_list, mm_list);
  224. count_objects(&dev_priv->mm.flushing_list, mm_list);
  225. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  226. count, mappable_count, size, mappable_size);
  227. size = count = mappable_size = mappable_count = 0;
  228. count_objects(&dev_priv->mm.pinned_list, mm_list);
  229. seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
  230. count, mappable_count, size, mappable_size);
  231. size = count = mappable_size = mappable_count = 0;
  232. count_objects(&dev_priv->mm.inactive_list, mm_list);
  233. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  234. count, mappable_count, size, mappable_size);
  235. size = count = mappable_size = mappable_count = 0;
  236. count_objects(&dev_priv->mm.deferred_free_list, mm_list);
  237. seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
  238. count, mappable_count, size, mappable_size);
  239. size = count = mappable_size = mappable_count = 0;
  240. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  241. if (obj->fault_mappable) {
  242. size += obj->gtt_space->size;
  243. ++count;
  244. }
  245. if (obj->pin_mappable) {
  246. mappable_size += obj->gtt_space->size;
  247. ++mappable_count;
  248. }
  249. }
  250. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  251. mappable_count, mappable_size);
  252. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  253. count, size);
  254. seq_printf(m, "%zu [%zu] gtt total\n",
  255. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  256. mutex_unlock(&dev->struct_mutex);
  257. return 0;
  258. }
  259. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  260. {
  261. struct drm_info_node *node = (struct drm_info_node *) m->private;
  262. struct drm_device *dev = node->minor->dev;
  263. struct drm_i915_private *dev_priv = dev->dev_private;
  264. struct drm_i915_gem_object *obj;
  265. size_t total_obj_size, total_gtt_size;
  266. int count, ret;
  267. ret = mutex_lock_interruptible(&dev->struct_mutex);
  268. if (ret)
  269. return ret;
  270. total_obj_size = total_gtt_size = count = 0;
  271. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  272. seq_printf(m, " ");
  273. describe_obj(m, obj);
  274. seq_printf(m, "\n");
  275. total_obj_size += obj->base.size;
  276. total_gtt_size += obj->gtt_space->size;
  277. count++;
  278. }
  279. mutex_unlock(&dev->struct_mutex);
  280. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  281. count, total_obj_size, total_gtt_size);
  282. return 0;
  283. }
  284. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  285. {
  286. struct drm_info_node *node = (struct drm_info_node *) m->private;
  287. struct drm_device *dev = node->minor->dev;
  288. unsigned long flags;
  289. struct intel_crtc *crtc;
  290. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  291. const char pipe = pipe_name(crtc->pipe);
  292. const char plane = plane_name(crtc->plane);
  293. struct intel_unpin_work *work;
  294. spin_lock_irqsave(&dev->event_lock, flags);
  295. work = crtc->unpin_work;
  296. if (work == NULL) {
  297. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  298. pipe, plane);
  299. } else {
  300. if (!work->pending) {
  301. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  302. pipe, plane);
  303. } else {
  304. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  305. pipe, plane);
  306. }
  307. if (work->enable_stall_check)
  308. seq_printf(m, "Stall check enabled, ");
  309. else
  310. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  311. seq_printf(m, "%d prepares\n", work->pending);
  312. if (work->old_fb_obj) {
  313. struct drm_i915_gem_object *obj = work->old_fb_obj;
  314. if (obj)
  315. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  316. }
  317. if (work->pending_flip_obj) {
  318. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  319. if (obj)
  320. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  321. }
  322. }
  323. spin_unlock_irqrestore(&dev->event_lock, flags);
  324. }
  325. return 0;
  326. }
  327. static int i915_gem_request_info(struct seq_file *m, void *data)
  328. {
  329. struct drm_info_node *node = (struct drm_info_node *) m->private;
  330. struct drm_device *dev = node->minor->dev;
  331. drm_i915_private_t *dev_priv = dev->dev_private;
  332. struct drm_i915_gem_request *gem_request;
  333. int ret, count;
  334. ret = mutex_lock_interruptible(&dev->struct_mutex);
  335. if (ret)
  336. return ret;
  337. count = 0;
  338. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  339. seq_printf(m, "Render requests:\n");
  340. list_for_each_entry(gem_request,
  341. &dev_priv->ring[RCS].request_list,
  342. list) {
  343. seq_printf(m, " %d @ %d\n",
  344. gem_request->seqno,
  345. (int) (jiffies - gem_request->emitted_jiffies));
  346. }
  347. count++;
  348. }
  349. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  350. seq_printf(m, "BSD requests:\n");
  351. list_for_each_entry(gem_request,
  352. &dev_priv->ring[VCS].request_list,
  353. list) {
  354. seq_printf(m, " %d @ %d\n",
  355. gem_request->seqno,
  356. (int) (jiffies - gem_request->emitted_jiffies));
  357. }
  358. count++;
  359. }
  360. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  361. seq_printf(m, "BLT requests:\n");
  362. list_for_each_entry(gem_request,
  363. &dev_priv->ring[BCS].request_list,
  364. list) {
  365. seq_printf(m, " %d @ %d\n",
  366. gem_request->seqno,
  367. (int) (jiffies - gem_request->emitted_jiffies));
  368. }
  369. count++;
  370. }
  371. mutex_unlock(&dev->struct_mutex);
  372. if (count == 0)
  373. seq_printf(m, "No requests\n");
  374. return 0;
  375. }
  376. static void i915_ring_seqno_info(struct seq_file *m,
  377. struct intel_ring_buffer *ring)
  378. {
  379. if (ring->get_seqno) {
  380. seq_printf(m, "Current sequence (%s): %d\n",
  381. ring->name, ring->get_seqno(ring));
  382. seq_printf(m, "Waiter sequence (%s): %d\n",
  383. ring->name, ring->waiting_seqno);
  384. seq_printf(m, "IRQ sequence (%s): %d\n",
  385. ring->name, ring->irq_seqno);
  386. }
  387. }
  388. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  389. {
  390. struct drm_info_node *node = (struct drm_info_node *) m->private;
  391. struct drm_device *dev = node->minor->dev;
  392. drm_i915_private_t *dev_priv = dev->dev_private;
  393. int ret, i;
  394. ret = mutex_lock_interruptible(&dev->struct_mutex);
  395. if (ret)
  396. return ret;
  397. for (i = 0; i < I915_NUM_RINGS; i++)
  398. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  399. mutex_unlock(&dev->struct_mutex);
  400. return 0;
  401. }
  402. static int i915_interrupt_info(struct seq_file *m, void *data)
  403. {
  404. struct drm_info_node *node = (struct drm_info_node *) m->private;
  405. struct drm_device *dev = node->minor->dev;
  406. drm_i915_private_t *dev_priv = dev->dev_private;
  407. int ret, i, pipe;
  408. ret = mutex_lock_interruptible(&dev->struct_mutex);
  409. if (ret)
  410. return ret;
  411. if (!HAS_PCH_SPLIT(dev)) {
  412. seq_printf(m, "Interrupt enable: %08x\n",
  413. I915_READ(IER));
  414. seq_printf(m, "Interrupt identity: %08x\n",
  415. I915_READ(IIR));
  416. seq_printf(m, "Interrupt mask: %08x\n",
  417. I915_READ(IMR));
  418. for_each_pipe(pipe)
  419. seq_printf(m, "Pipe %c stat: %08x\n",
  420. pipe_name(pipe),
  421. I915_READ(PIPESTAT(pipe)));
  422. } else {
  423. seq_printf(m, "North Display Interrupt enable: %08x\n",
  424. I915_READ(DEIER));
  425. seq_printf(m, "North Display Interrupt identity: %08x\n",
  426. I915_READ(DEIIR));
  427. seq_printf(m, "North Display Interrupt mask: %08x\n",
  428. I915_READ(DEIMR));
  429. seq_printf(m, "South Display Interrupt enable: %08x\n",
  430. I915_READ(SDEIER));
  431. seq_printf(m, "South Display Interrupt identity: %08x\n",
  432. I915_READ(SDEIIR));
  433. seq_printf(m, "South Display Interrupt mask: %08x\n",
  434. I915_READ(SDEIMR));
  435. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  436. I915_READ(GTIER));
  437. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  438. I915_READ(GTIIR));
  439. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  440. I915_READ(GTIMR));
  441. }
  442. seq_printf(m, "Interrupts received: %d\n",
  443. atomic_read(&dev_priv->irq_received));
  444. for (i = 0; i < I915_NUM_RINGS; i++) {
  445. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  446. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  447. dev_priv->ring[i].name,
  448. I915_READ_IMR(&dev_priv->ring[i]));
  449. }
  450. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  451. }
  452. mutex_unlock(&dev->struct_mutex);
  453. return 0;
  454. }
  455. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  456. {
  457. struct drm_info_node *node = (struct drm_info_node *) m->private;
  458. struct drm_device *dev = node->minor->dev;
  459. drm_i915_private_t *dev_priv = dev->dev_private;
  460. int i, ret;
  461. ret = mutex_lock_interruptible(&dev->struct_mutex);
  462. if (ret)
  463. return ret;
  464. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  465. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  466. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  467. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  468. seq_printf(m, "Fenced object[%2d] = ", i);
  469. if (obj == NULL)
  470. seq_printf(m, "unused");
  471. else
  472. describe_obj(m, obj);
  473. seq_printf(m, "\n");
  474. }
  475. mutex_unlock(&dev->struct_mutex);
  476. return 0;
  477. }
  478. static int i915_hws_info(struct seq_file *m, void *data)
  479. {
  480. struct drm_info_node *node = (struct drm_info_node *) m->private;
  481. struct drm_device *dev = node->minor->dev;
  482. drm_i915_private_t *dev_priv = dev->dev_private;
  483. struct intel_ring_buffer *ring;
  484. const volatile u32 __iomem *hws;
  485. int i;
  486. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  487. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  488. if (hws == NULL)
  489. return 0;
  490. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  491. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  492. i * 4,
  493. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  494. }
  495. return 0;
  496. }
  497. static void i915_dump_object(struct seq_file *m,
  498. struct io_mapping *mapping,
  499. struct drm_i915_gem_object *obj)
  500. {
  501. int page, page_count, i;
  502. page_count = obj->base.size / PAGE_SIZE;
  503. for (page = 0; page < page_count; page++) {
  504. u32 *mem = io_mapping_map_wc(mapping,
  505. obj->gtt_offset + page * PAGE_SIZE);
  506. for (i = 0; i < PAGE_SIZE; i += 4)
  507. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  508. io_mapping_unmap(mem);
  509. }
  510. }
  511. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  512. {
  513. struct drm_info_node *node = (struct drm_info_node *) m->private;
  514. struct drm_device *dev = node->minor->dev;
  515. drm_i915_private_t *dev_priv = dev->dev_private;
  516. struct drm_i915_gem_object *obj;
  517. int ret;
  518. ret = mutex_lock_interruptible(&dev->struct_mutex);
  519. if (ret)
  520. return ret;
  521. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  522. if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
  523. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  524. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
  525. }
  526. }
  527. mutex_unlock(&dev->struct_mutex);
  528. return 0;
  529. }
  530. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  531. {
  532. struct drm_info_node *node = (struct drm_info_node *) m->private;
  533. struct drm_device *dev = node->minor->dev;
  534. drm_i915_private_t *dev_priv = dev->dev_private;
  535. struct intel_ring_buffer *ring;
  536. int ret;
  537. ret = mutex_lock_interruptible(&dev->struct_mutex);
  538. if (ret)
  539. return ret;
  540. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  541. if (!ring->obj) {
  542. seq_printf(m, "No ringbuffer setup\n");
  543. } else {
  544. const u8 __iomem *virt = ring->virtual_start;
  545. uint32_t off;
  546. for (off = 0; off < ring->size; off += 4) {
  547. uint32_t *ptr = (uint32_t *)(virt + off);
  548. seq_printf(m, "%08x : %08x\n", off, *ptr);
  549. }
  550. }
  551. mutex_unlock(&dev->struct_mutex);
  552. return 0;
  553. }
  554. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  555. {
  556. struct drm_info_node *node = (struct drm_info_node *) m->private;
  557. struct drm_device *dev = node->minor->dev;
  558. drm_i915_private_t *dev_priv = dev->dev_private;
  559. struct intel_ring_buffer *ring;
  560. int ret;
  561. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  562. if (ring->size == 0)
  563. return 0;
  564. ret = mutex_lock_interruptible(&dev->struct_mutex);
  565. if (ret)
  566. return ret;
  567. seq_printf(m, "Ring %s:\n", ring->name);
  568. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  569. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  570. seq_printf(m, " Size : %08x\n", ring->size);
  571. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  572. seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
  573. if (IS_GEN6(dev)) {
  574. seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
  575. seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
  576. }
  577. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  578. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  579. mutex_unlock(&dev->struct_mutex);
  580. return 0;
  581. }
  582. static const char *ring_str(int ring)
  583. {
  584. switch (ring) {
  585. case RING_RENDER: return " render";
  586. case RING_BSD: return " bsd";
  587. case RING_BLT: return " blt";
  588. default: return "";
  589. }
  590. }
  591. static const char *pin_flag(int pinned)
  592. {
  593. if (pinned > 0)
  594. return " P";
  595. else if (pinned < 0)
  596. return " p";
  597. else
  598. return "";
  599. }
  600. static const char *tiling_flag(int tiling)
  601. {
  602. switch (tiling) {
  603. default:
  604. case I915_TILING_NONE: return "";
  605. case I915_TILING_X: return " X";
  606. case I915_TILING_Y: return " Y";
  607. }
  608. }
  609. static const char *dirty_flag(int dirty)
  610. {
  611. return dirty ? " dirty" : "";
  612. }
  613. static const char *purgeable_flag(int purgeable)
  614. {
  615. return purgeable ? " purgeable" : "";
  616. }
  617. static void print_error_buffers(struct seq_file *m,
  618. const char *name,
  619. struct drm_i915_error_buffer *err,
  620. int count)
  621. {
  622. seq_printf(m, "%s [%d]:\n", name, count);
  623. while (count--) {
  624. seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
  625. err->gtt_offset,
  626. err->size,
  627. err->read_domains,
  628. err->write_domain,
  629. err->seqno,
  630. pin_flag(err->pinned),
  631. tiling_flag(err->tiling),
  632. dirty_flag(err->dirty),
  633. purgeable_flag(err->purgeable),
  634. ring_str(err->ring),
  635. cache_level_str(err->cache_level));
  636. if (err->name)
  637. seq_printf(m, " (name: %d)", err->name);
  638. if (err->fence_reg != I915_FENCE_REG_NONE)
  639. seq_printf(m, " (fence: %d)", err->fence_reg);
  640. seq_printf(m, "\n");
  641. err++;
  642. }
  643. }
  644. static int i915_error_state(struct seq_file *m, void *unused)
  645. {
  646. struct drm_info_node *node = (struct drm_info_node *) m->private;
  647. struct drm_device *dev = node->minor->dev;
  648. drm_i915_private_t *dev_priv = dev->dev_private;
  649. struct drm_i915_error_state *error;
  650. unsigned long flags;
  651. int i, page, offset, elt;
  652. spin_lock_irqsave(&dev_priv->error_lock, flags);
  653. if (!dev_priv->first_error) {
  654. seq_printf(m, "no error state collected\n");
  655. goto out;
  656. }
  657. error = dev_priv->first_error;
  658. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  659. error->time.tv_usec);
  660. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  661. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  662. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  663. if (INTEL_INFO(dev)->gen >= 6) {
  664. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  665. seq_printf(m, "Blitter command stream:\n");
  666. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  667. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  668. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  669. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  670. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  671. seq_printf(m, "Video (BSD) command stream:\n");
  672. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  673. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  674. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  675. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  676. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  677. }
  678. seq_printf(m, "Render command stream:\n");
  679. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  680. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  681. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  682. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  683. if (INTEL_INFO(dev)->gen >= 4) {
  684. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  685. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  686. }
  687. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  688. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  689. for (i = 0; i < dev_priv->num_fence_regs; i++)
  690. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  691. if (error->active_bo)
  692. print_error_buffers(m, "Active",
  693. error->active_bo,
  694. error->active_bo_count);
  695. if (error->pinned_bo)
  696. print_error_buffers(m, "Pinned",
  697. error->pinned_bo,
  698. error->pinned_bo_count);
  699. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  700. if (error->batchbuffer[i]) {
  701. struct drm_i915_error_object *obj = error->batchbuffer[i];
  702. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  703. dev_priv->ring[i].name,
  704. obj->gtt_offset);
  705. offset = 0;
  706. for (page = 0; page < obj->page_count; page++) {
  707. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  708. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  709. offset += 4;
  710. }
  711. }
  712. }
  713. }
  714. for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
  715. if (error->ringbuffer[i]) {
  716. struct drm_i915_error_object *obj = error->ringbuffer[i];
  717. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  718. dev_priv->ring[i].name,
  719. obj->gtt_offset);
  720. offset = 0;
  721. for (page = 0; page < obj->page_count; page++) {
  722. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  723. seq_printf(m, "%08x : %08x\n",
  724. offset,
  725. obj->pages[page][elt]);
  726. offset += 4;
  727. }
  728. }
  729. }
  730. }
  731. if (error->overlay)
  732. intel_overlay_print_error_state(m, error->overlay);
  733. if (error->display)
  734. intel_display_print_error_state(m, dev, error->display);
  735. out:
  736. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  737. return 0;
  738. }
  739. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  740. {
  741. struct drm_info_node *node = (struct drm_info_node *) m->private;
  742. struct drm_device *dev = node->minor->dev;
  743. drm_i915_private_t *dev_priv = dev->dev_private;
  744. u16 crstanddelay;
  745. int ret;
  746. ret = mutex_lock_interruptible(&dev->struct_mutex);
  747. if (ret)
  748. return ret;
  749. crstanddelay = I915_READ16(CRSTANDVID);
  750. mutex_unlock(&dev->struct_mutex);
  751. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  752. return 0;
  753. }
  754. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  755. {
  756. struct drm_info_node *node = (struct drm_info_node *) m->private;
  757. struct drm_device *dev = node->minor->dev;
  758. drm_i915_private_t *dev_priv = dev->dev_private;
  759. int ret;
  760. if (IS_GEN5(dev)) {
  761. u16 rgvswctl = I915_READ16(MEMSWCTL);
  762. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  763. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  764. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  765. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  766. MEMSTAT_VID_SHIFT);
  767. seq_printf(m, "Current P-state: %d\n",
  768. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  769. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  770. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  771. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  772. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  773. u32 rpstat;
  774. u32 rpupei, rpcurup, rpprevup;
  775. u32 rpdownei, rpcurdown, rpprevdown;
  776. int max_freq;
  777. /* RPSTAT1 is in the GT power well */
  778. ret = mutex_lock_interruptible(&dev->struct_mutex);
  779. if (ret)
  780. return ret;
  781. gen6_gt_force_wake_get(dev_priv);
  782. rpstat = I915_READ(GEN6_RPSTAT1);
  783. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  784. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  785. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  786. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  787. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  788. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  789. gen6_gt_force_wake_put(dev_priv);
  790. mutex_unlock(&dev->struct_mutex);
  791. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  792. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  793. seq_printf(m, "Render p-state ratio: %d\n",
  794. (gt_perf_status & 0xff00) >> 8);
  795. seq_printf(m, "Render p-state VID: %d\n",
  796. gt_perf_status & 0xff);
  797. seq_printf(m, "Render p-state limit: %d\n",
  798. rp_state_limits & 0xff);
  799. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  800. GEN6_CAGF_SHIFT) * 50);
  801. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  802. GEN6_CURICONT_MASK);
  803. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  804. GEN6_CURBSYTAVG_MASK);
  805. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  806. GEN6_CURBSYTAVG_MASK);
  807. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  808. GEN6_CURIAVG_MASK);
  809. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  810. GEN6_CURBSYTAVG_MASK);
  811. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  812. GEN6_CURBSYTAVG_MASK);
  813. max_freq = (rp_state_cap & 0xff0000) >> 16;
  814. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  815. max_freq * 50);
  816. max_freq = (rp_state_cap & 0xff00) >> 8;
  817. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  818. max_freq * 50);
  819. max_freq = rp_state_cap & 0xff;
  820. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  821. max_freq * 50);
  822. } else {
  823. seq_printf(m, "no P-state info available\n");
  824. }
  825. return 0;
  826. }
  827. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  828. {
  829. struct drm_info_node *node = (struct drm_info_node *) m->private;
  830. struct drm_device *dev = node->minor->dev;
  831. drm_i915_private_t *dev_priv = dev->dev_private;
  832. u32 delayfreq;
  833. int ret, i;
  834. ret = mutex_lock_interruptible(&dev->struct_mutex);
  835. if (ret)
  836. return ret;
  837. for (i = 0; i < 16; i++) {
  838. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  839. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  840. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  841. }
  842. mutex_unlock(&dev->struct_mutex);
  843. return 0;
  844. }
  845. static inline int MAP_TO_MV(int map)
  846. {
  847. return 1250 - (map * 25);
  848. }
  849. static int i915_inttoext_table(struct seq_file *m, void *unused)
  850. {
  851. struct drm_info_node *node = (struct drm_info_node *) m->private;
  852. struct drm_device *dev = node->minor->dev;
  853. drm_i915_private_t *dev_priv = dev->dev_private;
  854. u32 inttoext;
  855. int ret, i;
  856. ret = mutex_lock_interruptible(&dev->struct_mutex);
  857. if (ret)
  858. return ret;
  859. for (i = 1; i <= 32; i++) {
  860. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  861. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  862. }
  863. mutex_unlock(&dev->struct_mutex);
  864. return 0;
  865. }
  866. static int i915_drpc_info(struct seq_file *m, void *unused)
  867. {
  868. struct drm_info_node *node = (struct drm_info_node *) m->private;
  869. struct drm_device *dev = node->minor->dev;
  870. drm_i915_private_t *dev_priv = dev->dev_private;
  871. u32 rgvmodectl, rstdbyctl;
  872. u16 crstandvid;
  873. int ret;
  874. ret = mutex_lock_interruptible(&dev->struct_mutex);
  875. if (ret)
  876. return ret;
  877. rgvmodectl = I915_READ(MEMMODECTL);
  878. rstdbyctl = I915_READ(RSTDBYCTL);
  879. crstandvid = I915_READ16(CRSTANDVID);
  880. mutex_unlock(&dev->struct_mutex);
  881. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  882. "yes" : "no");
  883. seq_printf(m, "Boost freq: %d\n",
  884. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  885. MEMMODE_BOOST_FREQ_SHIFT);
  886. seq_printf(m, "HW control enabled: %s\n",
  887. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  888. seq_printf(m, "SW control enabled: %s\n",
  889. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  890. seq_printf(m, "Gated voltage change: %s\n",
  891. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  892. seq_printf(m, "Starting frequency: P%d\n",
  893. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  894. seq_printf(m, "Max P-state: P%d\n",
  895. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  896. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  897. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  898. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  899. seq_printf(m, "Render standby enabled: %s\n",
  900. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  901. seq_printf(m, "Current RS state: ");
  902. switch (rstdbyctl & RSX_STATUS_MASK) {
  903. case RSX_STATUS_ON:
  904. seq_printf(m, "on\n");
  905. break;
  906. case RSX_STATUS_RC1:
  907. seq_printf(m, "RC1\n");
  908. break;
  909. case RSX_STATUS_RC1E:
  910. seq_printf(m, "RC1E\n");
  911. break;
  912. case RSX_STATUS_RS1:
  913. seq_printf(m, "RS1\n");
  914. break;
  915. case RSX_STATUS_RS2:
  916. seq_printf(m, "RS2 (RC6)\n");
  917. break;
  918. case RSX_STATUS_RS3:
  919. seq_printf(m, "RC3 (RC6+)\n");
  920. break;
  921. default:
  922. seq_printf(m, "unknown\n");
  923. break;
  924. }
  925. return 0;
  926. }
  927. static int i915_fbc_status(struct seq_file *m, void *unused)
  928. {
  929. struct drm_info_node *node = (struct drm_info_node *) m->private;
  930. struct drm_device *dev = node->minor->dev;
  931. drm_i915_private_t *dev_priv = dev->dev_private;
  932. if (!I915_HAS_FBC(dev)) {
  933. seq_printf(m, "FBC unsupported on this chipset\n");
  934. return 0;
  935. }
  936. if (intel_fbc_enabled(dev)) {
  937. seq_printf(m, "FBC enabled\n");
  938. } else {
  939. seq_printf(m, "FBC disabled: ");
  940. switch (dev_priv->no_fbc_reason) {
  941. case FBC_NO_OUTPUT:
  942. seq_printf(m, "no outputs");
  943. break;
  944. case FBC_STOLEN_TOO_SMALL:
  945. seq_printf(m, "not enough stolen memory");
  946. break;
  947. case FBC_UNSUPPORTED_MODE:
  948. seq_printf(m, "mode not supported");
  949. break;
  950. case FBC_MODE_TOO_LARGE:
  951. seq_printf(m, "mode too large");
  952. break;
  953. case FBC_BAD_PLANE:
  954. seq_printf(m, "FBC unsupported on plane");
  955. break;
  956. case FBC_NOT_TILED:
  957. seq_printf(m, "scanout buffer not tiled");
  958. break;
  959. case FBC_MULTIPLE_PIPES:
  960. seq_printf(m, "multiple pipes are enabled");
  961. break;
  962. case FBC_MODULE_PARAM:
  963. seq_printf(m, "disabled per module param (default off)");
  964. break;
  965. default:
  966. seq_printf(m, "unknown reason");
  967. }
  968. seq_printf(m, "\n");
  969. }
  970. return 0;
  971. }
  972. static int i915_sr_status(struct seq_file *m, void *unused)
  973. {
  974. struct drm_info_node *node = (struct drm_info_node *) m->private;
  975. struct drm_device *dev = node->minor->dev;
  976. drm_i915_private_t *dev_priv = dev->dev_private;
  977. bool sr_enabled = false;
  978. if (HAS_PCH_SPLIT(dev))
  979. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  980. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  981. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  982. else if (IS_I915GM(dev))
  983. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  984. else if (IS_PINEVIEW(dev))
  985. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  986. seq_printf(m, "self-refresh: %s\n",
  987. sr_enabled ? "enabled" : "disabled");
  988. return 0;
  989. }
  990. static int i915_emon_status(struct seq_file *m, void *unused)
  991. {
  992. struct drm_info_node *node = (struct drm_info_node *) m->private;
  993. struct drm_device *dev = node->minor->dev;
  994. drm_i915_private_t *dev_priv = dev->dev_private;
  995. unsigned long temp, chipset, gfx;
  996. int ret;
  997. ret = mutex_lock_interruptible(&dev->struct_mutex);
  998. if (ret)
  999. return ret;
  1000. temp = i915_mch_val(dev_priv);
  1001. chipset = i915_chipset_val(dev_priv);
  1002. gfx = i915_gfx_val(dev_priv);
  1003. mutex_unlock(&dev->struct_mutex);
  1004. seq_printf(m, "GMCH temp: %ld\n", temp);
  1005. seq_printf(m, "Chipset power: %ld\n", chipset);
  1006. seq_printf(m, "GFX power: %ld\n", gfx);
  1007. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1008. return 0;
  1009. }
  1010. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1011. {
  1012. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1013. struct drm_device *dev = node->minor->dev;
  1014. drm_i915_private_t *dev_priv = dev->dev_private;
  1015. int ret;
  1016. int gpu_freq, ia_freq;
  1017. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1018. seq_printf(m, "unsupported on this chipset\n");
  1019. return 0;
  1020. }
  1021. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1022. if (ret)
  1023. return ret;
  1024. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1025. for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
  1026. gpu_freq++) {
  1027. I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
  1028. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  1029. GEN6_PCODE_READ_MIN_FREQ_TABLE);
  1030. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  1031. GEN6_PCODE_READY) == 0, 10)) {
  1032. DRM_ERROR("pcode read of freq table timed out\n");
  1033. continue;
  1034. }
  1035. ia_freq = I915_READ(GEN6_PCODE_DATA);
  1036. seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
  1037. }
  1038. mutex_unlock(&dev->struct_mutex);
  1039. return 0;
  1040. }
  1041. static int i915_gfxec(struct seq_file *m, void *unused)
  1042. {
  1043. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1044. struct drm_device *dev = node->minor->dev;
  1045. drm_i915_private_t *dev_priv = dev->dev_private;
  1046. int ret;
  1047. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1048. if (ret)
  1049. return ret;
  1050. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1051. mutex_unlock(&dev->struct_mutex);
  1052. return 0;
  1053. }
  1054. static int i915_opregion(struct seq_file *m, void *unused)
  1055. {
  1056. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1057. struct drm_device *dev = node->minor->dev;
  1058. drm_i915_private_t *dev_priv = dev->dev_private;
  1059. struct intel_opregion *opregion = &dev_priv->opregion;
  1060. int ret;
  1061. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1062. if (ret)
  1063. return ret;
  1064. if (opregion->header)
  1065. seq_write(m, opregion->header, OPREGION_SIZE);
  1066. mutex_unlock(&dev->struct_mutex);
  1067. return 0;
  1068. }
  1069. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1070. {
  1071. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1072. struct drm_device *dev = node->minor->dev;
  1073. drm_i915_private_t *dev_priv = dev->dev_private;
  1074. struct intel_fbdev *ifbdev;
  1075. struct intel_framebuffer *fb;
  1076. int ret;
  1077. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1078. if (ret)
  1079. return ret;
  1080. ifbdev = dev_priv->fbdev;
  1081. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1082. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1083. fb->base.width,
  1084. fb->base.height,
  1085. fb->base.depth,
  1086. fb->base.bits_per_pixel);
  1087. describe_obj(m, fb->obj);
  1088. seq_printf(m, "\n");
  1089. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1090. if (&fb->base == ifbdev->helper.fb)
  1091. continue;
  1092. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1093. fb->base.width,
  1094. fb->base.height,
  1095. fb->base.depth,
  1096. fb->base.bits_per_pixel);
  1097. describe_obj(m, fb->obj);
  1098. seq_printf(m, "\n");
  1099. }
  1100. mutex_unlock(&dev->mode_config.mutex);
  1101. return 0;
  1102. }
  1103. static int i915_context_status(struct seq_file *m, void *unused)
  1104. {
  1105. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1106. struct drm_device *dev = node->minor->dev;
  1107. drm_i915_private_t *dev_priv = dev->dev_private;
  1108. int ret;
  1109. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1110. if (ret)
  1111. return ret;
  1112. if (dev_priv->pwrctx) {
  1113. seq_printf(m, "power context ");
  1114. describe_obj(m, dev_priv->pwrctx);
  1115. seq_printf(m, "\n");
  1116. }
  1117. if (dev_priv->renderctx) {
  1118. seq_printf(m, "render context ");
  1119. describe_obj(m, dev_priv->renderctx);
  1120. seq_printf(m, "\n");
  1121. }
  1122. mutex_unlock(&dev->mode_config.mutex);
  1123. return 0;
  1124. }
  1125. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1126. {
  1127. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1128. struct drm_device *dev = node->minor->dev;
  1129. struct drm_i915_private *dev_priv = dev->dev_private;
  1130. seq_printf(m, "forcewake count = %d\n",
  1131. atomic_read(&dev_priv->forcewake_count));
  1132. return 0;
  1133. }
  1134. static int
  1135. i915_wedged_open(struct inode *inode,
  1136. struct file *filp)
  1137. {
  1138. filp->private_data = inode->i_private;
  1139. return 0;
  1140. }
  1141. static ssize_t
  1142. i915_wedged_read(struct file *filp,
  1143. char __user *ubuf,
  1144. size_t max,
  1145. loff_t *ppos)
  1146. {
  1147. struct drm_device *dev = filp->private_data;
  1148. drm_i915_private_t *dev_priv = dev->dev_private;
  1149. char buf[80];
  1150. int len;
  1151. len = snprintf(buf, sizeof(buf),
  1152. "wedged : %d\n",
  1153. atomic_read(&dev_priv->mm.wedged));
  1154. if (len > sizeof(buf))
  1155. len = sizeof(buf);
  1156. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1157. }
  1158. static ssize_t
  1159. i915_wedged_write(struct file *filp,
  1160. const char __user *ubuf,
  1161. size_t cnt,
  1162. loff_t *ppos)
  1163. {
  1164. struct drm_device *dev = filp->private_data;
  1165. char buf[20];
  1166. int val = 1;
  1167. if (cnt > 0) {
  1168. if (cnt > sizeof(buf) - 1)
  1169. return -EINVAL;
  1170. if (copy_from_user(buf, ubuf, cnt))
  1171. return -EFAULT;
  1172. buf[cnt] = 0;
  1173. val = simple_strtoul(buf, NULL, 0);
  1174. }
  1175. DRM_INFO("Manually setting wedged to %d\n", val);
  1176. i915_handle_error(dev, val);
  1177. return cnt;
  1178. }
  1179. static const struct file_operations i915_wedged_fops = {
  1180. .owner = THIS_MODULE,
  1181. .open = i915_wedged_open,
  1182. .read = i915_wedged_read,
  1183. .write = i915_wedged_write,
  1184. .llseek = default_llseek,
  1185. };
  1186. static int
  1187. i915_max_freq_open(struct inode *inode,
  1188. struct file *filp)
  1189. {
  1190. filp->private_data = inode->i_private;
  1191. return 0;
  1192. }
  1193. static ssize_t
  1194. i915_max_freq_read(struct file *filp,
  1195. char __user *ubuf,
  1196. size_t max,
  1197. loff_t *ppos)
  1198. {
  1199. struct drm_device *dev = filp->private_data;
  1200. drm_i915_private_t *dev_priv = dev->dev_private;
  1201. char buf[80];
  1202. int len;
  1203. len = snprintf(buf, sizeof(buf),
  1204. "max freq: %d\n", dev_priv->max_delay * 50);
  1205. if (len > sizeof(buf))
  1206. len = sizeof(buf);
  1207. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1208. }
  1209. static ssize_t
  1210. i915_max_freq_write(struct file *filp,
  1211. const char __user *ubuf,
  1212. size_t cnt,
  1213. loff_t *ppos)
  1214. {
  1215. struct drm_device *dev = filp->private_data;
  1216. struct drm_i915_private *dev_priv = dev->dev_private;
  1217. char buf[20];
  1218. int val = 1;
  1219. if (cnt > 0) {
  1220. if (cnt > sizeof(buf) - 1)
  1221. return -EINVAL;
  1222. if (copy_from_user(buf, ubuf, cnt))
  1223. return -EFAULT;
  1224. buf[cnt] = 0;
  1225. val = simple_strtoul(buf, NULL, 0);
  1226. }
  1227. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1228. /*
  1229. * Turbo will still be enabled, but won't go above the set value.
  1230. */
  1231. dev_priv->max_delay = val / 50;
  1232. gen6_set_rps(dev, val / 50);
  1233. return cnt;
  1234. }
  1235. static const struct file_operations i915_max_freq_fops = {
  1236. .owner = THIS_MODULE,
  1237. .open = i915_max_freq_open,
  1238. .read = i915_max_freq_read,
  1239. .write = i915_max_freq_write,
  1240. .llseek = default_llseek,
  1241. };
  1242. static int
  1243. i915_cache_sharing_open(struct inode *inode,
  1244. struct file *filp)
  1245. {
  1246. filp->private_data = inode->i_private;
  1247. return 0;
  1248. }
  1249. static ssize_t
  1250. i915_cache_sharing_read(struct file *filp,
  1251. char __user *ubuf,
  1252. size_t max,
  1253. loff_t *ppos)
  1254. {
  1255. struct drm_device *dev = filp->private_data;
  1256. drm_i915_private_t *dev_priv = dev->dev_private;
  1257. char buf[80];
  1258. u32 snpcr;
  1259. int len;
  1260. mutex_lock(&dev_priv->dev->struct_mutex);
  1261. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1262. mutex_unlock(&dev_priv->dev->struct_mutex);
  1263. len = snprintf(buf, sizeof(buf),
  1264. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1265. GEN6_MBC_SNPCR_SHIFT);
  1266. if (len > sizeof(buf))
  1267. len = sizeof(buf);
  1268. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1269. }
  1270. static ssize_t
  1271. i915_cache_sharing_write(struct file *filp,
  1272. const char __user *ubuf,
  1273. size_t cnt,
  1274. loff_t *ppos)
  1275. {
  1276. struct drm_device *dev = filp->private_data;
  1277. struct drm_i915_private *dev_priv = dev->dev_private;
  1278. char buf[20];
  1279. u32 snpcr;
  1280. int val = 1;
  1281. if (cnt > 0) {
  1282. if (cnt > sizeof(buf) - 1)
  1283. return -EINVAL;
  1284. if (copy_from_user(buf, ubuf, cnt))
  1285. return -EFAULT;
  1286. buf[cnt] = 0;
  1287. val = simple_strtoul(buf, NULL, 0);
  1288. }
  1289. if (val < 0 || val > 3)
  1290. return -EINVAL;
  1291. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1292. /* Update the cache sharing policy here as well */
  1293. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1294. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1295. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1296. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1297. return cnt;
  1298. }
  1299. static const struct file_operations i915_cache_sharing_fops = {
  1300. .owner = THIS_MODULE,
  1301. .open = i915_cache_sharing_open,
  1302. .read = i915_cache_sharing_read,
  1303. .write = i915_cache_sharing_write,
  1304. .llseek = default_llseek,
  1305. };
  1306. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1307. * allocated we need to hook into the minor for release. */
  1308. static int
  1309. drm_add_fake_info_node(struct drm_minor *minor,
  1310. struct dentry *ent,
  1311. const void *key)
  1312. {
  1313. struct drm_info_node *node;
  1314. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1315. if (node == NULL) {
  1316. debugfs_remove(ent);
  1317. return -ENOMEM;
  1318. }
  1319. node->minor = minor;
  1320. node->dent = ent;
  1321. node->info_ent = (void *) key;
  1322. mutex_lock(&minor->debugfs_lock);
  1323. list_add(&node->list, &minor->debugfs_list);
  1324. mutex_unlock(&minor->debugfs_lock);
  1325. return 0;
  1326. }
  1327. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  1328. {
  1329. struct drm_device *dev = minor->dev;
  1330. struct dentry *ent;
  1331. ent = debugfs_create_file("i915_wedged",
  1332. S_IRUGO | S_IWUSR,
  1333. root, dev,
  1334. &i915_wedged_fops);
  1335. if (IS_ERR(ent))
  1336. return PTR_ERR(ent);
  1337. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  1338. }
  1339. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1340. {
  1341. struct drm_device *dev = inode->i_private;
  1342. struct drm_i915_private *dev_priv = dev->dev_private;
  1343. int ret;
  1344. if (!IS_GEN6(dev))
  1345. return 0;
  1346. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1347. if (ret)
  1348. return ret;
  1349. gen6_gt_force_wake_get(dev_priv);
  1350. mutex_unlock(&dev->struct_mutex);
  1351. return 0;
  1352. }
  1353. int i915_forcewake_release(struct inode *inode, struct file *file)
  1354. {
  1355. struct drm_device *dev = inode->i_private;
  1356. struct drm_i915_private *dev_priv = dev->dev_private;
  1357. if (!IS_GEN6(dev))
  1358. return 0;
  1359. /*
  1360. * It's bad that we can potentially hang userspace if struct_mutex gets
  1361. * forever stuck. However, if we cannot acquire this lock it means that
  1362. * almost certainly the driver has hung, is not unload-able. Therefore
  1363. * hanging here is probably a minor inconvenience not to be seen my
  1364. * almost every user.
  1365. */
  1366. mutex_lock(&dev->struct_mutex);
  1367. gen6_gt_force_wake_put(dev_priv);
  1368. mutex_unlock(&dev->struct_mutex);
  1369. return 0;
  1370. }
  1371. static const struct file_operations i915_forcewake_fops = {
  1372. .owner = THIS_MODULE,
  1373. .open = i915_forcewake_open,
  1374. .release = i915_forcewake_release,
  1375. };
  1376. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1377. {
  1378. struct drm_device *dev = minor->dev;
  1379. struct dentry *ent;
  1380. ent = debugfs_create_file("i915_forcewake_user",
  1381. S_IRUSR,
  1382. root, dev,
  1383. &i915_forcewake_fops);
  1384. if (IS_ERR(ent))
  1385. return PTR_ERR(ent);
  1386. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1387. }
  1388. static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
  1389. {
  1390. struct drm_device *dev = minor->dev;
  1391. struct dentry *ent;
  1392. ent = debugfs_create_file("i915_max_freq",
  1393. S_IRUGO | S_IWUSR,
  1394. root, dev,
  1395. &i915_max_freq_fops);
  1396. if (IS_ERR(ent))
  1397. return PTR_ERR(ent);
  1398. return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
  1399. }
  1400. static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor)
  1401. {
  1402. struct drm_device *dev = minor->dev;
  1403. struct dentry *ent;
  1404. ent = debugfs_create_file("i915_cache_sharing",
  1405. S_IRUGO | S_IWUSR,
  1406. root, dev,
  1407. &i915_cache_sharing_fops);
  1408. if (IS_ERR(ent))
  1409. return PTR_ERR(ent);
  1410. return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops);
  1411. }
  1412. static struct drm_info_list i915_debugfs_list[] = {
  1413. {"i915_capabilities", i915_capabilities, 0},
  1414. {"i915_gem_objects", i915_gem_object_info, 0},
  1415. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1416. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1417. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  1418. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1419. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  1420. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  1421. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1422. {"i915_gem_request", i915_gem_request_info, 0},
  1423. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1424. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1425. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1426. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1427. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1428. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1429. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
  1430. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
  1431. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
  1432. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
  1433. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
  1434. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
  1435. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  1436. {"i915_error_state", i915_error_state, 0},
  1437. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1438. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1439. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1440. {"i915_inttoext_table", i915_inttoext_table, 0},
  1441. {"i915_drpc_info", i915_drpc_info, 0},
  1442. {"i915_emon_status", i915_emon_status, 0},
  1443. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1444. {"i915_gfxec", i915_gfxec, 0},
  1445. {"i915_fbc_status", i915_fbc_status, 0},
  1446. {"i915_sr_status", i915_sr_status, 0},
  1447. {"i915_opregion", i915_opregion, 0},
  1448. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1449. {"i915_context_status", i915_context_status, 0},
  1450. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1451. };
  1452. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1453. int i915_debugfs_init(struct drm_minor *minor)
  1454. {
  1455. int ret;
  1456. ret = i915_wedged_create(minor->debugfs_root, minor);
  1457. if (ret)
  1458. return ret;
  1459. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1460. if (ret)
  1461. return ret;
  1462. ret = i915_max_freq_create(minor->debugfs_root, minor);
  1463. if (ret)
  1464. return ret;
  1465. ret = i915_cache_sharing_create(minor->debugfs_root, minor);
  1466. if (ret)
  1467. return ret;
  1468. return drm_debugfs_create_files(i915_debugfs_list,
  1469. I915_DEBUGFS_ENTRIES,
  1470. minor->debugfs_root, minor);
  1471. }
  1472. void i915_debugfs_cleanup(struct drm_minor *minor)
  1473. {
  1474. drm_debugfs_remove_files(i915_debugfs_list,
  1475. I915_DEBUGFS_ENTRIES, minor);
  1476. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1477. 1, minor);
  1478. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1479. 1, minor);
  1480. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1481. 1, minor);
  1482. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1483. 1, minor);
  1484. }
  1485. #endif /* CONFIG_DEBUG_FS */