hw.c 75 KB

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  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #include "via-core.h"
  19. #include "global.h"
  20. static struct pll_map pll_value[] = {
  21. {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  22. CX700_25_175M, VX855_25_175M},
  23. {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  24. CX700_29_581M, VX855_29_581M},
  25. {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  26. CX700_26_880M, VX855_26_880M},
  27. {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  28. CX700_31_490M, VX855_31_490M},
  29. {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  30. CX700_31_500M, VX855_31_500M},
  31. {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  32. CX700_31_728M, VX855_31_728M},
  33. {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  34. CX700_32_668M, VX855_32_668M},
  35. {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  36. CX700_36_000M, VX855_36_000M},
  37. {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  38. CX700_40_000M, VX855_40_000M},
  39. {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  40. CX700_41_291M, VX855_41_291M},
  41. {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  42. CX700_43_163M, VX855_43_163M},
  43. {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  44. CX700_45_250M, VX855_45_250M},
  45. {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  46. CX700_46_000M, VX855_46_000M},
  47. {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  48. CX700_46_996M, VX855_46_996M},
  49. {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  50. CX700_48_000M, VX855_48_000M},
  51. {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  52. CX700_48_875M, VX855_48_875M},
  53. {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  54. CX700_49_500M, VX855_49_500M},
  55. {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  56. CX700_52_406M, VX855_52_406M},
  57. {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  58. CX700_52_977M, VX855_52_977M},
  59. {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  60. CX700_56_250M, VX855_56_250M},
  61. {CLK_57_275M, 0, 0, 0, VX855_57_275M},
  62. {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  63. CX700_60_466M, VX855_60_466M},
  64. {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  65. CX700_61_500M, VX855_61_500M},
  66. {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  67. CX700_65_000M, VX855_65_000M},
  68. {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  69. CX700_65_178M, VX855_65_178M},
  70. {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  71. CX700_66_750M, VX855_66_750M},
  72. {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  73. CX700_68_179M, VX855_68_179M},
  74. {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  75. CX700_69_924M, VX855_69_924M},
  76. {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  77. CX700_70_159M, VX855_70_159M},
  78. {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  79. CX700_72_000M, VX855_72_000M},
  80. {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  81. CX700_78_750M, VX855_78_750M},
  82. {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  83. CX700_80_136M, VX855_80_136M},
  84. {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  85. CX700_83_375M, VX855_83_375M},
  86. {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  87. CX700_83_950M, VX855_83_950M},
  88. {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  89. CX700_84_750M, VX855_84_750M},
  90. {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  91. CX700_85_860M, VX855_85_860M},
  92. {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  93. CX700_88_750M, VX855_88_750M},
  94. {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  95. CX700_94_500M, VX855_94_500M},
  96. {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
  97. CX700_97_750M, VX855_97_750M},
  98. {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
  99. CX700_101_000M, VX855_101_000M},
  100. {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
  101. CX700_106_500M, VX855_106_500M},
  102. {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
  103. CX700_108_000M, VX855_108_000M},
  104. {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
  105. CX700_113_309M, VX855_113_309M},
  106. {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
  107. CX700_118_840M, VX855_118_840M},
  108. {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
  109. CX700_119_000M, VX855_119_000M},
  110. {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
  111. CX700_121_750M, 0},
  112. {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
  113. CX700_125_104M, 0},
  114. {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
  115. CX700_133_308M, 0},
  116. {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
  117. CX700_135_000M, VX855_135_000M},
  118. {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
  119. CX700_136_700M, VX855_136_700M},
  120. {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
  121. CX700_138_400M, VX855_138_400M},
  122. {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
  123. CX700_146_760M, VX855_146_760M},
  124. {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
  125. CX700_153_920M, VX855_153_920M},
  126. {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
  127. CX700_156_000M, VX855_156_000M},
  128. {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
  129. CX700_157_500M, VX855_157_500M},
  130. {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
  131. CX700_162_000M, VX855_162_000M},
  132. {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
  133. CX700_187_000M, VX855_187_000M},
  134. {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
  135. CX700_193_295M, VX855_193_295M},
  136. {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
  137. CX700_202_500M, VX855_202_500M},
  138. {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
  139. CX700_204_000M, VX855_204_000M},
  140. {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
  141. CX700_218_500M, VX855_218_500M},
  142. {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
  143. CX700_234_000M, VX855_234_000M},
  144. {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
  145. CX700_267_250M, VX855_267_250M},
  146. {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
  147. CX700_297_500M, VX855_297_500M},
  148. {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
  149. CX700_74_481M, VX855_74_481M},
  150. {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
  151. CX700_172_798M, VX855_172_798M},
  152. {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
  153. CX700_122_614M, VX855_122_614M},
  154. {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
  155. CX700_74_270M, 0},
  156. {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
  157. CX700_148_500M, VX855_148_500M}
  158. };
  159. static struct fifo_depth_select display_fifo_depth_reg = {
  160. /* IGA1 FIFO Depth_Select */
  161. {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
  162. /* IGA2 FIFO Depth_Select */
  163. {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
  164. {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
  165. };
  166. static struct fifo_threshold_select fifo_threshold_select_reg = {
  167. /* IGA1 FIFO Threshold Select */
  168. {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
  169. /* IGA2 FIFO Threshold Select */
  170. {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
  171. };
  172. static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
  173. /* IGA1 FIFO High Threshold Select */
  174. {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
  175. /* IGA2 FIFO High Threshold Select */
  176. {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
  177. };
  178. static struct display_queue_expire_num display_queue_expire_num_reg = {
  179. /* IGA1 Display Queue Expire Num */
  180. {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
  181. /* IGA2 Display Queue Expire Num */
  182. {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
  183. };
  184. /* Definition Fetch Count Registers*/
  185. static struct fetch_count fetch_count_reg = {
  186. /* IGA1 Fetch Count Register */
  187. {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
  188. /* IGA2 Fetch Count Register */
  189. {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
  190. };
  191. static struct iga1_crtc_timing iga1_crtc_reg = {
  192. /* IGA1 Horizontal Total */
  193. {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
  194. /* IGA1 Horizontal Addressable Video */
  195. {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
  196. /* IGA1 Horizontal Blank Start */
  197. {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
  198. /* IGA1 Horizontal Blank End */
  199. {IGA1_HOR_BLANK_END_REG_NUM,
  200. {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
  201. /* IGA1 Horizontal Sync Start */
  202. {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
  203. /* IGA1 Horizontal Sync End */
  204. {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
  205. /* IGA1 Vertical Total */
  206. {IGA1_VER_TOTAL_REG_NUM,
  207. {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
  208. /* IGA1 Vertical Addressable Video */
  209. {IGA1_VER_ADDR_REG_NUM,
  210. {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
  211. /* IGA1 Vertical Blank Start */
  212. {IGA1_VER_BLANK_START_REG_NUM,
  213. {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
  214. /* IGA1 Vertical Blank End */
  215. {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
  216. /* IGA1 Vertical Sync Start */
  217. {IGA1_VER_SYNC_START_REG_NUM,
  218. {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
  219. /* IGA1 Vertical Sync End */
  220. {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
  221. };
  222. static struct iga2_crtc_timing iga2_crtc_reg = {
  223. /* IGA2 Horizontal Total */
  224. {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
  225. /* IGA2 Horizontal Addressable Video */
  226. {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
  227. /* IGA2 Horizontal Blank Start */
  228. {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
  229. /* IGA2 Horizontal Blank End */
  230. {IGA2_HOR_BLANK_END_REG_NUM,
  231. {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
  232. /* IGA2 Horizontal Sync Start */
  233. {IGA2_HOR_SYNC_START_REG_NUM,
  234. {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
  235. /* IGA2 Horizontal Sync End */
  236. {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
  237. /* IGA2 Vertical Total */
  238. {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
  239. /* IGA2 Vertical Addressable Video */
  240. {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
  241. /* IGA2 Vertical Blank Start */
  242. {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
  243. /* IGA2 Vertical Blank End */
  244. {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
  245. /* IGA2 Vertical Sync Start */
  246. {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
  247. /* IGA2 Vertical Sync End */
  248. {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
  249. };
  250. static struct rgbLUT palLUT_table[] = {
  251. /* {R,G,B} */
  252. /* Index 0x00~0x03 */
  253. {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
  254. 0x2A,
  255. 0x2A},
  256. /* Index 0x04~0x07 */
  257. {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
  258. 0x2A,
  259. 0x2A},
  260. /* Index 0x08~0x0B */
  261. {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
  262. 0x3F,
  263. 0x3F},
  264. /* Index 0x0C~0x0F */
  265. {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
  266. 0x3F,
  267. 0x3F},
  268. /* Index 0x10~0x13 */
  269. {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
  270. 0x0B,
  271. 0x0B},
  272. /* Index 0x14~0x17 */
  273. {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
  274. 0x18,
  275. 0x18},
  276. /* Index 0x18~0x1B */
  277. {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
  278. 0x28,
  279. 0x28},
  280. /* Index 0x1C~0x1F */
  281. {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
  282. 0x3F,
  283. 0x3F},
  284. /* Index 0x20~0x23 */
  285. {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
  286. 0x00,
  287. 0x3F},
  288. /* Index 0x24~0x27 */
  289. {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
  290. 0x00,
  291. 0x10},
  292. /* Index 0x28~0x2B */
  293. {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
  294. 0x2F,
  295. 0x00},
  296. /* Index 0x2C~0x2F */
  297. {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
  298. 0x3F,
  299. 0x00},
  300. /* Index 0x30~0x33 */
  301. {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
  302. 0x3F,
  303. 0x2F},
  304. /* Index 0x34~0x37 */
  305. {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
  306. 0x10,
  307. 0x3F},
  308. /* Index 0x38~0x3B */
  309. {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
  310. 0x1F,
  311. 0x3F},
  312. /* Index 0x3C~0x3F */
  313. {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
  314. 0x1F,
  315. 0x27},
  316. /* Index 0x40~0x43 */
  317. {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
  318. 0x3F,
  319. 0x1F},
  320. /* Index 0x44~0x47 */
  321. {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
  322. 0x3F,
  323. 0x1F},
  324. /* Index 0x48~0x4B */
  325. {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
  326. 0x3F,
  327. 0x37},
  328. /* Index 0x4C~0x4F */
  329. {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
  330. 0x27,
  331. 0x3F},
  332. /* Index 0x50~0x53 */
  333. {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
  334. 0x2D,
  335. 0x3F},
  336. /* Index 0x54~0x57 */
  337. {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
  338. 0x2D,
  339. 0x31},
  340. /* Index 0x58~0x5B */
  341. {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
  342. 0x3A,
  343. 0x2D},
  344. /* Index 0x5C~0x5F */
  345. {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
  346. 0x3F,
  347. 0x2D},
  348. /* Index 0x60~0x63 */
  349. {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
  350. 0x3F,
  351. 0x3A},
  352. /* Index 0x64~0x67 */
  353. {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
  354. 0x31,
  355. 0x3F},
  356. /* Index 0x68~0x6B */
  357. {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
  358. 0x00,
  359. 0x1C},
  360. /* Index 0x6C~0x6F */
  361. {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
  362. 0x00,
  363. 0x07},
  364. /* Index 0x70~0x73 */
  365. {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
  366. 0x15,
  367. 0x00},
  368. /* Index 0x74~0x77 */
  369. {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
  370. 0x1C,
  371. 0x00},
  372. /* Index 0x78~0x7B */
  373. {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
  374. 0x1C,
  375. 0x15},
  376. /* Index 0x7C~0x7F */
  377. {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
  378. 0x07,
  379. 0x1C},
  380. /* Index 0x80~0x83 */
  381. {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
  382. 0x0E,
  383. 0x1C},
  384. /* Index 0x84~0x87 */
  385. {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
  386. 0x0E,
  387. 0x11},
  388. /* Index 0x88~0x8B */
  389. {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
  390. 0x18,
  391. 0x0E},
  392. /* Index 0x8C~0x8F */
  393. {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
  394. 0x1C,
  395. 0x0E},
  396. /* Index 0x90~0x93 */
  397. {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
  398. 0x1C,
  399. 0x18},
  400. /* Index 0x94~0x97 */
  401. {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
  402. 0x11,
  403. 0x1C},
  404. /* Index 0x98~0x9B */
  405. {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
  406. 0x14,
  407. 0x1C},
  408. /* Index 0x9C~0x9F */
  409. {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
  410. 0x14,
  411. 0x16},
  412. /* Index 0xA0~0xA3 */
  413. {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
  414. 0x1A,
  415. 0x14},
  416. /* Index 0xA4~0xA7 */
  417. {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
  418. 0x1C,
  419. 0x14},
  420. /* Index 0xA8~0xAB */
  421. {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
  422. 0x1C,
  423. 0x1A},
  424. /* Index 0xAC~0xAF */
  425. {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
  426. 0x16,
  427. 0x1C},
  428. /* Index 0xB0~0xB3 */
  429. {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
  430. 0x00,
  431. 0x10},
  432. /* Index 0xB4~0xB7 */
  433. {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
  434. 0x00,
  435. 0x04},
  436. /* Index 0xB8~0xBB */
  437. {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
  438. 0x0C,
  439. 0x00},
  440. /* Index 0xBC~0xBF */
  441. {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
  442. 0x10,
  443. 0x00},
  444. /* Index 0xC0~0xC3 */
  445. {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
  446. 0x10,
  447. 0x0C},
  448. /* Index 0xC4~0xC7 */
  449. {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
  450. 0x04,
  451. 0x10},
  452. /* Index 0xC8~0xCB */
  453. {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
  454. 0x08,
  455. 0x10},
  456. /* Index 0xCC~0xCF */
  457. {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
  458. 0x08,
  459. 0x0A},
  460. /* Index 0xD0~0xD3 */
  461. {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
  462. 0x0E,
  463. 0x08},
  464. /* Index 0xD4~0xD7 */
  465. {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
  466. 0x10,
  467. 0x08},
  468. /* Index 0xD8~0xDB */
  469. {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
  470. 0x10,
  471. 0x0E},
  472. /* Index 0xDC~0xDF */
  473. {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
  474. 0x0A,
  475. 0x10},
  476. /* Index 0xE0~0xE3 */
  477. {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
  478. 0x0B,
  479. 0x10},
  480. /* Index 0xE4~0xE7 */
  481. {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
  482. 0x0B,
  483. 0x0C},
  484. /* Index 0xE8~0xEB */
  485. {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
  486. 0x0F,
  487. 0x0B},
  488. /* Index 0xEC~0xEF */
  489. {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
  490. 0x10,
  491. 0x0B},
  492. /* Index 0xF0~0xF3 */
  493. {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
  494. 0x10,
  495. 0x0F},
  496. /* Index 0xF4~0xF7 */
  497. {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
  498. 0x0C,
  499. 0x10},
  500. /* Index 0xF8~0xFB */
  501. {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
  502. 0x00,
  503. 0x00},
  504. /* Index 0xFC~0xFF */
  505. {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
  506. 0x00,
  507. 0x00}
  508. };
  509. static void set_crt_output_path(int set_iga);
  510. static void dvi_patch_skew_dvp0(void);
  511. static void dvi_patch_skew_dvp1(void);
  512. static void dvi_patch_skew_dvp_low(void);
  513. static void set_dvi_output_path(int set_iga, int output_interface);
  514. static void set_lcd_output_path(int set_iga, int output_interface);
  515. static void load_fix_bit_crtc_reg(void);
  516. static void init_gfx_chip_info(int chip_type);
  517. static void init_tmds_chip_info(void);
  518. static void init_lvds_chip_info(void);
  519. static void device_screen_off(void);
  520. static void device_screen_on(void);
  521. static void set_display_channel(void);
  522. static void device_off(void);
  523. static void device_on(void);
  524. static void enable_second_display_channel(void);
  525. static void disable_second_display_channel(void);
  526. void viafb_write_reg(u8 index, u16 io_port, u8 data)
  527. {
  528. outb(index, io_port);
  529. outb(data, io_port + 1);
  530. /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
  531. }
  532. u8 viafb_read_reg(int io_port, u8 index)
  533. {
  534. outb(index, io_port);
  535. return inb(io_port + 1);
  536. }
  537. void viafb_lock_crt(void)
  538. {
  539. viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
  540. }
  541. void viafb_unlock_crt(void)
  542. {
  543. viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
  544. viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
  545. }
  546. void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
  547. {
  548. u8 tmp;
  549. outb(index, io_port);
  550. tmp = inb(io_port + 1);
  551. outb((data & mask) | (tmp & (~mask)), io_port + 1);
  552. /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
  553. }
  554. void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
  555. {
  556. outb(index, LUT_INDEX_WRITE);
  557. outb(r, LUT_DATA);
  558. outb(g, LUT_DATA);
  559. outb(b, LUT_DATA);
  560. }
  561. /*Set IGA path for each device*/
  562. void viafb_set_iga_path(void)
  563. {
  564. if (viafb_SAMM_ON == 1) {
  565. if (viafb_CRT_ON) {
  566. if (viafb_primary_dev == CRT_Device)
  567. viaparinfo->crt_setting_info->iga_path = IGA1;
  568. else
  569. viaparinfo->crt_setting_info->iga_path = IGA2;
  570. }
  571. if (viafb_DVI_ON) {
  572. if (viafb_primary_dev == DVI_Device)
  573. viaparinfo->tmds_setting_info->iga_path = IGA1;
  574. else
  575. viaparinfo->tmds_setting_info->iga_path = IGA2;
  576. }
  577. if (viafb_LCD_ON) {
  578. if (viafb_primary_dev == LCD_Device) {
  579. if (viafb_dual_fb &&
  580. (viaparinfo->chip_info->gfx_chip_name ==
  581. UNICHROME_CLE266)) {
  582. viaparinfo->
  583. lvds_setting_info->iga_path = IGA2;
  584. viaparinfo->
  585. crt_setting_info->iga_path = IGA1;
  586. viaparinfo->
  587. tmds_setting_info->iga_path = IGA1;
  588. } else
  589. viaparinfo->
  590. lvds_setting_info->iga_path = IGA1;
  591. } else {
  592. viaparinfo->lvds_setting_info->iga_path = IGA2;
  593. }
  594. }
  595. if (viafb_LCD2_ON) {
  596. if (LCD2_Device == viafb_primary_dev)
  597. viaparinfo->lvds_setting_info2->iga_path = IGA1;
  598. else
  599. viaparinfo->lvds_setting_info2->iga_path = IGA2;
  600. }
  601. } else {
  602. viafb_SAMM_ON = 0;
  603. if (viafb_CRT_ON && viafb_LCD_ON) {
  604. viaparinfo->crt_setting_info->iga_path = IGA1;
  605. viaparinfo->lvds_setting_info->iga_path = IGA2;
  606. } else if (viafb_CRT_ON && viafb_DVI_ON) {
  607. viaparinfo->crt_setting_info->iga_path = IGA1;
  608. viaparinfo->tmds_setting_info->iga_path = IGA2;
  609. } else if (viafb_LCD_ON && viafb_DVI_ON) {
  610. viaparinfo->tmds_setting_info->iga_path = IGA1;
  611. viaparinfo->lvds_setting_info->iga_path = IGA2;
  612. } else if (viafb_LCD_ON && viafb_LCD2_ON) {
  613. viaparinfo->lvds_setting_info->iga_path = IGA2;
  614. viaparinfo->lvds_setting_info2->iga_path = IGA2;
  615. } else if (viafb_CRT_ON) {
  616. viaparinfo->crt_setting_info->iga_path = IGA1;
  617. } else if (viafb_LCD_ON) {
  618. viaparinfo->lvds_setting_info->iga_path = IGA2;
  619. } else if (viafb_DVI_ON) {
  620. viaparinfo->tmds_setting_info->iga_path = IGA1;
  621. }
  622. }
  623. }
  624. void viafb_set_primary_address(u32 addr)
  625. {
  626. DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
  627. viafb_write_reg(CR0D, VIACR, addr & 0xFF);
  628. viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
  629. viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
  630. viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
  631. }
  632. void viafb_set_secondary_address(u32 addr)
  633. {
  634. DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
  635. /* secondary display supports only quadword aligned memory */
  636. viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
  637. viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
  638. viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
  639. viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
  640. }
  641. void viafb_set_primary_pitch(u32 pitch)
  642. {
  643. DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
  644. /* spec does not say that first adapter skips 3 bits but old
  645. * code did it and seems to be reasonable in analogy to 2nd adapter
  646. */
  647. pitch = pitch >> 3;
  648. viafb_write_reg(0x13, VIACR, pitch & 0xFF);
  649. viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
  650. }
  651. void viafb_set_secondary_pitch(u32 pitch)
  652. {
  653. DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
  654. pitch = pitch >> 3;
  655. viafb_write_reg(0x66, VIACR, pitch & 0xFF);
  656. viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
  657. viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
  658. }
  659. void viafb_set_primary_color_depth(u8 depth)
  660. {
  661. u8 value;
  662. DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
  663. switch (depth) {
  664. case 8:
  665. value = 0x00;
  666. break;
  667. case 15:
  668. value = 0x04;
  669. break;
  670. case 16:
  671. value = 0x14;
  672. break;
  673. case 24:
  674. value = 0x0C;
  675. break;
  676. case 30:
  677. value = 0x08;
  678. break;
  679. default:
  680. printk(KERN_WARNING "viafb_set_primary_color_depth: "
  681. "Unsupported depth: %d\n", depth);
  682. return;
  683. }
  684. viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
  685. }
  686. void viafb_set_secondary_color_depth(u8 depth)
  687. {
  688. u8 value;
  689. DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
  690. switch (depth) {
  691. case 8:
  692. value = 0x00;
  693. break;
  694. case 16:
  695. value = 0x40;
  696. break;
  697. case 24:
  698. value = 0xC0;
  699. break;
  700. case 30:
  701. value = 0x80;
  702. break;
  703. default:
  704. printk(KERN_WARNING "viafb_set_secondary_color_depth: "
  705. "Unsupported depth: %d\n", depth);
  706. return;
  707. }
  708. viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
  709. }
  710. static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
  711. {
  712. outb(0xFF, 0x3C6); /* bit mask of palette */
  713. outb(index, 0x3C8);
  714. outb(red, 0x3C9);
  715. outb(green, 0x3C9);
  716. outb(blue, 0x3C9);
  717. }
  718. void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
  719. {
  720. viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
  721. set_color_register(index, red, green, blue);
  722. }
  723. void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
  724. {
  725. viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
  726. set_color_register(index, red, green, blue);
  727. }
  728. void viafb_set_output_path(int device, int set_iga, int output_interface)
  729. {
  730. switch (device) {
  731. case DEVICE_CRT:
  732. set_crt_output_path(set_iga);
  733. break;
  734. case DEVICE_DVI:
  735. set_dvi_output_path(set_iga, output_interface);
  736. break;
  737. case DEVICE_LCD:
  738. set_lcd_output_path(set_iga, output_interface);
  739. break;
  740. }
  741. }
  742. static void set_crt_output_path(int set_iga)
  743. {
  744. viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
  745. switch (set_iga) {
  746. case IGA1:
  747. viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
  748. break;
  749. case IGA2:
  750. viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
  751. viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
  752. break;
  753. }
  754. }
  755. static void dvi_patch_skew_dvp0(void)
  756. {
  757. /* Reset data driving first: */
  758. viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
  759. viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
  760. switch (viaparinfo->chip_info->gfx_chip_name) {
  761. case UNICHROME_P4M890:
  762. {
  763. if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
  764. (viaparinfo->tmds_setting_info->v_active ==
  765. 1200))
  766. viafb_write_reg_mask(CR96, VIACR, 0x03,
  767. BIT0 + BIT1 + BIT2);
  768. else
  769. viafb_write_reg_mask(CR96, VIACR, 0x07,
  770. BIT0 + BIT1 + BIT2);
  771. break;
  772. }
  773. case UNICHROME_P4M900:
  774. {
  775. viafb_write_reg_mask(CR96, VIACR, 0x07,
  776. BIT0 + BIT1 + BIT2 + BIT3);
  777. viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
  778. viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
  779. break;
  780. }
  781. default:
  782. {
  783. break;
  784. }
  785. }
  786. }
  787. static void dvi_patch_skew_dvp1(void)
  788. {
  789. switch (viaparinfo->chip_info->gfx_chip_name) {
  790. case UNICHROME_CX700:
  791. {
  792. break;
  793. }
  794. default:
  795. {
  796. break;
  797. }
  798. }
  799. }
  800. static void dvi_patch_skew_dvp_low(void)
  801. {
  802. switch (viaparinfo->chip_info->gfx_chip_name) {
  803. case UNICHROME_K8M890:
  804. {
  805. viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
  806. break;
  807. }
  808. case UNICHROME_P4M900:
  809. {
  810. viafb_write_reg_mask(CR99, VIACR, 0x08,
  811. BIT0 + BIT1 + BIT2 + BIT3);
  812. break;
  813. }
  814. case UNICHROME_P4M890:
  815. {
  816. viafb_write_reg_mask(CR99, VIACR, 0x0F,
  817. BIT0 + BIT1 + BIT2 + BIT3);
  818. break;
  819. }
  820. default:
  821. {
  822. break;
  823. }
  824. }
  825. }
  826. static void set_dvi_output_path(int set_iga, int output_interface)
  827. {
  828. switch (output_interface) {
  829. case INTERFACE_DVP0:
  830. viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
  831. if (set_iga == IGA1) {
  832. viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
  833. viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
  834. BIT5 + BIT7);
  835. } else {
  836. viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
  837. viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
  838. BIT5 + BIT7);
  839. }
  840. viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
  841. dvi_patch_skew_dvp0();
  842. break;
  843. case INTERFACE_DVP1:
  844. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  845. if (set_iga == IGA1)
  846. viafb_write_reg_mask(CR93, VIACR, 0x21,
  847. BIT0 + BIT5 + BIT7);
  848. else
  849. viafb_write_reg_mask(CR93, VIACR, 0xA1,
  850. BIT0 + BIT5 + BIT7);
  851. } else {
  852. if (set_iga == IGA1)
  853. viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
  854. else
  855. viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
  856. }
  857. viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
  858. dvi_patch_skew_dvp1();
  859. break;
  860. case INTERFACE_DFP_HIGH:
  861. if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
  862. if (set_iga == IGA1) {
  863. viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
  864. viafb_write_reg_mask(CR97, VIACR, 0x03,
  865. BIT0 + BIT1 + BIT4);
  866. } else {
  867. viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
  868. viafb_write_reg_mask(CR97, VIACR, 0x13,
  869. BIT0 + BIT1 + BIT4);
  870. }
  871. }
  872. viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
  873. break;
  874. case INTERFACE_DFP_LOW:
  875. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
  876. break;
  877. if (set_iga == IGA1) {
  878. viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
  879. viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
  880. } else {
  881. viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
  882. viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
  883. }
  884. viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
  885. dvi_patch_skew_dvp_low();
  886. break;
  887. case INTERFACE_TMDS:
  888. if (set_iga == IGA1)
  889. viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
  890. else
  891. viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
  892. break;
  893. }
  894. if (set_iga == IGA2) {
  895. enable_second_display_channel();
  896. /* Disable LCD Scaling */
  897. viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
  898. }
  899. }
  900. static void set_lcd_output_path(int set_iga, int output_interface)
  901. {
  902. DEBUG_MSG(KERN_INFO
  903. "set_lcd_output_path, iga:%d,out_interface:%d\n",
  904. set_iga, output_interface);
  905. switch (set_iga) {
  906. case IGA1:
  907. viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
  908. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  909. disable_second_display_channel();
  910. break;
  911. case IGA2:
  912. viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
  913. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  914. enable_second_display_channel();
  915. break;
  916. }
  917. switch (output_interface) {
  918. case INTERFACE_DVP0:
  919. if (set_iga == IGA1) {
  920. viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
  921. } else {
  922. viafb_write_reg(CR91, VIACR, 0x00);
  923. viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
  924. }
  925. break;
  926. case INTERFACE_DVP1:
  927. if (set_iga == IGA1)
  928. viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
  929. else {
  930. viafb_write_reg(CR91, VIACR, 0x00);
  931. viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
  932. }
  933. break;
  934. case INTERFACE_DFP_HIGH:
  935. if (set_iga == IGA1)
  936. viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
  937. else {
  938. viafb_write_reg(CR91, VIACR, 0x00);
  939. viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
  940. viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
  941. }
  942. break;
  943. case INTERFACE_DFP_LOW:
  944. if (set_iga == IGA1)
  945. viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
  946. else {
  947. viafb_write_reg(CR91, VIACR, 0x00);
  948. viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
  949. viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
  950. }
  951. break;
  952. case INTERFACE_DFP:
  953. if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
  954. || (UNICHROME_P4M890 ==
  955. viaparinfo->chip_info->gfx_chip_name))
  956. viafb_write_reg_mask(CR97, VIACR, 0x84,
  957. BIT7 + BIT2 + BIT1 + BIT0);
  958. if (set_iga == IGA1) {
  959. viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
  960. viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
  961. } else {
  962. viafb_write_reg(CR91, VIACR, 0x00);
  963. viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
  964. viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
  965. }
  966. break;
  967. case INTERFACE_LVDS0:
  968. case INTERFACE_LVDS0LVDS1:
  969. if (set_iga == IGA1)
  970. viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
  971. else
  972. viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
  973. break;
  974. case INTERFACE_LVDS1:
  975. if (set_iga == IGA1)
  976. viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
  977. else
  978. viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
  979. break;
  980. }
  981. }
  982. static void load_fix_bit_crtc_reg(void)
  983. {
  984. /* always set to 1 */
  985. viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
  986. /* line compare should set all bits = 1 (extend modes) */
  987. viafb_write_reg(CR18, VIACR, 0xff);
  988. /* line compare should set all bits = 1 (extend modes) */
  989. viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
  990. /* line compare should set all bits = 1 (extend modes) */
  991. viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
  992. /* line compare should set all bits = 1 (extend modes) */
  993. viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
  994. /* line compare should set all bits = 1 (extend modes) */
  995. viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
  996. /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
  997. /* extend mode always set to e3h */
  998. viafb_write_reg(CR17, VIACR, 0xe3);
  999. /* extend mode always set to 0h */
  1000. viafb_write_reg(CR08, VIACR, 0x00);
  1001. /* extend mode always set to 0h */
  1002. viafb_write_reg(CR14, VIACR, 0x00);
  1003. /* If K8M800, enable Prefetch Mode. */
  1004. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
  1005. || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
  1006. viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
  1007. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
  1008. && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
  1009. viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
  1010. }
  1011. void viafb_load_reg(int timing_value, int viafb_load_reg_num,
  1012. struct io_register *reg,
  1013. int io_type)
  1014. {
  1015. int reg_mask;
  1016. int bit_num = 0;
  1017. int data;
  1018. int i, j;
  1019. int shift_next_reg;
  1020. int start_index, end_index, cr_index;
  1021. u16 get_bit;
  1022. for (i = 0; i < viafb_load_reg_num; i++) {
  1023. reg_mask = 0;
  1024. data = 0;
  1025. start_index = reg[i].start_bit;
  1026. end_index = reg[i].end_bit;
  1027. cr_index = reg[i].io_addr;
  1028. shift_next_reg = bit_num;
  1029. for (j = start_index; j <= end_index; j++) {
  1030. /*if (bit_num==8) timing_value = timing_value >>8; */
  1031. reg_mask = reg_mask | (BIT0 << j);
  1032. get_bit = (timing_value & (BIT0 << bit_num));
  1033. data =
  1034. data | ((get_bit >> shift_next_reg) << start_index);
  1035. bit_num++;
  1036. }
  1037. if (io_type == VIACR)
  1038. viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
  1039. else
  1040. viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
  1041. }
  1042. }
  1043. /* Write Registers */
  1044. void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
  1045. {
  1046. int i;
  1047. unsigned char RegTemp;
  1048. /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
  1049. for (i = 0; i < ItemNum; i++) {
  1050. outb(RegTable[i].index, RegTable[i].port);
  1051. RegTemp = inb(RegTable[i].port + 1);
  1052. RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
  1053. outb(RegTemp, RegTable[i].port + 1);
  1054. }
  1055. }
  1056. void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
  1057. {
  1058. int reg_value;
  1059. int viafb_load_reg_num;
  1060. struct io_register *reg = NULL;
  1061. switch (set_iga) {
  1062. case IGA1:
  1063. reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
  1064. viafb_load_reg_num = fetch_count_reg.
  1065. iga1_fetch_count_reg.reg_num;
  1066. reg = fetch_count_reg.iga1_fetch_count_reg.reg;
  1067. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
  1068. break;
  1069. case IGA2:
  1070. reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
  1071. viafb_load_reg_num = fetch_count_reg.
  1072. iga2_fetch_count_reg.reg_num;
  1073. reg = fetch_count_reg.iga2_fetch_count_reg.reg;
  1074. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
  1075. break;
  1076. }
  1077. }
  1078. void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
  1079. {
  1080. int reg_value;
  1081. int viafb_load_reg_num;
  1082. struct io_register *reg = NULL;
  1083. int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
  1084. 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
  1085. int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
  1086. 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
  1087. if (set_iga == IGA1) {
  1088. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
  1089. iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
  1090. iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
  1091. iga1_fifo_high_threshold =
  1092. K800_IGA1_FIFO_HIGH_THRESHOLD;
  1093. /* If resolution > 1280x1024, expire length = 64, else
  1094. expire length = 128 */
  1095. if ((hor_active > 1280) && (ver_active > 1024))
  1096. iga1_display_queue_expire_num = 16;
  1097. else
  1098. iga1_display_queue_expire_num =
  1099. K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1100. }
  1101. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
  1102. iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
  1103. iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
  1104. iga1_fifo_high_threshold =
  1105. P880_IGA1_FIFO_HIGH_THRESHOLD;
  1106. iga1_display_queue_expire_num =
  1107. P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1108. /* If resolution > 1280x1024, expire length = 64, else
  1109. expire length = 128 */
  1110. if ((hor_active > 1280) && (ver_active > 1024))
  1111. iga1_display_queue_expire_num = 16;
  1112. else
  1113. iga1_display_queue_expire_num =
  1114. P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1115. }
  1116. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
  1117. iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
  1118. iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
  1119. iga1_fifo_high_threshold =
  1120. CN700_IGA1_FIFO_HIGH_THRESHOLD;
  1121. /* If resolution > 1280x1024, expire length = 64,
  1122. else expire length = 128 */
  1123. if ((hor_active > 1280) && (ver_active > 1024))
  1124. iga1_display_queue_expire_num = 16;
  1125. else
  1126. iga1_display_queue_expire_num =
  1127. CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1128. }
  1129. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  1130. iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
  1131. iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
  1132. iga1_fifo_high_threshold =
  1133. CX700_IGA1_FIFO_HIGH_THRESHOLD;
  1134. iga1_display_queue_expire_num =
  1135. CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1136. }
  1137. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
  1138. iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
  1139. iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
  1140. iga1_fifo_high_threshold =
  1141. K8M890_IGA1_FIFO_HIGH_THRESHOLD;
  1142. iga1_display_queue_expire_num =
  1143. K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1144. }
  1145. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
  1146. iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
  1147. iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
  1148. iga1_fifo_high_threshold =
  1149. P4M890_IGA1_FIFO_HIGH_THRESHOLD;
  1150. iga1_display_queue_expire_num =
  1151. P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1152. }
  1153. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
  1154. iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
  1155. iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
  1156. iga1_fifo_high_threshold =
  1157. P4M900_IGA1_FIFO_HIGH_THRESHOLD;
  1158. iga1_display_queue_expire_num =
  1159. P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1160. }
  1161. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
  1162. iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
  1163. iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
  1164. iga1_fifo_high_threshold =
  1165. VX800_IGA1_FIFO_HIGH_THRESHOLD;
  1166. iga1_display_queue_expire_num =
  1167. VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1168. }
  1169. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
  1170. iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
  1171. iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
  1172. iga1_fifo_high_threshold =
  1173. VX855_IGA1_FIFO_HIGH_THRESHOLD;
  1174. iga1_display_queue_expire_num =
  1175. VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
  1176. }
  1177. /* Set Display FIFO Depath Select */
  1178. reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
  1179. viafb_load_reg_num =
  1180. display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
  1181. reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
  1182. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
  1183. /* Set Display FIFO Threshold Select */
  1184. reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
  1185. viafb_load_reg_num =
  1186. fifo_threshold_select_reg.
  1187. iga1_fifo_threshold_select_reg.reg_num;
  1188. reg =
  1189. fifo_threshold_select_reg.
  1190. iga1_fifo_threshold_select_reg.reg;
  1191. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
  1192. /* Set FIFO High Threshold Select */
  1193. reg_value =
  1194. IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
  1195. viafb_load_reg_num =
  1196. fifo_high_threshold_select_reg.
  1197. iga1_fifo_high_threshold_select_reg.reg_num;
  1198. reg =
  1199. fifo_high_threshold_select_reg.
  1200. iga1_fifo_high_threshold_select_reg.reg;
  1201. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
  1202. /* Set Display Queue Expire Num */
  1203. reg_value =
  1204. IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
  1205. (iga1_display_queue_expire_num);
  1206. viafb_load_reg_num =
  1207. display_queue_expire_num_reg.
  1208. iga1_display_queue_expire_num_reg.reg_num;
  1209. reg =
  1210. display_queue_expire_num_reg.
  1211. iga1_display_queue_expire_num_reg.reg;
  1212. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
  1213. } else {
  1214. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
  1215. iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
  1216. iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
  1217. iga2_fifo_high_threshold =
  1218. K800_IGA2_FIFO_HIGH_THRESHOLD;
  1219. /* If resolution > 1280x1024, expire length = 64,
  1220. else expire length = 128 */
  1221. if ((hor_active > 1280) && (ver_active > 1024))
  1222. iga2_display_queue_expire_num = 16;
  1223. else
  1224. iga2_display_queue_expire_num =
  1225. K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1226. }
  1227. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
  1228. iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
  1229. iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
  1230. iga2_fifo_high_threshold =
  1231. P880_IGA2_FIFO_HIGH_THRESHOLD;
  1232. /* If resolution > 1280x1024, expire length = 64,
  1233. else expire length = 128 */
  1234. if ((hor_active > 1280) && (ver_active > 1024))
  1235. iga2_display_queue_expire_num = 16;
  1236. else
  1237. iga2_display_queue_expire_num =
  1238. P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1239. }
  1240. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
  1241. iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
  1242. iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
  1243. iga2_fifo_high_threshold =
  1244. CN700_IGA2_FIFO_HIGH_THRESHOLD;
  1245. /* If resolution > 1280x1024, expire length = 64,
  1246. else expire length = 128 */
  1247. if ((hor_active > 1280) && (ver_active > 1024))
  1248. iga2_display_queue_expire_num = 16;
  1249. else
  1250. iga2_display_queue_expire_num =
  1251. CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1252. }
  1253. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  1254. iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
  1255. iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
  1256. iga2_fifo_high_threshold =
  1257. CX700_IGA2_FIFO_HIGH_THRESHOLD;
  1258. iga2_display_queue_expire_num =
  1259. CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1260. }
  1261. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
  1262. iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
  1263. iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
  1264. iga2_fifo_high_threshold =
  1265. K8M890_IGA2_FIFO_HIGH_THRESHOLD;
  1266. iga2_display_queue_expire_num =
  1267. K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1268. }
  1269. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
  1270. iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
  1271. iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
  1272. iga2_fifo_high_threshold =
  1273. P4M890_IGA2_FIFO_HIGH_THRESHOLD;
  1274. iga2_display_queue_expire_num =
  1275. P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1276. }
  1277. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
  1278. iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
  1279. iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
  1280. iga2_fifo_high_threshold =
  1281. P4M900_IGA2_FIFO_HIGH_THRESHOLD;
  1282. iga2_display_queue_expire_num =
  1283. P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1284. }
  1285. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
  1286. iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
  1287. iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
  1288. iga2_fifo_high_threshold =
  1289. VX800_IGA2_FIFO_HIGH_THRESHOLD;
  1290. iga2_display_queue_expire_num =
  1291. VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1292. }
  1293. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
  1294. iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
  1295. iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
  1296. iga2_fifo_high_threshold =
  1297. VX855_IGA2_FIFO_HIGH_THRESHOLD;
  1298. iga2_display_queue_expire_num =
  1299. VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
  1300. }
  1301. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
  1302. /* Set Display FIFO Depath Select */
  1303. reg_value =
  1304. IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
  1305. - 1;
  1306. /* Patch LCD in IGA2 case */
  1307. viafb_load_reg_num =
  1308. display_fifo_depth_reg.
  1309. iga2_fifo_depth_select_reg.reg_num;
  1310. reg =
  1311. display_fifo_depth_reg.
  1312. iga2_fifo_depth_select_reg.reg;
  1313. viafb_load_reg(reg_value,
  1314. viafb_load_reg_num, reg, VIACR);
  1315. } else {
  1316. /* Set Display FIFO Depath Select */
  1317. reg_value =
  1318. IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
  1319. viafb_load_reg_num =
  1320. display_fifo_depth_reg.
  1321. iga2_fifo_depth_select_reg.reg_num;
  1322. reg =
  1323. display_fifo_depth_reg.
  1324. iga2_fifo_depth_select_reg.reg;
  1325. viafb_load_reg(reg_value,
  1326. viafb_load_reg_num, reg, VIACR);
  1327. }
  1328. /* Set Display FIFO Threshold Select */
  1329. reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
  1330. viafb_load_reg_num =
  1331. fifo_threshold_select_reg.
  1332. iga2_fifo_threshold_select_reg.reg_num;
  1333. reg =
  1334. fifo_threshold_select_reg.
  1335. iga2_fifo_threshold_select_reg.reg;
  1336. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
  1337. /* Set FIFO High Threshold Select */
  1338. reg_value =
  1339. IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
  1340. viafb_load_reg_num =
  1341. fifo_high_threshold_select_reg.
  1342. iga2_fifo_high_threshold_select_reg.reg_num;
  1343. reg =
  1344. fifo_high_threshold_select_reg.
  1345. iga2_fifo_high_threshold_select_reg.reg;
  1346. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
  1347. /* Set Display Queue Expire Num */
  1348. reg_value =
  1349. IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
  1350. (iga2_display_queue_expire_num);
  1351. viafb_load_reg_num =
  1352. display_queue_expire_num_reg.
  1353. iga2_display_queue_expire_num_reg.reg_num;
  1354. reg =
  1355. display_queue_expire_num_reg.
  1356. iga2_display_queue_expire_num_reg.reg;
  1357. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
  1358. }
  1359. }
  1360. u32 viafb_get_clk_value(int clk)
  1361. {
  1362. int i;
  1363. for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
  1364. if (clk == pll_value[i].clk) {
  1365. switch (viaparinfo->chip_info->gfx_chip_name) {
  1366. case UNICHROME_CLE266:
  1367. case UNICHROME_K400:
  1368. return pll_value[i].cle266_pll;
  1369. case UNICHROME_K800:
  1370. case UNICHROME_PM800:
  1371. case UNICHROME_CN700:
  1372. return pll_value[i].k800_pll;
  1373. case UNICHROME_CX700:
  1374. case UNICHROME_K8M890:
  1375. case UNICHROME_P4M890:
  1376. case UNICHROME_P4M900:
  1377. case UNICHROME_VX800:
  1378. return pll_value[i].cx700_pll;
  1379. case UNICHROME_VX855:
  1380. return pll_value[i].vx855_pll;
  1381. }
  1382. }
  1383. }
  1384. DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
  1385. return 0;
  1386. }
  1387. /* Set VCLK*/
  1388. void viafb_set_vclock(u32 CLK, int set_iga)
  1389. {
  1390. unsigned char RegTemp;
  1391. /* H.W. Reset : ON */
  1392. viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
  1393. if (set_iga == IGA1) {
  1394. /* Change D,N FOR VCLK */
  1395. switch (viaparinfo->chip_info->gfx_chip_name) {
  1396. case UNICHROME_CLE266:
  1397. case UNICHROME_K400:
  1398. viafb_write_reg(SR46, VIASR, CLK / 0x100);
  1399. viafb_write_reg(SR47, VIASR, CLK % 0x100);
  1400. break;
  1401. case UNICHROME_K800:
  1402. case UNICHROME_PM800:
  1403. case UNICHROME_CN700:
  1404. case UNICHROME_CX700:
  1405. case UNICHROME_K8M890:
  1406. case UNICHROME_P4M890:
  1407. case UNICHROME_P4M900:
  1408. case UNICHROME_VX800:
  1409. case UNICHROME_VX855:
  1410. viafb_write_reg(SR44, VIASR, CLK / 0x10000);
  1411. DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
  1412. viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
  1413. DEBUG_MSG(KERN_INFO "\nSR45=%x",
  1414. (CLK & 0xFFFF) / 0x100);
  1415. viafb_write_reg(SR46, VIASR, CLK % 0x100);
  1416. DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
  1417. break;
  1418. }
  1419. }
  1420. if (set_iga == IGA2) {
  1421. /* Change D,N FOR LCK */
  1422. switch (viaparinfo->chip_info->gfx_chip_name) {
  1423. case UNICHROME_CLE266:
  1424. case UNICHROME_K400:
  1425. viafb_write_reg(SR44, VIASR, CLK / 0x100);
  1426. viafb_write_reg(SR45, VIASR, CLK % 0x100);
  1427. break;
  1428. case UNICHROME_K800:
  1429. case UNICHROME_PM800:
  1430. case UNICHROME_CN700:
  1431. case UNICHROME_CX700:
  1432. case UNICHROME_K8M890:
  1433. case UNICHROME_P4M890:
  1434. case UNICHROME_P4M900:
  1435. case UNICHROME_VX800:
  1436. case UNICHROME_VX855:
  1437. viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
  1438. viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
  1439. viafb_write_reg(SR4C, VIASR, CLK % 0x100);
  1440. break;
  1441. }
  1442. }
  1443. /* H.W. Reset : OFF */
  1444. viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
  1445. /* Reset PLL */
  1446. if (set_iga == IGA1) {
  1447. viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
  1448. viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
  1449. }
  1450. if (set_iga == IGA2) {
  1451. viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
  1452. viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
  1453. }
  1454. /* Fire! */
  1455. RegTemp = inb(VIARMisc);
  1456. outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
  1457. }
  1458. void viafb_load_crtc_timing(struct display_timing device_timing,
  1459. int set_iga)
  1460. {
  1461. int i;
  1462. int viafb_load_reg_num = 0;
  1463. int reg_value = 0;
  1464. struct io_register *reg = NULL;
  1465. viafb_unlock_crt();
  1466. for (i = 0; i < 12; i++) {
  1467. if (set_iga == IGA1) {
  1468. switch (i) {
  1469. case H_TOTAL_INDEX:
  1470. reg_value =
  1471. IGA1_HOR_TOTAL_FORMULA(device_timing.
  1472. hor_total);
  1473. viafb_load_reg_num =
  1474. iga1_crtc_reg.hor_total.reg_num;
  1475. reg = iga1_crtc_reg.hor_total.reg;
  1476. break;
  1477. case H_ADDR_INDEX:
  1478. reg_value =
  1479. IGA1_HOR_ADDR_FORMULA(device_timing.
  1480. hor_addr);
  1481. viafb_load_reg_num =
  1482. iga1_crtc_reg.hor_addr.reg_num;
  1483. reg = iga1_crtc_reg.hor_addr.reg;
  1484. break;
  1485. case H_BLANK_START_INDEX:
  1486. reg_value =
  1487. IGA1_HOR_BLANK_START_FORMULA
  1488. (device_timing.hor_blank_start);
  1489. viafb_load_reg_num =
  1490. iga1_crtc_reg.hor_blank_start.reg_num;
  1491. reg = iga1_crtc_reg.hor_blank_start.reg;
  1492. break;
  1493. case H_BLANK_END_INDEX:
  1494. reg_value =
  1495. IGA1_HOR_BLANK_END_FORMULA
  1496. (device_timing.hor_blank_start,
  1497. device_timing.hor_blank_end);
  1498. viafb_load_reg_num =
  1499. iga1_crtc_reg.hor_blank_end.reg_num;
  1500. reg = iga1_crtc_reg.hor_blank_end.reg;
  1501. break;
  1502. case H_SYNC_START_INDEX:
  1503. reg_value =
  1504. IGA1_HOR_SYNC_START_FORMULA
  1505. (device_timing.hor_sync_start);
  1506. viafb_load_reg_num =
  1507. iga1_crtc_reg.hor_sync_start.reg_num;
  1508. reg = iga1_crtc_reg.hor_sync_start.reg;
  1509. break;
  1510. case H_SYNC_END_INDEX:
  1511. reg_value =
  1512. IGA1_HOR_SYNC_END_FORMULA
  1513. (device_timing.hor_sync_start,
  1514. device_timing.hor_sync_end);
  1515. viafb_load_reg_num =
  1516. iga1_crtc_reg.hor_sync_end.reg_num;
  1517. reg = iga1_crtc_reg.hor_sync_end.reg;
  1518. break;
  1519. case V_TOTAL_INDEX:
  1520. reg_value =
  1521. IGA1_VER_TOTAL_FORMULA(device_timing.
  1522. ver_total);
  1523. viafb_load_reg_num =
  1524. iga1_crtc_reg.ver_total.reg_num;
  1525. reg = iga1_crtc_reg.ver_total.reg;
  1526. break;
  1527. case V_ADDR_INDEX:
  1528. reg_value =
  1529. IGA1_VER_ADDR_FORMULA(device_timing.
  1530. ver_addr);
  1531. viafb_load_reg_num =
  1532. iga1_crtc_reg.ver_addr.reg_num;
  1533. reg = iga1_crtc_reg.ver_addr.reg;
  1534. break;
  1535. case V_BLANK_START_INDEX:
  1536. reg_value =
  1537. IGA1_VER_BLANK_START_FORMULA
  1538. (device_timing.ver_blank_start);
  1539. viafb_load_reg_num =
  1540. iga1_crtc_reg.ver_blank_start.reg_num;
  1541. reg = iga1_crtc_reg.ver_blank_start.reg;
  1542. break;
  1543. case V_BLANK_END_INDEX:
  1544. reg_value =
  1545. IGA1_VER_BLANK_END_FORMULA
  1546. (device_timing.ver_blank_start,
  1547. device_timing.ver_blank_end);
  1548. viafb_load_reg_num =
  1549. iga1_crtc_reg.ver_blank_end.reg_num;
  1550. reg = iga1_crtc_reg.ver_blank_end.reg;
  1551. break;
  1552. case V_SYNC_START_INDEX:
  1553. reg_value =
  1554. IGA1_VER_SYNC_START_FORMULA
  1555. (device_timing.ver_sync_start);
  1556. viafb_load_reg_num =
  1557. iga1_crtc_reg.ver_sync_start.reg_num;
  1558. reg = iga1_crtc_reg.ver_sync_start.reg;
  1559. break;
  1560. case V_SYNC_END_INDEX:
  1561. reg_value =
  1562. IGA1_VER_SYNC_END_FORMULA
  1563. (device_timing.ver_sync_start,
  1564. device_timing.ver_sync_end);
  1565. viafb_load_reg_num =
  1566. iga1_crtc_reg.ver_sync_end.reg_num;
  1567. reg = iga1_crtc_reg.ver_sync_end.reg;
  1568. break;
  1569. }
  1570. }
  1571. if (set_iga == IGA2) {
  1572. switch (i) {
  1573. case H_TOTAL_INDEX:
  1574. reg_value =
  1575. IGA2_HOR_TOTAL_FORMULA(device_timing.
  1576. hor_total);
  1577. viafb_load_reg_num =
  1578. iga2_crtc_reg.hor_total.reg_num;
  1579. reg = iga2_crtc_reg.hor_total.reg;
  1580. break;
  1581. case H_ADDR_INDEX:
  1582. reg_value =
  1583. IGA2_HOR_ADDR_FORMULA(device_timing.
  1584. hor_addr);
  1585. viafb_load_reg_num =
  1586. iga2_crtc_reg.hor_addr.reg_num;
  1587. reg = iga2_crtc_reg.hor_addr.reg;
  1588. break;
  1589. case H_BLANK_START_INDEX:
  1590. reg_value =
  1591. IGA2_HOR_BLANK_START_FORMULA
  1592. (device_timing.hor_blank_start);
  1593. viafb_load_reg_num =
  1594. iga2_crtc_reg.hor_blank_start.reg_num;
  1595. reg = iga2_crtc_reg.hor_blank_start.reg;
  1596. break;
  1597. case H_BLANK_END_INDEX:
  1598. reg_value =
  1599. IGA2_HOR_BLANK_END_FORMULA
  1600. (device_timing.hor_blank_start,
  1601. device_timing.hor_blank_end);
  1602. viafb_load_reg_num =
  1603. iga2_crtc_reg.hor_blank_end.reg_num;
  1604. reg = iga2_crtc_reg.hor_blank_end.reg;
  1605. break;
  1606. case H_SYNC_START_INDEX:
  1607. reg_value =
  1608. IGA2_HOR_SYNC_START_FORMULA
  1609. (device_timing.hor_sync_start);
  1610. if (UNICHROME_CN700 <=
  1611. viaparinfo->chip_info->gfx_chip_name)
  1612. viafb_load_reg_num =
  1613. iga2_crtc_reg.hor_sync_start.
  1614. reg_num;
  1615. else
  1616. viafb_load_reg_num = 3;
  1617. reg = iga2_crtc_reg.hor_sync_start.reg;
  1618. break;
  1619. case H_SYNC_END_INDEX:
  1620. reg_value =
  1621. IGA2_HOR_SYNC_END_FORMULA
  1622. (device_timing.hor_sync_start,
  1623. device_timing.hor_sync_end);
  1624. viafb_load_reg_num =
  1625. iga2_crtc_reg.hor_sync_end.reg_num;
  1626. reg = iga2_crtc_reg.hor_sync_end.reg;
  1627. break;
  1628. case V_TOTAL_INDEX:
  1629. reg_value =
  1630. IGA2_VER_TOTAL_FORMULA(device_timing.
  1631. ver_total);
  1632. viafb_load_reg_num =
  1633. iga2_crtc_reg.ver_total.reg_num;
  1634. reg = iga2_crtc_reg.ver_total.reg;
  1635. break;
  1636. case V_ADDR_INDEX:
  1637. reg_value =
  1638. IGA2_VER_ADDR_FORMULA(device_timing.
  1639. ver_addr);
  1640. viafb_load_reg_num =
  1641. iga2_crtc_reg.ver_addr.reg_num;
  1642. reg = iga2_crtc_reg.ver_addr.reg;
  1643. break;
  1644. case V_BLANK_START_INDEX:
  1645. reg_value =
  1646. IGA2_VER_BLANK_START_FORMULA
  1647. (device_timing.ver_blank_start);
  1648. viafb_load_reg_num =
  1649. iga2_crtc_reg.ver_blank_start.reg_num;
  1650. reg = iga2_crtc_reg.ver_blank_start.reg;
  1651. break;
  1652. case V_BLANK_END_INDEX:
  1653. reg_value =
  1654. IGA2_VER_BLANK_END_FORMULA
  1655. (device_timing.ver_blank_start,
  1656. device_timing.ver_blank_end);
  1657. viafb_load_reg_num =
  1658. iga2_crtc_reg.ver_blank_end.reg_num;
  1659. reg = iga2_crtc_reg.ver_blank_end.reg;
  1660. break;
  1661. case V_SYNC_START_INDEX:
  1662. reg_value =
  1663. IGA2_VER_SYNC_START_FORMULA
  1664. (device_timing.ver_sync_start);
  1665. viafb_load_reg_num =
  1666. iga2_crtc_reg.ver_sync_start.reg_num;
  1667. reg = iga2_crtc_reg.ver_sync_start.reg;
  1668. break;
  1669. case V_SYNC_END_INDEX:
  1670. reg_value =
  1671. IGA2_VER_SYNC_END_FORMULA
  1672. (device_timing.ver_sync_start,
  1673. device_timing.ver_sync_end);
  1674. viafb_load_reg_num =
  1675. iga2_crtc_reg.ver_sync_end.reg_num;
  1676. reg = iga2_crtc_reg.ver_sync_end.reg;
  1677. break;
  1678. }
  1679. }
  1680. viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
  1681. }
  1682. viafb_lock_crt();
  1683. }
  1684. void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
  1685. struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
  1686. {
  1687. struct display_timing crt_reg;
  1688. int i;
  1689. int index = 0;
  1690. int h_addr, v_addr;
  1691. u32 pll_D_N;
  1692. for (i = 0; i < video_mode->mode_array; i++) {
  1693. index = i;
  1694. if (crt_table[i].refresh_rate == viaparinfo->
  1695. crt_setting_info->refresh_rate)
  1696. break;
  1697. }
  1698. crt_reg = crt_table[index].crtc;
  1699. /* Mode 640x480 has border, but LCD/DFP didn't have border. */
  1700. /* So we would delete border. */
  1701. if ((viafb_LCD_ON | viafb_DVI_ON)
  1702. && video_mode->crtc[0].crtc.hor_addr == 640
  1703. && video_mode->crtc[0].crtc.ver_addr == 480
  1704. && viaparinfo->crt_setting_info->refresh_rate == 60) {
  1705. /* The border is 8 pixels. */
  1706. crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
  1707. /* Blanking time should add left and right borders. */
  1708. crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
  1709. }
  1710. h_addr = crt_reg.hor_addr;
  1711. v_addr = crt_reg.ver_addr;
  1712. /* update polarity for CRT timing */
  1713. if (crt_table[index].h_sync_polarity == NEGATIVE) {
  1714. if (crt_table[index].v_sync_polarity == NEGATIVE)
  1715. outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
  1716. (BIT6 + BIT7), VIAWMisc);
  1717. else
  1718. outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
  1719. VIAWMisc);
  1720. } else {
  1721. if (crt_table[index].v_sync_polarity == NEGATIVE)
  1722. outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
  1723. VIAWMisc);
  1724. else
  1725. outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
  1726. }
  1727. if (set_iga == IGA1) {
  1728. viafb_unlock_crt();
  1729. viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
  1730. viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
  1731. viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
  1732. }
  1733. switch (set_iga) {
  1734. case IGA1:
  1735. viafb_load_crtc_timing(crt_reg, IGA1);
  1736. break;
  1737. case IGA2:
  1738. viafb_load_crtc_timing(crt_reg, IGA2);
  1739. break;
  1740. }
  1741. load_fix_bit_crtc_reg();
  1742. viafb_lock_crt();
  1743. viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
  1744. viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
  1745. /* load FIFO */
  1746. if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
  1747. && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
  1748. viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
  1749. pll_D_N = viafb_get_clk_value(crt_table[index].clk);
  1750. DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
  1751. viafb_set_vclock(pll_D_N, set_iga);
  1752. }
  1753. void viafb_init_chip_info(int chip_type)
  1754. {
  1755. init_gfx_chip_info(chip_type);
  1756. init_tmds_chip_info();
  1757. init_lvds_chip_info();
  1758. viaparinfo->crt_setting_info->iga_path = IGA1;
  1759. viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
  1760. /*Set IGA path for each device */
  1761. viafb_set_iga_path();
  1762. viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
  1763. viaparinfo->lvds_setting_info->get_lcd_size_method =
  1764. GET_LCD_SIZE_BY_USER_SETTING;
  1765. viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
  1766. viaparinfo->lvds_setting_info2->display_method =
  1767. viaparinfo->lvds_setting_info->display_method;
  1768. viaparinfo->lvds_setting_info2->lcd_mode =
  1769. viaparinfo->lvds_setting_info->lcd_mode;
  1770. }
  1771. void viafb_update_device_setting(int hres, int vres,
  1772. int bpp, int vmode_refresh, int flag)
  1773. {
  1774. if (flag == 0) {
  1775. viaparinfo->crt_setting_info->h_active = hres;
  1776. viaparinfo->crt_setting_info->v_active = vres;
  1777. viaparinfo->crt_setting_info->bpp = bpp;
  1778. viaparinfo->crt_setting_info->refresh_rate =
  1779. vmode_refresh;
  1780. viaparinfo->tmds_setting_info->h_active = hres;
  1781. viaparinfo->tmds_setting_info->v_active = vres;
  1782. viaparinfo->lvds_setting_info->h_active = hres;
  1783. viaparinfo->lvds_setting_info->v_active = vres;
  1784. viaparinfo->lvds_setting_info->bpp = bpp;
  1785. viaparinfo->lvds_setting_info->refresh_rate =
  1786. vmode_refresh;
  1787. viaparinfo->lvds_setting_info2->h_active = hres;
  1788. viaparinfo->lvds_setting_info2->v_active = vres;
  1789. viaparinfo->lvds_setting_info2->bpp = bpp;
  1790. viaparinfo->lvds_setting_info2->refresh_rate =
  1791. vmode_refresh;
  1792. } else {
  1793. if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
  1794. viaparinfo->tmds_setting_info->h_active = hres;
  1795. viaparinfo->tmds_setting_info->v_active = vres;
  1796. }
  1797. if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
  1798. viaparinfo->lvds_setting_info->h_active = hres;
  1799. viaparinfo->lvds_setting_info->v_active = vres;
  1800. viaparinfo->lvds_setting_info->bpp = bpp;
  1801. viaparinfo->lvds_setting_info->refresh_rate =
  1802. vmode_refresh;
  1803. }
  1804. if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
  1805. viaparinfo->lvds_setting_info2->h_active = hres;
  1806. viaparinfo->lvds_setting_info2->v_active = vres;
  1807. viaparinfo->lvds_setting_info2->bpp = bpp;
  1808. viaparinfo->lvds_setting_info2->refresh_rate =
  1809. vmode_refresh;
  1810. }
  1811. }
  1812. }
  1813. static void init_gfx_chip_info(int chip_type)
  1814. {
  1815. u8 tmp;
  1816. viaparinfo->chip_info->gfx_chip_name = chip_type;
  1817. /* Check revision of CLE266 Chip */
  1818. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  1819. /* CR4F only define in CLE266.CX chip */
  1820. tmp = viafb_read_reg(VIACR, CR4F);
  1821. viafb_write_reg(CR4F, VIACR, 0x55);
  1822. if (viafb_read_reg(VIACR, CR4F) != 0x55)
  1823. viaparinfo->chip_info->gfx_chip_revision =
  1824. CLE266_REVISION_AX;
  1825. else
  1826. viaparinfo->chip_info->gfx_chip_revision =
  1827. CLE266_REVISION_CX;
  1828. /* restore orignal CR4F value */
  1829. viafb_write_reg(CR4F, VIACR, tmp);
  1830. }
  1831. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  1832. tmp = viafb_read_reg(VIASR, SR43);
  1833. DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
  1834. if (tmp & 0x02) {
  1835. viaparinfo->chip_info->gfx_chip_revision =
  1836. CX700_REVISION_700M2;
  1837. } else if (tmp & 0x40) {
  1838. viaparinfo->chip_info->gfx_chip_revision =
  1839. CX700_REVISION_700M;
  1840. } else {
  1841. viaparinfo->chip_info->gfx_chip_revision =
  1842. CX700_REVISION_700;
  1843. }
  1844. }
  1845. /* Determine which 2D engine we have */
  1846. switch (viaparinfo->chip_info->gfx_chip_name) {
  1847. case UNICHROME_VX800:
  1848. case UNICHROME_VX855:
  1849. viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
  1850. break;
  1851. case UNICHROME_K8M890:
  1852. case UNICHROME_P4M900:
  1853. viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
  1854. break;
  1855. default:
  1856. viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
  1857. break;
  1858. }
  1859. }
  1860. static void init_tmds_chip_info(void)
  1861. {
  1862. viafb_tmds_trasmitter_identify();
  1863. if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
  1864. output_interface) {
  1865. switch (viaparinfo->chip_info->gfx_chip_name) {
  1866. case UNICHROME_CX700:
  1867. {
  1868. /* we should check support by hardware layout.*/
  1869. if ((viafb_display_hardware_layout ==
  1870. HW_LAYOUT_DVI_ONLY)
  1871. || (viafb_display_hardware_layout ==
  1872. HW_LAYOUT_LCD_DVI)) {
  1873. viaparinfo->chip_info->tmds_chip_info.
  1874. output_interface = INTERFACE_TMDS;
  1875. } else {
  1876. viaparinfo->chip_info->tmds_chip_info.
  1877. output_interface =
  1878. INTERFACE_NONE;
  1879. }
  1880. break;
  1881. }
  1882. case UNICHROME_K8M890:
  1883. case UNICHROME_P4M900:
  1884. case UNICHROME_P4M890:
  1885. /* TMDS on PCIE, we set DFPLOW as default. */
  1886. viaparinfo->chip_info->tmds_chip_info.output_interface =
  1887. INTERFACE_DFP_LOW;
  1888. break;
  1889. default:
  1890. {
  1891. /* set DVP1 default for DVI */
  1892. viaparinfo->chip_info->tmds_chip_info
  1893. .output_interface = INTERFACE_DVP1;
  1894. }
  1895. }
  1896. }
  1897. DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
  1898. viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
  1899. viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
  1900. &viaparinfo->shared->tmds_setting_info);
  1901. }
  1902. static void init_lvds_chip_info(void)
  1903. {
  1904. if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
  1905. viaparinfo->lvds_setting_info->get_lcd_size_method =
  1906. GET_LCD_SIZE_BY_VGA_BIOS;
  1907. else
  1908. viaparinfo->lvds_setting_info->get_lcd_size_method =
  1909. GET_LCD_SIZE_BY_USER_SETTING;
  1910. viafb_lvds_trasmitter_identify();
  1911. viafb_init_lcd_size();
  1912. viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
  1913. viaparinfo->lvds_setting_info);
  1914. if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
  1915. viafb_init_lvds_output_interface(&viaparinfo->chip_info->
  1916. lvds_chip_info2, viaparinfo->lvds_setting_info2);
  1917. }
  1918. /*If CX700,two singel LCD, we need to reassign
  1919. LCD interface to different LVDS port */
  1920. if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
  1921. && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
  1922. if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
  1923. lvds_chip_name) && (INTEGRATED_LVDS ==
  1924. viaparinfo->chip_info->
  1925. lvds_chip_info2.lvds_chip_name)) {
  1926. viaparinfo->chip_info->lvds_chip_info.output_interface =
  1927. INTERFACE_LVDS0;
  1928. viaparinfo->chip_info->lvds_chip_info2.
  1929. output_interface =
  1930. INTERFACE_LVDS1;
  1931. }
  1932. }
  1933. DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
  1934. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  1935. DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
  1936. viaparinfo->chip_info->lvds_chip_info.output_interface);
  1937. DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
  1938. viaparinfo->chip_info->lvds_chip_info.output_interface);
  1939. }
  1940. void viafb_init_dac(int set_iga)
  1941. {
  1942. int i;
  1943. u8 tmp;
  1944. if (set_iga == IGA1) {
  1945. /* access Primary Display's LUT */
  1946. viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
  1947. /* turn off LCK */
  1948. viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
  1949. for (i = 0; i < 256; i++) {
  1950. write_dac_reg(i, palLUT_table[i].red,
  1951. palLUT_table[i].green,
  1952. palLUT_table[i].blue);
  1953. }
  1954. /* turn on LCK */
  1955. viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
  1956. } else {
  1957. tmp = viafb_read_reg(VIACR, CR6A);
  1958. /* access Secondary Display's LUT */
  1959. viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
  1960. viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
  1961. for (i = 0; i < 256; i++) {
  1962. write_dac_reg(i, palLUT_table[i].red,
  1963. palLUT_table[i].green,
  1964. palLUT_table[i].blue);
  1965. }
  1966. /* set IGA1 DAC for default */
  1967. viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
  1968. viafb_write_reg(CR6A, VIACR, tmp);
  1969. }
  1970. }
  1971. static void device_screen_off(void)
  1972. {
  1973. /* turn off CRT screen (IGA1) */
  1974. viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
  1975. }
  1976. static void device_screen_on(void)
  1977. {
  1978. /* turn on CRT screen (IGA1) */
  1979. viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
  1980. }
  1981. static void set_display_channel(void)
  1982. {
  1983. /*If viafb_LCD2_ON, on cx700, internal lvds's information
  1984. is keeped on lvds_setting_info2 */
  1985. if (viafb_LCD2_ON &&
  1986. viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
  1987. /* For dual channel LCD: */
  1988. /* Set to Dual LVDS channel. */
  1989. viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
  1990. } else if (viafb_LCD_ON && viafb_DVI_ON) {
  1991. /* For LCD+DFP: */
  1992. /* Set to LVDS1 + TMDS channel. */
  1993. viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
  1994. } else if (viafb_DVI_ON) {
  1995. /* Set to single TMDS channel. */
  1996. viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
  1997. } else if (viafb_LCD_ON) {
  1998. if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
  1999. /* For dual channel LCD: */
  2000. /* Set to Dual LVDS channel. */
  2001. viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
  2002. } else {
  2003. /* Set to LVDS0 + LVDS1 channel. */
  2004. viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
  2005. }
  2006. }
  2007. }
  2008. int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
  2009. struct VideoModeTable *vmode_tbl1, int video_bpp1)
  2010. {
  2011. int i, j;
  2012. int port;
  2013. u8 value, index, mask;
  2014. struct crt_mode_table *crt_timing;
  2015. struct crt_mode_table *crt_timing1 = NULL;
  2016. device_screen_off();
  2017. crt_timing = vmode_tbl->crtc;
  2018. if (viafb_SAMM_ON == 1) {
  2019. crt_timing1 = vmode_tbl1->crtc;
  2020. }
  2021. inb(VIAStatus);
  2022. outb(0x00, VIAAR);
  2023. /* Write Common Setting for Video Mode */
  2024. switch (viaparinfo->chip_info->gfx_chip_name) {
  2025. case UNICHROME_CLE266:
  2026. viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
  2027. break;
  2028. case UNICHROME_K400:
  2029. viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
  2030. break;
  2031. case UNICHROME_K800:
  2032. case UNICHROME_PM800:
  2033. viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
  2034. break;
  2035. case UNICHROME_CN700:
  2036. case UNICHROME_K8M890:
  2037. case UNICHROME_P4M890:
  2038. case UNICHROME_P4M900:
  2039. viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
  2040. break;
  2041. case UNICHROME_CX700:
  2042. case UNICHROME_VX800:
  2043. viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
  2044. break;
  2045. case UNICHROME_VX855:
  2046. viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
  2047. break;
  2048. }
  2049. device_off();
  2050. /* Fill VPIT Parameters */
  2051. /* Write Misc Register */
  2052. outb(VPIT.Misc, VIAWMisc);
  2053. /* Write Sequencer */
  2054. for (i = 1; i <= StdSR; i++) {
  2055. outb(i, VIASR);
  2056. outb(VPIT.SR[i - 1], VIASR + 1);
  2057. }
  2058. viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
  2059. viafb_set_iga_path();
  2060. /* Write CRTC */
  2061. viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
  2062. /* Write Graphic Controller */
  2063. for (i = 0; i < StdGR; i++) {
  2064. outb(i, VIAGR);
  2065. outb(VPIT.GR[i], VIAGR + 1);
  2066. }
  2067. /* Write Attribute Controller */
  2068. for (i = 0; i < StdAR; i++) {
  2069. inb(VIAStatus);
  2070. outb(i, VIAAR);
  2071. outb(VPIT.AR[i], VIAAR);
  2072. }
  2073. inb(VIAStatus);
  2074. outb(0x20, VIAAR);
  2075. /* Update Patch Register */
  2076. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
  2077. || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
  2078. && vmode_tbl->crtc[0].crtc.hor_addr == 1024
  2079. && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
  2080. for (j = 0; j < res_patch_table[0].table_length; j++) {
  2081. index = res_patch_table[0].io_reg_table[j].index;
  2082. port = res_patch_table[0].io_reg_table[j].port;
  2083. value = res_patch_table[0].io_reg_table[j].value;
  2084. mask = res_patch_table[0].io_reg_table[j].mask;
  2085. viafb_write_reg_mask(index, port, value, mask);
  2086. }
  2087. }
  2088. viafb_set_primary_pitch(viafbinfo->fix.line_length);
  2089. viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
  2090. : viafbinfo->fix.line_length);
  2091. viafb_set_primary_color_depth(viaparinfo->depth);
  2092. viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
  2093. : viaparinfo->depth);
  2094. /* Update Refresh Rate Setting */
  2095. /* Clear On Screen */
  2096. /* CRT set mode */
  2097. if (viafb_CRT_ON) {
  2098. if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
  2099. IGA2)) {
  2100. viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
  2101. video_bpp1 / 8,
  2102. viaparinfo->crt_setting_info->iga_path);
  2103. } else {
  2104. viafb_fill_crtc_timing(crt_timing, vmode_tbl,
  2105. video_bpp / 8,
  2106. viaparinfo->crt_setting_info->iga_path);
  2107. }
  2108. set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
  2109. /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
  2110. to 8 alignment (1368),there is several pixels (2 pixels)
  2111. on right side of screen. */
  2112. if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
  2113. viafb_unlock_crt();
  2114. viafb_write_reg(CR02, VIACR,
  2115. viafb_read_reg(VIACR, CR02) - 1);
  2116. viafb_lock_crt();
  2117. }
  2118. }
  2119. if (viafb_DVI_ON) {
  2120. if (viafb_SAMM_ON &&
  2121. (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
  2122. viafb_dvi_set_mode(viafb_get_mode
  2123. (viaparinfo->tmds_setting_info->h_active,
  2124. viaparinfo->tmds_setting_info->
  2125. v_active),
  2126. video_bpp1, viaparinfo->
  2127. tmds_setting_info->iga_path);
  2128. } else {
  2129. viafb_dvi_set_mode(viafb_get_mode
  2130. (viaparinfo->tmds_setting_info->h_active,
  2131. viaparinfo->
  2132. tmds_setting_info->v_active),
  2133. video_bpp, viaparinfo->
  2134. tmds_setting_info->iga_path);
  2135. }
  2136. }
  2137. if (viafb_LCD_ON) {
  2138. if (viafb_SAMM_ON &&
  2139. (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
  2140. viaparinfo->lvds_setting_info->bpp = video_bpp1;
  2141. viafb_lcd_set_mode(crt_timing1, viaparinfo->
  2142. lvds_setting_info,
  2143. &viaparinfo->chip_info->lvds_chip_info);
  2144. } else {
  2145. /* IGA1 doesn't have LCD scaling, so set it center. */
  2146. if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
  2147. viaparinfo->lvds_setting_info->display_method =
  2148. LCD_CENTERING;
  2149. }
  2150. viaparinfo->lvds_setting_info->bpp = video_bpp;
  2151. viafb_lcd_set_mode(crt_timing, viaparinfo->
  2152. lvds_setting_info,
  2153. &viaparinfo->chip_info->lvds_chip_info);
  2154. }
  2155. }
  2156. if (viafb_LCD2_ON) {
  2157. if (viafb_SAMM_ON &&
  2158. (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
  2159. viaparinfo->lvds_setting_info2->bpp = video_bpp1;
  2160. viafb_lcd_set_mode(crt_timing1, viaparinfo->
  2161. lvds_setting_info2,
  2162. &viaparinfo->chip_info->lvds_chip_info2);
  2163. } else {
  2164. /* IGA1 doesn't have LCD scaling, so set it center. */
  2165. if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
  2166. viaparinfo->lvds_setting_info2->display_method =
  2167. LCD_CENTERING;
  2168. }
  2169. viaparinfo->lvds_setting_info2->bpp = video_bpp;
  2170. viafb_lcd_set_mode(crt_timing, viaparinfo->
  2171. lvds_setting_info2,
  2172. &viaparinfo->chip_info->lvds_chip_info2);
  2173. }
  2174. }
  2175. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
  2176. && (viafb_LCD_ON || viafb_DVI_ON))
  2177. set_display_channel();
  2178. /* If set mode normally, save resolution information for hot-plug . */
  2179. if (!viafb_hotplug) {
  2180. viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
  2181. viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
  2182. viafb_hotplug_bpp = video_bpp;
  2183. viafb_hotplug_refresh = viafb_refresh;
  2184. if (viafb_DVI_ON)
  2185. viafb_DeviceStatus = DVI_Device;
  2186. else
  2187. viafb_DeviceStatus = CRT_Device;
  2188. }
  2189. device_on();
  2190. if (viafb_SAMM_ON == 1)
  2191. viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
  2192. device_screen_on();
  2193. return 1;
  2194. }
  2195. int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
  2196. {
  2197. int i;
  2198. for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
  2199. if ((hres == res_map_refresh_tbl[i].hres)
  2200. && (vres == res_map_refresh_tbl[i].vres)
  2201. && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
  2202. return res_map_refresh_tbl[i].pixclock;
  2203. }
  2204. return RES_640X480_60HZ_PIXCLOCK;
  2205. }
  2206. int viafb_get_refresh(int hres, int vres, u32 long_refresh)
  2207. {
  2208. #define REFRESH_TOLERANCE 3
  2209. int i, nearest = -1, diff = REFRESH_TOLERANCE;
  2210. for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
  2211. if ((hres == res_map_refresh_tbl[i].hres)
  2212. && (vres == res_map_refresh_tbl[i].vres)
  2213. && (diff > (abs(long_refresh -
  2214. res_map_refresh_tbl[i].vmode_refresh)))) {
  2215. diff = abs(long_refresh - res_map_refresh_tbl[i].
  2216. vmode_refresh);
  2217. nearest = i;
  2218. }
  2219. }
  2220. #undef REFRESH_TOLERANCE
  2221. if (nearest > 0)
  2222. return res_map_refresh_tbl[nearest].vmode_refresh;
  2223. return 60;
  2224. }
  2225. static void device_off(void)
  2226. {
  2227. viafb_crt_disable();
  2228. viafb_dvi_disable();
  2229. viafb_lcd_disable();
  2230. }
  2231. static void device_on(void)
  2232. {
  2233. if (viafb_CRT_ON == 1)
  2234. viafb_crt_enable();
  2235. if (viafb_DVI_ON == 1)
  2236. viafb_dvi_enable();
  2237. if (viafb_LCD_ON == 1)
  2238. viafb_lcd_enable();
  2239. }
  2240. void viafb_crt_disable(void)
  2241. {
  2242. viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
  2243. }
  2244. void viafb_crt_enable(void)
  2245. {
  2246. viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
  2247. }
  2248. static void enable_second_display_channel(void)
  2249. {
  2250. /* to enable second display channel. */
  2251. viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
  2252. viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
  2253. viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
  2254. }
  2255. static void disable_second_display_channel(void)
  2256. {
  2257. /* to disable second display channel. */
  2258. viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
  2259. viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
  2260. viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
  2261. }
  2262. void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
  2263. *p_gfx_dpa_setting)
  2264. {
  2265. switch (output_interface) {
  2266. case INTERFACE_DVP0:
  2267. {
  2268. /* DVP0 Clock Polarity and Adjust: */
  2269. viafb_write_reg_mask(CR96, VIACR,
  2270. p_gfx_dpa_setting->DVP0, 0x0F);
  2271. /* DVP0 Clock and Data Pads Driving: */
  2272. viafb_write_reg_mask(SR1E, VIASR,
  2273. p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
  2274. viafb_write_reg_mask(SR2A, VIASR,
  2275. p_gfx_dpa_setting->DVP0ClockDri_S1,
  2276. BIT4);
  2277. viafb_write_reg_mask(SR1B, VIASR,
  2278. p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
  2279. viafb_write_reg_mask(SR2A, VIASR,
  2280. p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
  2281. break;
  2282. }
  2283. case INTERFACE_DVP1:
  2284. {
  2285. /* DVP1 Clock Polarity and Adjust: */
  2286. viafb_write_reg_mask(CR9B, VIACR,
  2287. p_gfx_dpa_setting->DVP1, 0x0F);
  2288. /* DVP1 Clock and Data Pads Driving: */
  2289. viafb_write_reg_mask(SR65, VIASR,
  2290. p_gfx_dpa_setting->DVP1Driving, 0x0F);
  2291. break;
  2292. }
  2293. case INTERFACE_DFP_HIGH:
  2294. {
  2295. viafb_write_reg_mask(CR97, VIACR,
  2296. p_gfx_dpa_setting->DFPHigh, 0x0F);
  2297. break;
  2298. }
  2299. case INTERFACE_DFP_LOW:
  2300. {
  2301. viafb_write_reg_mask(CR99, VIACR,
  2302. p_gfx_dpa_setting->DFPLow, 0x0F);
  2303. break;
  2304. }
  2305. case INTERFACE_DFP:
  2306. {
  2307. viafb_write_reg_mask(CR97, VIACR,
  2308. p_gfx_dpa_setting->DFPHigh, 0x0F);
  2309. viafb_write_reg_mask(CR99, VIACR,
  2310. p_gfx_dpa_setting->DFPLow, 0x0F);
  2311. break;
  2312. }
  2313. }
  2314. }
  2315. /*According var's xres, yres fill var's other timing information*/
  2316. void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
  2317. struct VideoModeTable *vmode_tbl)
  2318. {
  2319. struct crt_mode_table *crt_timing = NULL;
  2320. struct display_timing crt_reg;
  2321. int i = 0, index = 0;
  2322. crt_timing = vmode_tbl->crtc;
  2323. for (i = 0; i < vmode_tbl->mode_array; i++) {
  2324. index = i;
  2325. if (crt_timing[i].refresh_rate == refresh)
  2326. break;
  2327. }
  2328. crt_reg = crt_timing[index].crtc;
  2329. var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
  2330. var->left_margin =
  2331. crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
  2332. var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
  2333. var->hsync_len = crt_reg.hor_sync_end;
  2334. var->upper_margin =
  2335. crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
  2336. var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
  2337. var->vsync_len = crt_reg.ver_sync_end;
  2338. }