siimage.c 22 KB

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  1. /*
  2. * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
  3. * Copyright (C) 2003 Red Hat <alan@redhat.com>
  4. * Copyright (C) 2007 MontaVista Software, Inc.
  5. * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  6. *
  7. * May be copied or modified under the terms of the GNU General Public License
  8. *
  9. * Documentation for CMD680:
  10. * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  11. *
  12. * Documentation for SiI 3112:
  13. * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  14. *
  15. * Errata and other documentation only available under NDA.
  16. *
  17. *
  18. * FAQ Items:
  19. * If you are using Marvell SATA-IDE adapters with Maxtor drives
  20. * ensure the system is set up for ATA100/UDMA5 not UDMA6.
  21. *
  22. * If you are using WD drives with SATA bridges you must set the
  23. * drive to "Single". "Master" will hang
  24. *
  25. * If you have strange problems with nVidia chipset systems please
  26. * see the SI support documentation and update your system BIOS
  27. * if necessary
  28. *
  29. * The Dell DRAC4 has some interesting features including effectively hot
  30. * unplugging/replugging the virtual CD interface when the DRAC is reset.
  31. * This often causes drivers/ide/siimage to panic but is ok with the rather
  32. * smarter code in libata.
  33. *
  34. * TODO:
  35. * - IORDY fixes
  36. * - VDMA support
  37. */
  38. #include <linux/types.h>
  39. #include <linux/module.h>
  40. #include <linux/pci.h>
  41. #include <linux/hdreg.h>
  42. #include <linux/ide.h>
  43. #include <linux/init.h>
  44. #include <asm/io.h>
  45. /**
  46. * pdev_is_sata - check if device is SATA
  47. * @pdev: PCI device to check
  48. *
  49. * Returns true if this is a SATA controller
  50. */
  51. static int pdev_is_sata(struct pci_dev *pdev)
  52. {
  53. #ifdef CONFIG_BLK_DEV_IDE_SATA
  54. switch(pdev->device) {
  55. case PCI_DEVICE_ID_SII_3112:
  56. case PCI_DEVICE_ID_SII_1210SA:
  57. return 1;
  58. case PCI_DEVICE_ID_SII_680:
  59. return 0;
  60. }
  61. BUG();
  62. #endif
  63. return 0;
  64. }
  65. /**
  66. * is_sata - check if hwif is SATA
  67. * @hwif: interface to check
  68. *
  69. * Returns true if this is a SATA controller
  70. */
  71. static inline int is_sata(ide_hwif_t *hwif)
  72. {
  73. return pdev_is_sata(to_pci_dev(hwif->dev));
  74. }
  75. /**
  76. * siimage_selreg - return register base
  77. * @hwif: interface
  78. * @r: config offset
  79. *
  80. * Turn a config register offset into the right address in either
  81. * PCI space or MMIO space to access the control register in question
  82. * Thankfully this is a configuration operation so isnt performance
  83. * criticial.
  84. */
  85. static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  86. {
  87. unsigned long base = (unsigned long)hwif->hwif_data;
  88. base += 0xA0 + r;
  89. if(hwif->mmio)
  90. base += (hwif->channel << 6);
  91. else
  92. base += (hwif->channel << 4);
  93. return base;
  94. }
  95. /**
  96. * siimage_seldev - return register base
  97. * @hwif: interface
  98. * @r: config offset
  99. *
  100. * Turn a config register offset into the right address in either
  101. * PCI space or MMIO space to access the control register in question
  102. * including accounting for the unit shift.
  103. */
  104. static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
  105. {
  106. ide_hwif_t *hwif = HWIF(drive);
  107. unsigned long base = (unsigned long)hwif->hwif_data;
  108. base += 0xA0 + r;
  109. if(hwif->mmio)
  110. base += (hwif->channel << 6);
  111. else
  112. base += (hwif->channel << 4);
  113. base |= drive->select.b.unit << drive->select.b.unit;
  114. return base;
  115. }
  116. /**
  117. * sil_udma_filter - compute UDMA mask
  118. * @drive: IDE device
  119. *
  120. * Compute the available UDMA speeds for the device on the interface.
  121. *
  122. * For the CMD680 this depends on the clocking mode (scsc), for the
  123. * SI3112 SATA controller life is a bit simpler.
  124. */
  125. static u8 sil_pata_udma_filter(ide_drive_t *drive)
  126. {
  127. ide_hwif_t *hwif = drive->hwif;
  128. struct pci_dev *dev = to_pci_dev(hwif->dev);
  129. unsigned long base = (unsigned long) hwif->hwif_data;
  130. u8 mask = 0, scsc = 0;
  131. if (hwif->mmio)
  132. scsc = hwif->INB(base + 0x4A);
  133. else
  134. pci_read_config_byte(dev, 0x8A, &scsc);
  135. if ((scsc & 0x30) == 0x10) /* 133 */
  136. mask = ATA_UDMA6;
  137. else if ((scsc & 0x30) == 0x20) /* 2xPCI */
  138. mask = ATA_UDMA6;
  139. else if ((scsc & 0x30) == 0x00) /* 100 */
  140. mask = ATA_UDMA5;
  141. else /* Disabled ? */
  142. BUG();
  143. return mask;
  144. }
  145. static u8 sil_sata_udma_filter(ide_drive_t *drive)
  146. {
  147. return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
  148. }
  149. /**
  150. * sil_set_pio_mode - set host controller for PIO mode
  151. * @drive: drive
  152. * @pio: PIO mode number
  153. *
  154. * Load the timing settings for this device mode into the
  155. * controller. If we are in PIO mode 3 or 4 turn on IORDY
  156. * monitoring (bit 9). The TF timing is bits 31:16
  157. */
  158. static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
  159. {
  160. const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
  161. const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
  162. ide_hwif_t *hwif = HWIF(drive);
  163. ide_drive_t *pair = ide_get_paired_drive(drive);
  164. u32 speedt = 0;
  165. u16 speedp = 0;
  166. unsigned long addr = siimage_seldev(drive, 0x04);
  167. unsigned long tfaddr = siimage_selreg(hwif, 0x02);
  168. unsigned long base = (unsigned long)hwif->hwif_data;
  169. u8 tf_pio = pio;
  170. u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
  171. : (hwif->mmio ? 0xB4 : 0x80);
  172. u8 mode = 0;
  173. u8 unit = drive->select.b.unit;
  174. /* trim *taskfile* PIO to the slowest of the master/slave */
  175. if (pair->present) {
  176. u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
  177. if (pair_pio < tf_pio)
  178. tf_pio = pair_pio;
  179. }
  180. /* cheat for now and use the docs */
  181. speedp = data_speed[pio];
  182. speedt = tf_speed[tf_pio];
  183. if (hwif->mmio) {
  184. hwif->OUTW(speedp, addr);
  185. hwif->OUTW(speedt, tfaddr);
  186. /* Now set up IORDY */
  187. if (pio > 2)
  188. hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
  189. else
  190. hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
  191. mode = hwif->INB(base + addr_mask);
  192. mode &= ~(unit ? 0x30 : 0x03);
  193. mode |= (unit ? 0x10 : 0x01);
  194. hwif->OUTB(mode, base + addr_mask);
  195. } else {
  196. struct pci_dev *dev = to_pci_dev(hwif->dev);
  197. pci_write_config_word(dev, addr, speedp);
  198. pci_write_config_word(dev, tfaddr, speedt);
  199. pci_read_config_word(dev, tfaddr - 2, &speedp);
  200. speedp &= ~0x200;
  201. /* Set IORDY for mode 3 or 4 */
  202. if (pio > 2)
  203. speedp |= 0x200;
  204. pci_write_config_word(dev, tfaddr - 2, speedp);
  205. pci_read_config_byte(dev, addr_mask, &mode);
  206. mode &= ~(unit ? 0x30 : 0x03);
  207. mode |= (unit ? 0x10 : 0x01);
  208. pci_write_config_byte(dev, addr_mask, mode);
  209. }
  210. }
  211. /**
  212. * sil_set_dma_mode - set host controller for DMA mode
  213. * @drive: drive
  214. * @speed: DMA mode
  215. *
  216. * Tune the SiI chipset for the desired DMA mode.
  217. */
  218. static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
  219. {
  220. u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
  221. u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
  222. u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
  223. ide_hwif_t *hwif = HWIF(drive);
  224. struct pci_dev *dev = to_pci_dev(hwif->dev);
  225. u16 ultra = 0, multi = 0;
  226. u8 mode = 0, unit = drive->select.b.unit;
  227. unsigned long base = (unsigned long)hwif->hwif_data;
  228. u8 scsc = 0, addr_mask = ((hwif->channel) ?
  229. ((hwif->mmio) ? 0xF4 : 0x84) :
  230. ((hwif->mmio) ? 0xB4 : 0x80));
  231. unsigned long ma = siimage_seldev(drive, 0x08);
  232. unsigned long ua = siimage_seldev(drive, 0x0C);
  233. if (hwif->mmio) {
  234. scsc = hwif->INB(base + 0x4A);
  235. mode = hwif->INB(base + addr_mask);
  236. multi = hwif->INW(ma);
  237. ultra = hwif->INW(ua);
  238. } else {
  239. pci_read_config_byte(dev, 0x8A, &scsc);
  240. pci_read_config_byte(dev, addr_mask, &mode);
  241. pci_read_config_word(dev, ma, &multi);
  242. pci_read_config_word(dev, ua, &ultra);
  243. }
  244. mode &= ~((unit) ? 0x30 : 0x03);
  245. ultra &= ~0x3F;
  246. scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
  247. scsc = is_sata(hwif) ? 1 : scsc;
  248. if (speed >= XFER_UDMA_0) {
  249. multi = dma[2];
  250. ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
  251. ultra5[speed - XFER_UDMA_0]);
  252. mode |= (unit ? 0x30 : 0x03);
  253. } else {
  254. multi = dma[speed - XFER_MW_DMA_0];
  255. mode |= (unit ? 0x20 : 0x02);
  256. }
  257. if (hwif->mmio) {
  258. hwif->OUTB(mode, base + addr_mask);
  259. hwif->OUTW(multi, ma);
  260. hwif->OUTW(ultra, ua);
  261. } else {
  262. pci_write_config_byte(dev, addr_mask, mode);
  263. pci_write_config_word(dev, ma, multi);
  264. pci_write_config_word(dev, ua, ultra);
  265. }
  266. }
  267. /* returns 1 if dma irq issued, 0 otherwise */
  268. static int siimage_io_dma_test_irq(ide_drive_t *drive)
  269. {
  270. ide_hwif_t *hwif = HWIF(drive);
  271. struct pci_dev *dev = to_pci_dev(hwif->dev);
  272. u8 dma_altstat = 0;
  273. unsigned long addr = siimage_selreg(hwif, 1);
  274. /* return 1 if INTR asserted */
  275. if ((hwif->INB(hwif->dma_status) & 4) == 4)
  276. return 1;
  277. /* return 1 if Device INTR asserted */
  278. pci_read_config_byte(dev, addr, &dma_altstat);
  279. if (dma_altstat & 8)
  280. return 0; //return 1;
  281. return 0;
  282. }
  283. /**
  284. * siimage_mmio_dma_test_irq - check we caused an IRQ
  285. * @drive: drive we are testing
  286. *
  287. * Check if we caused an IDE DMA interrupt. We may also have caused
  288. * SATA status interrupts, if so we clean them up and continue.
  289. */
  290. static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
  291. {
  292. ide_hwif_t *hwif = HWIF(drive);
  293. unsigned long addr = siimage_selreg(hwif, 0x1);
  294. void __iomem *sata_error_addr
  295. = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
  296. if (sata_error_addr) {
  297. unsigned long base = (unsigned long)hwif->hwif_data;
  298. u32 ext_stat = readl((void __iomem *)(base + 0x10));
  299. u8 watchdog = 0;
  300. if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
  301. u32 sata_error = readl(sata_error_addr);
  302. writel(sata_error, sata_error_addr);
  303. watchdog = (sata_error & 0x00680000) ? 1 : 0;
  304. printk(KERN_WARNING "%s: sata_error = 0x%08x, "
  305. "watchdog = %d, %s\n",
  306. drive->name, sata_error, watchdog,
  307. __func__);
  308. } else {
  309. watchdog = (ext_stat & 0x8000) ? 1 : 0;
  310. }
  311. ext_stat >>= 16;
  312. if (!(ext_stat & 0x0404) && !watchdog)
  313. return 0;
  314. }
  315. /* return 1 if INTR asserted */
  316. if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
  317. return 1;
  318. /* return 1 if Device INTR asserted */
  319. if ((readb((void __iomem *)addr) & 8) == 8)
  320. return 0; //return 1;
  321. return 0;
  322. }
  323. static int siimage_dma_test_irq(ide_drive_t *drive)
  324. {
  325. if (drive->hwif->mmio)
  326. return siimage_mmio_dma_test_irq(drive);
  327. else
  328. return siimage_io_dma_test_irq(drive);
  329. }
  330. /**
  331. * sil_sata_reset_poll - wait for SATA reset
  332. * @drive: drive we are resetting
  333. *
  334. * Poll the SATA phy and see whether it has come back from the dead
  335. * yet.
  336. */
  337. static int sil_sata_reset_poll(ide_drive_t *drive)
  338. {
  339. ide_hwif_t *hwif = drive->hwif;
  340. void __iomem *sata_status_addr
  341. = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
  342. if (sata_status_addr) {
  343. /* SATA Status is available only when in MMIO mode */
  344. u32 sata_stat = readl(sata_status_addr);
  345. if ((sata_stat & 0x03) != 0x03) {
  346. printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
  347. hwif->name, sata_stat);
  348. HWGROUP(drive)->polling = 0;
  349. return ide_started;
  350. }
  351. }
  352. return 0;
  353. }
  354. /**
  355. * sil_sata_pre_reset - reset hook
  356. * @drive: IDE device being reset
  357. *
  358. * For the SATA devices we need to handle recalibration/geometry
  359. * differently
  360. */
  361. static void sil_sata_pre_reset(ide_drive_t *drive)
  362. {
  363. if (drive->media == ide_disk) {
  364. drive->special.b.set_geometry = 0;
  365. drive->special.b.recalibrate = 0;
  366. }
  367. }
  368. /**
  369. * proc_reports_siimage - add siimage controller to proc
  370. * @dev: PCI device
  371. * @clocking: SCSC value
  372. * @name: controller name
  373. *
  374. * Report the clocking mode of the controller and add it to
  375. * the /proc interface layer
  376. */
  377. static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
  378. {
  379. if (!pdev_is_sata(dev)) {
  380. printk(KERN_INFO "%s: BASE CLOCK ", name);
  381. clocking &= 0x03;
  382. switch (clocking) {
  383. case 0x03: printk("DISABLED!\n"); break;
  384. case 0x02: printk("== 2X PCI\n"); break;
  385. case 0x01: printk("== 133\n"); break;
  386. case 0x00: printk("== 100\n"); break;
  387. }
  388. }
  389. }
  390. /**
  391. * setup_mmio_siimage - switch an SI controller into MMIO
  392. * @dev: PCI device we are configuring
  393. * @name: device name
  394. *
  395. * Attempt to put the device into mmio mode. There are some slight
  396. * complications here with certain systems where the mmio bar isnt
  397. * mapped so we have to be sure we can fall back to I/O.
  398. */
  399. static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
  400. {
  401. resource_size_t bar5 = pci_resource_start(dev, 5);
  402. unsigned long barsize = pci_resource_len(dev, 5);
  403. u8 tmpbyte = 0;
  404. void __iomem *ioaddr;
  405. u32 tmp, irq_mask;
  406. /*
  407. * Drop back to PIO if we can't map the mmio. Some
  408. * systems seem to get terminally confused in the PCI
  409. * spaces.
  410. */
  411. if(!request_mem_region(bar5, barsize, name))
  412. {
  413. printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
  414. return 0;
  415. }
  416. ioaddr = ioremap(bar5, barsize);
  417. if (ioaddr == NULL)
  418. {
  419. release_mem_region(bar5, barsize);
  420. return 0;
  421. }
  422. pci_set_master(dev);
  423. pci_set_drvdata(dev, (void *) ioaddr);
  424. if (pdev_is_sata(dev)) {
  425. /* make sure IDE0/1 interrupts are not masked */
  426. irq_mask = (1 << 22) | (1 << 23);
  427. tmp = readl(ioaddr + 0x48);
  428. if (tmp & irq_mask) {
  429. tmp &= ~irq_mask;
  430. writel(tmp, ioaddr + 0x48);
  431. readl(ioaddr + 0x48); /* flush */
  432. }
  433. writel(0, ioaddr + 0x148);
  434. writel(0, ioaddr + 0x1C8);
  435. }
  436. writeb(0, ioaddr + 0xB4);
  437. writeb(0, ioaddr + 0xF4);
  438. tmpbyte = readb(ioaddr + 0x4A);
  439. switch(tmpbyte & 0x30) {
  440. case 0x00:
  441. /* In 100 MHz clocking, try and switch to 133 */
  442. writeb(tmpbyte|0x10, ioaddr + 0x4A);
  443. break;
  444. case 0x10:
  445. /* On 133Mhz clocking */
  446. break;
  447. case 0x20:
  448. /* On PCIx2 clocking */
  449. break;
  450. case 0x30:
  451. /* Clocking is disabled */
  452. /* 133 clock attempt to force it on */
  453. writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
  454. break;
  455. }
  456. tmpbyte = readb(ioaddr + 0x4A);
  457. writeb( 0x72, ioaddr + 0xA1);
  458. writew( 0x328A, ioaddr + 0xA2);
  459. writel(0x62DD62DD, ioaddr + 0xA4);
  460. writel(0x43924392, ioaddr + 0xA8);
  461. writel(0x40094009, ioaddr + 0xAC);
  462. writeb( 0x72, ioaddr + 0xE1);
  463. writew( 0x328A, ioaddr + 0xE2);
  464. writel(0x62DD62DD, ioaddr + 0xE4);
  465. writel(0x43924392, ioaddr + 0xE8);
  466. writel(0x40094009, ioaddr + 0xEC);
  467. if (pdev_is_sata(dev)) {
  468. writel(0xFFFF0000, ioaddr + 0x108);
  469. writel(0xFFFF0000, ioaddr + 0x188);
  470. writel(0x00680000, ioaddr + 0x148);
  471. writel(0x00680000, ioaddr + 0x1C8);
  472. }
  473. proc_reports_siimage(dev, (tmpbyte>>4), name);
  474. return 1;
  475. }
  476. /**
  477. * init_chipset_siimage - set up an SI device
  478. * @dev: PCI device
  479. * @name: device name
  480. *
  481. * Perform the initial PCI set up for this device. Attempt to switch
  482. * to 133MHz clocking if the system isn't already set up to do it.
  483. */
  484. static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
  485. {
  486. u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
  487. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
  488. pci_read_config_byte(dev, 0x8A, &BA5_EN);
  489. if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
  490. if (setup_mmio_siimage(dev, name)) {
  491. return 0;
  492. }
  493. }
  494. pci_write_config_byte(dev, 0x80, 0x00);
  495. pci_write_config_byte(dev, 0x84, 0x00);
  496. pci_read_config_byte(dev, 0x8A, &tmpbyte);
  497. switch(tmpbyte & 0x30) {
  498. case 0x00:
  499. /* 133 clock attempt to force it on */
  500. pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
  501. case 0x30:
  502. /* if clocking is disabled */
  503. /* 133 clock attempt to force it on */
  504. pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
  505. case 0x10:
  506. /* 133 already */
  507. break;
  508. case 0x20:
  509. /* BIOS set PCI x2 clocking */
  510. break;
  511. }
  512. pci_read_config_byte(dev, 0x8A, &tmpbyte);
  513. pci_write_config_byte(dev, 0xA1, 0x72);
  514. pci_write_config_word(dev, 0xA2, 0x328A);
  515. pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
  516. pci_write_config_dword(dev, 0xA8, 0x43924392);
  517. pci_write_config_dword(dev, 0xAC, 0x40094009);
  518. pci_write_config_byte(dev, 0xB1, 0x72);
  519. pci_write_config_word(dev, 0xB2, 0x328A);
  520. pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
  521. pci_write_config_dword(dev, 0xB8, 0x43924392);
  522. pci_write_config_dword(dev, 0xBC, 0x40094009);
  523. proc_reports_siimage(dev, (tmpbyte>>4), name);
  524. return 0;
  525. }
  526. /**
  527. * init_mmio_iops_siimage - set up the iops for MMIO
  528. * @hwif: interface to set up
  529. *
  530. * The basic setup here is fairly simple, we can use standard MMIO
  531. * operations. However we do have to set the taskfile register offsets
  532. * by hand as there isnt a standard defined layout for them this
  533. * time.
  534. *
  535. * The hardware supports buffered taskfiles and also some rather nice
  536. * extended PRD tables. For better SI3112 support use the libata driver
  537. */
  538. static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
  539. {
  540. struct pci_dev *dev = to_pci_dev(hwif->dev);
  541. void *addr = pci_get_drvdata(dev);
  542. u8 ch = hwif->channel;
  543. unsigned long base;
  544. struct ide_io_ports *io_ports = &hwif->io_ports;
  545. /*
  546. * Fill in the basic HWIF bits
  547. */
  548. hwif->host_flags |= IDE_HFLAG_MMIO;
  549. default_hwif_mmiops(hwif);
  550. hwif->hwif_data = addr;
  551. /*
  552. * Now set up the hw. We have to do this ourselves as
  553. * the MMIO layout isnt the same as the standard port
  554. * based I/O
  555. */
  556. memset(io_ports, 0, sizeof(*io_ports));
  557. base = (unsigned long)addr;
  558. if (ch)
  559. base += 0xC0;
  560. else
  561. base += 0x80;
  562. /*
  563. * The buffered task file doesn't have status/control
  564. * so we can't currently use it sanely since we want to
  565. * use LBA48 mode.
  566. */
  567. io_ports->data_addr = base;
  568. io_ports->error_addr = base + 1;
  569. io_ports->nsect_addr = base + 2;
  570. io_ports->lbal_addr = base + 3;
  571. io_ports->lbam_addr = base + 4;
  572. io_ports->lbah_addr = base + 5;
  573. io_ports->device_addr = base + 6;
  574. io_ports->status_addr = base + 7;
  575. io_ports->ctl_addr = base + 10;
  576. if (pdev_is_sata(dev)) {
  577. base = (unsigned long)addr;
  578. if (ch)
  579. base += 0x80;
  580. hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
  581. hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
  582. hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
  583. }
  584. hwif->irq = dev->irq;
  585. hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
  586. hwif->mmio = 1;
  587. }
  588. static int is_dev_seagate_sata(ide_drive_t *drive)
  589. {
  590. const char *s = &drive->id->model[0];
  591. unsigned len;
  592. len = strnlen(s, sizeof(drive->id->model));
  593. if ((len > 4) && (!memcmp(s, "ST", 2))) {
  594. if ((!memcmp(s + len - 2, "AS", 2)) ||
  595. (!memcmp(s + len - 3, "ASL", 3))) {
  596. printk(KERN_INFO "%s: applying pessimistic Seagate "
  597. "errata fix\n", drive->name);
  598. return 1;
  599. }
  600. }
  601. return 0;
  602. }
  603. /**
  604. * sil_quirkproc - post probe fixups
  605. * @drive: drive
  606. *
  607. * Called after drive probe we use this to decide whether the
  608. * Seagate fixup must be applied. This used to be in init_iops but
  609. * that can occur before we know what drives are present.
  610. */
  611. static void __devinit sil_quirkproc(ide_drive_t *drive)
  612. {
  613. ide_hwif_t *hwif = drive->hwif;
  614. /* Try and raise the rqsize */
  615. if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
  616. hwif->rqsize = 128;
  617. }
  618. /**
  619. * init_iops_siimage - set up iops
  620. * @hwif: interface to set up
  621. *
  622. * Do the basic setup for the SIIMAGE hardware interface
  623. * and then do the MMIO setup if we can. This is the first
  624. * look in we get for setting up the hwif so that we
  625. * can get the iops right before using them.
  626. */
  627. static void __devinit init_iops_siimage(ide_hwif_t *hwif)
  628. {
  629. struct pci_dev *dev = to_pci_dev(hwif->dev);
  630. hwif->hwif_data = NULL;
  631. /* Pessimal until we finish probing */
  632. hwif->rqsize = 15;
  633. if (pci_get_drvdata(dev) == NULL)
  634. return;
  635. init_mmio_iops_siimage(hwif);
  636. }
  637. /**
  638. * sil_cable_detect - cable detection
  639. * @hwif: interface to check
  640. *
  641. * Check for the presence of an ATA66 capable cable on the
  642. * interface.
  643. */
  644. static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
  645. {
  646. struct pci_dev *dev = to_pci_dev(hwif->dev);
  647. unsigned long addr = siimage_selreg(hwif, 0);
  648. u8 ata66 = 0;
  649. if (pci_get_drvdata(dev) == NULL)
  650. pci_read_config_byte(dev, addr, &ata66);
  651. else
  652. ata66 = hwif->INB(addr);
  653. return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  654. }
  655. static const struct ide_port_ops sil_pata_port_ops = {
  656. .set_pio_mode = sil_set_pio_mode,
  657. .set_dma_mode = sil_set_dma_mode,
  658. .quirkproc = sil_quirkproc,
  659. .udma_filter = sil_pata_udma_filter,
  660. .cable_detect = sil_cable_detect,
  661. };
  662. static const struct ide_port_ops sil_sata_port_ops = {
  663. .set_pio_mode = sil_set_pio_mode,
  664. .set_dma_mode = sil_set_dma_mode,
  665. .reset_poll = sil_sata_reset_poll,
  666. .pre_reset = sil_sata_pre_reset,
  667. .quirkproc = sil_quirkproc,
  668. .udma_filter = sil_sata_udma_filter,
  669. .cable_detect = sil_cable_detect,
  670. };
  671. static struct ide_dma_ops sil_dma_ops = {
  672. .dma_test_irq = siimage_dma_test_irq,
  673. };
  674. #define DECLARE_SII_DEV(name_str, p_ops) \
  675. { \
  676. .name = name_str, \
  677. .init_chipset = init_chipset_siimage, \
  678. .init_iops = init_iops_siimage, \
  679. .port_ops = p_ops, \
  680. .dma_ops = &sil_dma_ops, \
  681. .pio_mask = ATA_PIO4, \
  682. .mwdma_mask = ATA_MWDMA2, \
  683. .udma_mask = ATA_UDMA6, \
  684. }
  685. static const struct ide_port_info siimage_chipsets[] __devinitdata = {
  686. /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops),
  687. /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops),
  688. /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops)
  689. };
  690. /**
  691. * siimage_init_one - pci layer discovery entry
  692. * @dev: PCI device
  693. * @id: ident table entry
  694. *
  695. * Called by the PCI code when it finds an SI680 or SI3112 controller.
  696. * We then use the IDE PCI generic helper to do most of the work.
  697. */
  698. static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  699. {
  700. struct ide_port_info d;
  701. u8 idx = id->driver_data;
  702. d = siimage_chipsets[idx];
  703. if (idx) {
  704. static int first = 1;
  705. if (first) {
  706. printk(KERN_INFO "siimage: For full SATA support you "
  707. "should use the libata sata_sil module.\n");
  708. first = 0;
  709. }
  710. d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
  711. }
  712. return ide_setup_pci_device(dev, &d);
  713. }
  714. static const struct pci_device_id siimage_pci_tbl[] = {
  715. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
  716. #ifdef CONFIG_BLK_DEV_IDE_SATA
  717. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
  718. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 },
  719. #endif
  720. { 0, },
  721. };
  722. MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
  723. static struct pci_driver driver = {
  724. .name = "SiI_IDE",
  725. .id_table = siimage_pci_tbl,
  726. .probe = siimage_init_one,
  727. };
  728. static int __init siimage_ide_init(void)
  729. {
  730. return ide_pci_register_driver(&driver);
  731. }
  732. module_init(siimage_ide_init);
  733. MODULE_AUTHOR("Andre Hedrick, Alan Cox");
  734. MODULE_DESCRIPTION("PCI driver module for SiI IDE");
  735. MODULE_LICENSE("GPL");