ohci-pci.c 6.3 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. * PCI Bus Glue
  13. *
  14. * This file is licenced under the GPL.
  15. */
  16. #include <linux/jiffies.h>
  17. #ifdef CONFIG_PPC_PMAC
  18. #include <asm/machdep.h>
  19. #include <asm/pmac_feature.h>
  20. #include <asm/pci-bridge.h>
  21. #include <asm/prom.h>
  22. #endif
  23. #ifndef CONFIG_PCI
  24. #error "This file is PCI bus glue. CONFIG_PCI must be defined."
  25. #endif
  26. /*-------------------------------------------------------------------------*/
  27. static int
  28. ohci_pci_reset (struct usb_hcd *hcd)
  29. {
  30. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  31. ohci_hcd_init (ohci);
  32. return ohci_init (ohci);
  33. }
  34. static int __devinit
  35. ohci_pci_start (struct usb_hcd *hcd)
  36. {
  37. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  38. int ret;
  39. if(hcd->self.controller && hcd->self.controller->bus == &pci_bus_type) {
  40. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  41. /* AMD 756, for most chips (early revs), corrupts register
  42. * values on read ... so enable the vendor workaround.
  43. */
  44. if (pdev->vendor == PCI_VENDOR_ID_AMD
  45. && pdev->device == 0x740c) {
  46. ohci->flags = OHCI_QUIRK_AMD756;
  47. ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
  48. // also somewhat erratum 10 (suspend/resume issues)
  49. }
  50. /* FIXME for some of the early AMD 760 southbridges, OHCI
  51. * won't work at all. blacklist them.
  52. */
  53. /* Apple's OHCI driver has a lot of bizarre workarounds
  54. * for this chip. Evidently control and bulk lists
  55. * can get confused. (B&W G3 models, and ...)
  56. */
  57. else if (pdev->vendor == PCI_VENDOR_ID_OPTI
  58. && pdev->device == 0xc861) {
  59. ohci_dbg (ohci,
  60. "WARNING: OPTi workarounds unavailable\n");
  61. }
  62. /* Check for NSC87560. We have to look at the bridge (fn1) to
  63. * identify the USB (fn2). This quirk might apply to more or
  64. * even all NSC stuff.
  65. */
  66. else if (pdev->vendor == PCI_VENDOR_ID_NS) {
  67. struct pci_dev *b;
  68. b = pci_find_slot (pdev->bus->number,
  69. PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
  70. if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
  71. && b->vendor == PCI_VENDOR_ID_NS) {
  72. ohci->flags |= OHCI_QUIRK_SUPERIO;
  73. ohci_dbg (ohci, "Using NSC SuperIO setup\n");
  74. }
  75. }
  76. /* Check for Compaq's ZFMicro chipset, which needs short
  77. * delays before control or bulk queues get re-activated
  78. * in finish_unlinks()
  79. */
  80. else if (pdev->vendor == PCI_VENDOR_ID_COMPAQ
  81. && pdev->device == 0xa0f8) {
  82. ohci->flags |= OHCI_QUIRK_ZFMICRO;
  83. ohci_dbg (ohci,
  84. "enabled Compaq ZFMicro chipset quirk\n");
  85. }
  86. }
  87. /* NOTE: there may have already been a first reset, to
  88. * keep bios/smm irqs from making trouble
  89. */
  90. if ((ret = ohci_run (ohci)) < 0) {
  91. ohci_err (ohci, "can't start\n");
  92. ohci_stop (hcd);
  93. return ret;
  94. }
  95. return 0;
  96. }
  97. #ifdef CONFIG_PM
  98. static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
  99. {
  100. /* root hub was already suspended */
  101. /* FIXME these PMAC things get called in the wrong places. ASIC
  102. * clocks should be turned off AFTER entering D3, and on BEFORE
  103. * trying to enter D0. Evidently the PCI layer doesn't currently
  104. * provide the right sort of platform hooks for this ...
  105. */
  106. #ifdef CONFIG_PPC_PMAC
  107. if (_machine == _MACH_Pmac) {
  108. struct device_node *of_node;
  109. /* Disable USB PAD & cell clock */
  110. of_node = pci_device_to_OF_node (to_pci_dev(hcd->self.controller));
  111. if (of_node)
  112. pmac_call_feature(PMAC_FTR_USB_ENABLE, of_node, 0, 0);
  113. }
  114. #endif /* CONFIG_PPC_PMAC */
  115. return 0;
  116. }
  117. static int ohci_pci_resume (struct usb_hcd *hcd)
  118. {
  119. #ifdef CONFIG_PPC_PMAC
  120. if (_machine == _MACH_Pmac) {
  121. struct device_node *of_node;
  122. /* Re-enable USB PAD & cell clock */
  123. of_node = pci_device_to_OF_node (to_pci_dev(hcd->self.controller));
  124. if (of_node)
  125. pmac_call_feature (PMAC_FTR_USB_ENABLE, of_node, 0, 1);
  126. }
  127. #endif /* CONFIG_PPC_PMAC */
  128. usb_hcd_resume_root_hub(hcd);
  129. return 0;
  130. }
  131. #endif /* CONFIG_PM */
  132. /*-------------------------------------------------------------------------*/
  133. static const struct hc_driver ohci_pci_hc_driver = {
  134. .description = hcd_name,
  135. .product_desc = "OHCI Host Controller",
  136. .hcd_priv_size = sizeof(struct ohci_hcd),
  137. /*
  138. * generic hardware linkage
  139. */
  140. .irq = ohci_irq,
  141. .flags = HCD_MEMORY | HCD_USB11,
  142. /*
  143. * basic lifecycle operations
  144. */
  145. .reset = ohci_pci_reset,
  146. .start = ohci_pci_start,
  147. #ifdef CONFIG_PM
  148. .suspend = ohci_pci_suspend,
  149. .resume = ohci_pci_resume,
  150. #endif
  151. .stop = ohci_stop,
  152. /*
  153. * managing i/o requests and associated device resources
  154. */
  155. .urb_enqueue = ohci_urb_enqueue,
  156. .urb_dequeue = ohci_urb_dequeue,
  157. .endpoint_disable = ohci_endpoint_disable,
  158. /*
  159. * scheduling support
  160. */
  161. .get_frame_number = ohci_get_frame,
  162. /*
  163. * root hub support
  164. */
  165. .hub_status_data = ohci_hub_status_data,
  166. .hub_control = ohci_hub_control,
  167. #ifdef CONFIG_PM
  168. .bus_suspend = ohci_bus_suspend,
  169. .bus_resume = ohci_bus_resume,
  170. #endif
  171. .start_port_reset = ohci_start_port_reset,
  172. };
  173. /*-------------------------------------------------------------------------*/
  174. static const struct pci_device_id pci_ids [] = { {
  175. /* handle any USB OHCI controller */
  176. PCI_DEVICE_CLASS((PCI_CLASS_SERIAL_USB << 8) | 0x10, ~0),
  177. .driver_data = (unsigned long) &ohci_pci_hc_driver,
  178. }, { /* end: all zeroes */ }
  179. };
  180. MODULE_DEVICE_TABLE (pci, pci_ids);
  181. /* pci driver glue; this is a "new style" PCI driver module */
  182. static struct pci_driver ohci_pci_driver = {
  183. .name = (char *) hcd_name,
  184. .id_table = pci_ids,
  185. .owner = THIS_MODULE,
  186. .probe = usb_hcd_pci_probe,
  187. .remove = usb_hcd_pci_remove,
  188. #ifdef CONFIG_PM
  189. .suspend = usb_hcd_pci_suspend,
  190. .resume = usb_hcd_pci_resume,
  191. #endif
  192. };
  193. static int __init ohci_hcd_pci_init (void)
  194. {
  195. printk (KERN_DEBUG "%s: " DRIVER_INFO " (PCI)\n", hcd_name);
  196. if (usb_disabled())
  197. return -ENODEV;
  198. pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
  199. sizeof (struct ed), sizeof (struct td));
  200. return pci_register_driver (&ohci_pci_driver);
  201. }
  202. module_init (ohci_hcd_pci_init);
  203. /*-------------------------------------------------------------------------*/
  204. static void __exit ohci_hcd_pci_cleanup (void)
  205. {
  206. pci_unregister_driver (&ohci_pci_driver);
  207. }
  208. module_exit (ohci_hcd_pci_cleanup);