intel_arch_perfmon.h 1.2 KB

1234567891011121314151617181920212223242526272829303132333435363738394041
  1. #ifndef _ASM_X86_INTEL_ARCH_PERFMON_H
  2. #define _ASM_X86_INTEL_ARCH_PERFMON_H
  3. #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
  4. #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
  5. #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
  6. #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
  7. #define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
  8. #define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
  9. #define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
  10. #define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
  11. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
  12. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
  13. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
  14. #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
  15. (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
  16. #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
  17. union cpuid10_eax {
  18. struct {
  19. unsigned int version_id:8;
  20. unsigned int num_counters:8;
  21. unsigned int bit_width:8;
  22. unsigned int mask_length:8;
  23. } split;
  24. unsigned int full;
  25. };
  26. #ifdef CONFIG_PERF_COUNTERS
  27. extern void init_hw_perf_counters(void);
  28. extern void perf_counters_lapic_init(int nmi);
  29. #else
  30. static inline void init_hw_perf_counters(void) { }
  31. static inline void perf_counters_lapic_init(int nmi) { }
  32. #endif
  33. #endif /* _ASM_X86_INTEL_ARCH_PERFMON_H */