spu_base.c 21 KB

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  1. /*
  2. * Low-level SPU handling
  3. *
  4. * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
  5. *
  6. * Author: Arnd Bergmann <arndb@de.ibm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #undef DEBUG
  23. #include <linux/interrupt.h>
  24. #include <linux/list.h>
  25. #include <linux/module.h>
  26. #include <linux/ptrace.h>
  27. #include <linux/slab.h>
  28. #include <linux/wait.h>
  29. #include <linux/mm.h>
  30. #include <linux/io.h>
  31. #include <linux/mutex.h>
  32. #include <linux/linux_logo.h>
  33. #include <asm/spu.h>
  34. #include <asm/spu_priv1.h>
  35. #include <asm/xmon.h>
  36. #include <asm/prom.h>
  37. #include "spu_priv1_mmio.h"
  38. const struct spu_management_ops *spu_management_ops;
  39. EXPORT_SYMBOL_GPL(spu_management_ops);
  40. const struct spu_priv1_ops *spu_priv1_ops;
  41. EXPORT_SYMBOL_GPL(spu_priv1_ops);
  42. struct cbe_spu_info cbe_spu_info[MAX_NUMNODES];
  43. EXPORT_SYMBOL_GPL(cbe_spu_info);
  44. /*
  45. * Protects cbe_spu_info and spu->number.
  46. */
  47. static DEFINE_SPINLOCK(spu_lock);
  48. /*
  49. * List of all spus in the system.
  50. *
  51. * This list is iterated by callers from irq context and callers that
  52. * want to sleep. Thus modifications need to be done with both
  53. * spu_full_list_lock and spu_full_list_mutex held, while iterating
  54. * through it requires either of these locks.
  55. *
  56. * In addition spu_full_list_lock protects all assignmens to
  57. * spu->mm.
  58. */
  59. static LIST_HEAD(spu_full_list);
  60. static DEFINE_SPINLOCK(spu_full_list_lock);
  61. static DEFINE_MUTEX(spu_full_list_mutex);
  62. void spu_invalidate_slbs(struct spu *spu)
  63. {
  64. struct spu_priv2 __iomem *priv2 = spu->priv2;
  65. if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
  66. out_be64(&priv2->slb_invalidate_all_W, 0UL);
  67. }
  68. EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
  69. /* This is called by the MM core when a segment size is changed, to
  70. * request a flush of all the SPEs using a given mm
  71. */
  72. void spu_flush_all_slbs(struct mm_struct *mm)
  73. {
  74. struct spu *spu;
  75. unsigned long flags;
  76. spin_lock_irqsave(&spu_full_list_lock, flags);
  77. list_for_each_entry(spu, &spu_full_list, full_list) {
  78. if (spu->mm == mm)
  79. spu_invalidate_slbs(spu);
  80. }
  81. spin_unlock_irqrestore(&spu_full_list_lock, flags);
  82. }
  83. /* The hack below stinks... try to do something better one of
  84. * these days... Does it even work properly with NR_CPUS == 1 ?
  85. */
  86. static inline void mm_needs_global_tlbie(struct mm_struct *mm)
  87. {
  88. int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;
  89. /* Global TLBIE broadcast required with SPEs. */
  90. __cpus_setall(&mm->cpu_vm_mask, nr);
  91. }
  92. void spu_associate_mm(struct spu *spu, struct mm_struct *mm)
  93. {
  94. unsigned long flags;
  95. spin_lock_irqsave(&spu_full_list_lock, flags);
  96. spu->mm = mm;
  97. spin_unlock_irqrestore(&spu_full_list_lock, flags);
  98. if (mm)
  99. mm_needs_global_tlbie(mm);
  100. }
  101. EXPORT_SYMBOL_GPL(spu_associate_mm);
  102. static int __spu_trap_invalid_dma(struct spu *spu)
  103. {
  104. pr_debug("%s\n", __FUNCTION__);
  105. spu->dma_callback(spu, SPE_EVENT_INVALID_DMA);
  106. return 0;
  107. }
  108. static int __spu_trap_dma_align(struct spu *spu)
  109. {
  110. pr_debug("%s\n", __FUNCTION__);
  111. spu->dma_callback(spu, SPE_EVENT_DMA_ALIGNMENT);
  112. return 0;
  113. }
  114. static int __spu_trap_error(struct spu *spu)
  115. {
  116. pr_debug("%s\n", __FUNCTION__);
  117. spu->dma_callback(spu, SPE_EVENT_SPE_ERROR);
  118. return 0;
  119. }
  120. static void spu_restart_dma(struct spu *spu)
  121. {
  122. struct spu_priv2 __iomem *priv2 = spu->priv2;
  123. if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
  124. out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
  125. }
  126. static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
  127. {
  128. struct spu_priv2 __iomem *priv2 = spu->priv2;
  129. struct mm_struct *mm = spu->mm;
  130. u64 esid, vsid, llp;
  131. int psize;
  132. pr_debug("%s\n", __FUNCTION__);
  133. if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
  134. /* SLBs are pre-loaded for context switch, so
  135. * we should never get here!
  136. */
  137. printk("%s: invalid access during switch!\n", __func__);
  138. return 1;
  139. }
  140. esid = (ea & ESID_MASK) | SLB_ESID_V;
  141. switch(REGION_ID(ea)) {
  142. case USER_REGION_ID:
  143. #ifdef CONFIG_PPC_MM_SLICES
  144. psize = get_slice_psize(mm, ea);
  145. #else
  146. psize = mm->context.user_psize;
  147. #endif
  148. vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) |
  149. SLB_VSID_USER;
  150. break;
  151. case VMALLOC_REGION_ID:
  152. if (ea < VMALLOC_END)
  153. psize = mmu_vmalloc_psize;
  154. else
  155. psize = mmu_io_psize;
  156. vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
  157. SLB_VSID_KERNEL;
  158. break;
  159. case KERNEL_REGION_ID:
  160. psize = mmu_linear_psize;
  161. vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
  162. SLB_VSID_KERNEL;
  163. break;
  164. default:
  165. /* Future: support kernel segments so that drivers
  166. * can use SPUs.
  167. */
  168. pr_debug("invalid region access at %016lx\n", ea);
  169. return 1;
  170. }
  171. llp = mmu_psize_defs[psize].sllp;
  172. out_be64(&priv2->slb_index_W, spu->slb_replace);
  173. out_be64(&priv2->slb_vsid_RW, vsid | llp);
  174. out_be64(&priv2->slb_esid_RW, esid);
  175. spu->slb_replace++;
  176. if (spu->slb_replace >= 8)
  177. spu->slb_replace = 0;
  178. spu_restart_dma(spu);
  179. spu->stats.slb_flt++;
  180. return 0;
  181. }
  182. extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
  183. static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
  184. {
  185. pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
  186. /* Handle kernel space hash faults immediately.
  187. User hash faults need to be deferred to process context. */
  188. if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
  189. && REGION_ID(ea) != USER_REGION_ID
  190. && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
  191. spu_restart_dma(spu);
  192. return 0;
  193. }
  194. if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
  195. printk("%s: invalid access during switch!\n", __func__);
  196. return 1;
  197. }
  198. spu->dar = ea;
  199. spu->dsisr = dsisr;
  200. mb();
  201. spu->stop_callback(spu);
  202. return 0;
  203. }
  204. static irqreturn_t
  205. spu_irq_class_0(int irq, void *data)
  206. {
  207. struct spu *spu;
  208. spu = data;
  209. spu->class_0_pending = 1;
  210. spu->stop_callback(spu);
  211. return IRQ_HANDLED;
  212. }
  213. int
  214. spu_irq_class_0_bottom(struct spu *spu)
  215. {
  216. unsigned long stat, mask;
  217. unsigned long flags;
  218. spu->class_0_pending = 0;
  219. spin_lock_irqsave(&spu->register_lock, flags);
  220. mask = spu_int_mask_get(spu, 0);
  221. stat = spu_int_stat_get(spu, 0);
  222. stat &= mask;
  223. if (stat & 1) /* invalid DMA alignment */
  224. __spu_trap_dma_align(spu);
  225. if (stat & 2) /* invalid MFC DMA */
  226. __spu_trap_invalid_dma(spu);
  227. if (stat & 4) /* error on SPU */
  228. __spu_trap_error(spu);
  229. spu_int_stat_clear(spu, 0, stat);
  230. spin_unlock_irqrestore(&spu->register_lock, flags);
  231. return (stat & 0x7) ? -EIO : 0;
  232. }
  233. EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
  234. static irqreturn_t
  235. spu_irq_class_1(int irq, void *data)
  236. {
  237. struct spu *spu;
  238. unsigned long stat, mask, dar, dsisr;
  239. spu = data;
  240. /* atomically read & clear class1 status. */
  241. spin_lock(&spu->register_lock);
  242. mask = spu_int_mask_get(spu, 1);
  243. stat = spu_int_stat_get(spu, 1) & mask;
  244. dar = spu_mfc_dar_get(spu);
  245. dsisr = spu_mfc_dsisr_get(spu);
  246. if (stat & 2) /* mapping fault */
  247. spu_mfc_dsisr_set(spu, 0ul);
  248. spu_int_stat_clear(spu, 1, stat);
  249. spin_unlock(&spu->register_lock);
  250. pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
  251. dar, dsisr);
  252. if (stat & 1) /* segment fault */
  253. __spu_trap_data_seg(spu, dar);
  254. if (stat & 2) { /* mapping fault */
  255. __spu_trap_data_map(spu, dar, dsisr);
  256. }
  257. if (stat & 4) /* ls compare & suspend on get */
  258. ;
  259. if (stat & 8) /* ls compare & suspend on put */
  260. ;
  261. return stat ? IRQ_HANDLED : IRQ_NONE;
  262. }
  263. static irqreturn_t
  264. spu_irq_class_2(int irq, void *data)
  265. {
  266. struct spu *spu;
  267. unsigned long stat;
  268. unsigned long mask;
  269. spu = data;
  270. spin_lock(&spu->register_lock);
  271. stat = spu_int_stat_get(spu, 2);
  272. mask = spu_int_mask_get(spu, 2);
  273. /* ignore interrupts we're not waiting for */
  274. stat &= mask;
  275. /*
  276. * mailbox interrupts (0x1 and 0x10) are level triggered.
  277. * mask them now before acknowledging.
  278. */
  279. if (stat & 0x11)
  280. spu_int_mask_and(spu, 2, ~(stat & 0x11));
  281. /* acknowledge all interrupts before the callbacks */
  282. spu_int_stat_clear(spu, 2, stat);
  283. spin_unlock(&spu->register_lock);
  284. pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
  285. if (stat & 1) /* PPC core mailbox */
  286. spu->ibox_callback(spu);
  287. if (stat & 2) /* SPU stop-and-signal */
  288. spu->stop_callback(spu);
  289. if (stat & 4) /* SPU halted */
  290. spu->stop_callback(spu);
  291. if (stat & 8) /* DMA tag group complete */
  292. spu->mfc_callback(spu);
  293. if (stat & 0x10) /* SPU mailbox threshold */
  294. spu->wbox_callback(spu);
  295. spu->stats.class2_intr++;
  296. return stat ? IRQ_HANDLED : IRQ_NONE;
  297. }
  298. static int spu_request_irqs(struct spu *spu)
  299. {
  300. int ret = 0;
  301. if (spu->irqs[0] != NO_IRQ) {
  302. snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
  303. spu->number);
  304. ret = request_irq(spu->irqs[0], spu_irq_class_0,
  305. IRQF_DISABLED,
  306. spu->irq_c0, spu);
  307. if (ret)
  308. goto bail0;
  309. }
  310. if (spu->irqs[1] != NO_IRQ) {
  311. snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
  312. spu->number);
  313. ret = request_irq(spu->irqs[1], spu_irq_class_1,
  314. IRQF_DISABLED,
  315. spu->irq_c1, spu);
  316. if (ret)
  317. goto bail1;
  318. }
  319. if (spu->irqs[2] != NO_IRQ) {
  320. snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
  321. spu->number);
  322. ret = request_irq(spu->irqs[2], spu_irq_class_2,
  323. IRQF_DISABLED,
  324. spu->irq_c2, spu);
  325. if (ret)
  326. goto bail2;
  327. }
  328. return 0;
  329. bail2:
  330. if (spu->irqs[1] != NO_IRQ)
  331. free_irq(spu->irqs[1], spu);
  332. bail1:
  333. if (spu->irqs[0] != NO_IRQ)
  334. free_irq(spu->irqs[0], spu);
  335. bail0:
  336. return ret;
  337. }
  338. static void spu_free_irqs(struct spu *spu)
  339. {
  340. if (spu->irqs[0] != NO_IRQ)
  341. free_irq(spu->irqs[0], spu);
  342. if (spu->irqs[1] != NO_IRQ)
  343. free_irq(spu->irqs[1], spu);
  344. if (spu->irqs[2] != NO_IRQ)
  345. free_irq(spu->irqs[2], spu);
  346. }
  347. static void spu_init_channels(struct spu *spu)
  348. {
  349. static const struct {
  350. unsigned channel;
  351. unsigned count;
  352. } zero_list[] = {
  353. { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
  354. { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
  355. }, count_list[] = {
  356. { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
  357. { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
  358. { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
  359. };
  360. struct spu_priv2 __iomem *priv2;
  361. int i;
  362. priv2 = spu->priv2;
  363. /* initialize all channel data to zero */
  364. for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
  365. int count;
  366. out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
  367. for (count = 0; count < zero_list[i].count; count++)
  368. out_be64(&priv2->spu_chnldata_RW, 0);
  369. }
  370. /* initialize channel counts to meaningful values */
  371. for (i = 0; i < ARRAY_SIZE(count_list); i++) {
  372. out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
  373. out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
  374. }
  375. }
  376. struct spu *spu_alloc_spu(struct spu *req_spu)
  377. {
  378. struct spu *spu, *ret = NULL;
  379. spin_lock(&spu_lock);
  380. list_for_each_entry(spu, &cbe_spu_info[req_spu->node].free_spus, list) {
  381. if (spu == req_spu) {
  382. list_del_init(&spu->list);
  383. pr_debug("Got SPU %d %d\n", spu->number, spu->node);
  384. spu_init_channels(spu);
  385. ret = spu;
  386. break;
  387. }
  388. }
  389. spin_unlock(&spu_lock);
  390. return ret;
  391. }
  392. EXPORT_SYMBOL_GPL(spu_alloc_spu);
  393. struct spu *spu_alloc_node(int node)
  394. {
  395. struct spu *spu = NULL;
  396. spin_lock(&spu_lock);
  397. if (!list_empty(&cbe_spu_info[node].free_spus)) {
  398. spu = list_entry(cbe_spu_info[node].free_spus.next, struct spu,
  399. list);
  400. list_del_init(&spu->list);
  401. pr_debug("Got SPU %d %d\n", spu->number, spu->node);
  402. }
  403. spin_unlock(&spu_lock);
  404. if (spu)
  405. spu_init_channels(spu);
  406. return spu;
  407. }
  408. EXPORT_SYMBOL_GPL(spu_alloc_node);
  409. struct spu *spu_alloc(void)
  410. {
  411. struct spu *spu = NULL;
  412. int node;
  413. for (node = 0; node < MAX_NUMNODES; node++) {
  414. spu = spu_alloc_node(node);
  415. if (spu)
  416. break;
  417. }
  418. return spu;
  419. }
  420. void spu_free(struct spu *spu)
  421. {
  422. spin_lock(&spu_lock);
  423. list_add_tail(&spu->list, &cbe_spu_info[spu->node].free_spus);
  424. spin_unlock(&spu_lock);
  425. }
  426. EXPORT_SYMBOL_GPL(spu_free);
  427. static int spu_shutdown(struct sys_device *sysdev)
  428. {
  429. struct spu *spu = container_of(sysdev, struct spu, sysdev);
  430. spu_free_irqs(spu);
  431. spu_destroy_spu(spu);
  432. return 0;
  433. }
  434. struct sysdev_class spu_sysdev_class = {
  435. set_kset_name("spu"),
  436. .shutdown = spu_shutdown,
  437. };
  438. int spu_add_sysdev_attr(struct sysdev_attribute *attr)
  439. {
  440. struct spu *spu;
  441. mutex_lock(&spu_full_list_mutex);
  442. list_for_each_entry(spu, &spu_full_list, full_list)
  443. sysdev_create_file(&spu->sysdev, attr);
  444. mutex_unlock(&spu_full_list_mutex);
  445. return 0;
  446. }
  447. EXPORT_SYMBOL_GPL(spu_add_sysdev_attr);
  448. int spu_add_sysdev_attr_group(struct attribute_group *attrs)
  449. {
  450. struct spu *spu;
  451. mutex_lock(&spu_full_list_mutex);
  452. list_for_each_entry(spu, &spu_full_list, full_list)
  453. sysfs_create_group(&spu->sysdev.kobj, attrs);
  454. mutex_unlock(&spu_full_list_mutex);
  455. return 0;
  456. }
  457. EXPORT_SYMBOL_GPL(spu_add_sysdev_attr_group);
  458. void spu_remove_sysdev_attr(struct sysdev_attribute *attr)
  459. {
  460. struct spu *spu;
  461. mutex_lock(&spu_full_list_mutex);
  462. list_for_each_entry(spu, &spu_full_list, full_list)
  463. sysdev_remove_file(&spu->sysdev, attr);
  464. mutex_unlock(&spu_full_list_mutex);
  465. }
  466. EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr);
  467. void spu_remove_sysdev_attr_group(struct attribute_group *attrs)
  468. {
  469. struct spu *spu;
  470. mutex_lock(&spu_full_list_mutex);
  471. list_for_each_entry(spu, &spu_full_list, full_list)
  472. sysfs_remove_group(&spu->sysdev.kobj, attrs);
  473. mutex_unlock(&spu_full_list_mutex);
  474. }
  475. EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr_group);
  476. static int spu_create_sysdev(struct spu *spu)
  477. {
  478. int ret;
  479. spu->sysdev.id = spu->number;
  480. spu->sysdev.cls = &spu_sysdev_class;
  481. ret = sysdev_register(&spu->sysdev);
  482. if (ret) {
  483. printk(KERN_ERR "Can't register SPU %d with sysfs\n",
  484. spu->number);
  485. return ret;
  486. }
  487. sysfs_add_device_to_node(&spu->sysdev, spu->node);
  488. return 0;
  489. }
  490. static int __init create_spu(void *data)
  491. {
  492. struct spu *spu;
  493. int ret;
  494. static int number;
  495. unsigned long flags;
  496. struct timespec ts;
  497. ret = -ENOMEM;
  498. spu = kzalloc(sizeof (*spu), GFP_KERNEL);
  499. if (!spu)
  500. goto out;
  501. spin_lock_init(&spu->register_lock);
  502. spin_lock(&spu_lock);
  503. spu->number = number++;
  504. spin_unlock(&spu_lock);
  505. ret = spu_create_spu(spu, data);
  506. if (ret)
  507. goto out_free;
  508. spu_mfc_sdr_setup(spu);
  509. spu_mfc_sr1_set(spu, 0x33);
  510. ret = spu_request_irqs(spu);
  511. if (ret)
  512. goto out_destroy;
  513. ret = spu_create_sysdev(spu);
  514. if (ret)
  515. goto out_free_irqs;
  516. spin_lock(&spu_lock);
  517. list_add(&spu->list, &cbe_spu_info[spu->node].free_spus);
  518. list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus);
  519. cbe_spu_info[spu->node].n_spus++;
  520. spin_unlock(&spu_lock);
  521. mutex_lock(&spu_full_list_mutex);
  522. spin_lock_irqsave(&spu_full_list_lock, flags);
  523. list_add(&spu->full_list, &spu_full_list);
  524. spin_unlock_irqrestore(&spu_full_list_lock, flags);
  525. mutex_unlock(&spu_full_list_mutex);
  526. spu->stats.util_state = SPU_UTIL_IDLE_LOADED;
  527. ktime_get_ts(&ts);
  528. spu->stats.tstamp = timespec_to_ns(&ts);
  529. INIT_LIST_HEAD(&spu->aff_list);
  530. goto out;
  531. out_free_irqs:
  532. spu_free_irqs(spu);
  533. out_destroy:
  534. spu_destroy_spu(spu);
  535. out_free:
  536. kfree(spu);
  537. out:
  538. return ret;
  539. }
  540. static const char *spu_state_names[] = {
  541. "user", "system", "iowait", "idle"
  542. };
  543. static unsigned long long spu_acct_time(struct spu *spu,
  544. enum spu_utilization_state state)
  545. {
  546. struct timespec ts;
  547. unsigned long long time = spu->stats.times[state];
  548. /*
  549. * If the spu is idle or the context is stopped, utilization
  550. * statistics are not updated. Apply the time delta from the
  551. * last recorded state of the spu.
  552. */
  553. if (spu->stats.util_state == state) {
  554. ktime_get_ts(&ts);
  555. time += timespec_to_ns(&ts) - spu->stats.tstamp;
  556. }
  557. return time / NSEC_PER_MSEC;
  558. }
  559. static ssize_t spu_stat_show(struct sys_device *sysdev, char *buf)
  560. {
  561. struct spu *spu = container_of(sysdev, struct spu, sysdev);
  562. return sprintf(buf, "%s %llu %llu %llu %llu "
  563. "%llu %llu %llu %llu %llu %llu %llu %llu\n",
  564. spu_state_names[spu->stats.util_state],
  565. spu_acct_time(spu, SPU_UTIL_USER),
  566. spu_acct_time(spu, SPU_UTIL_SYSTEM),
  567. spu_acct_time(spu, SPU_UTIL_IOWAIT),
  568. spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),
  569. spu->stats.vol_ctx_switch,
  570. spu->stats.invol_ctx_switch,
  571. spu->stats.slb_flt,
  572. spu->stats.hash_flt,
  573. spu->stats.min_flt,
  574. spu->stats.maj_flt,
  575. spu->stats.class2_intr,
  576. spu->stats.libassist);
  577. }
  578. static SYSDEV_ATTR(stat, 0644, spu_stat_show, NULL);
  579. /* Hardcoded affinity idxs for QS20 */
  580. #define SPES_PER_BE 8
  581. static int QS20_reg_idxs[SPES_PER_BE] = { 0, 2, 4, 6, 7, 5, 3, 1 };
  582. static int QS20_reg_memory[SPES_PER_BE] = { 1, 1, 0, 0, 0, 0, 0, 0 };
  583. static struct spu *spu_lookup_reg(int node, u32 reg)
  584. {
  585. struct spu *spu;
  586. list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list) {
  587. if (*(u32 *)get_property(spu_devnode(spu), "reg", NULL) == reg)
  588. return spu;
  589. }
  590. return NULL;
  591. }
  592. static void init_aff_QS20_harcoded(void)
  593. {
  594. int node, i;
  595. struct spu *last_spu, *spu;
  596. u32 reg;
  597. for (node = 0; node < MAX_NUMNODES; node++) {
  598. last_spu = NULL;
  599. for (i = 0; i < SPES_PER_BE; i++) {
  600. reg = QS20_reg_idxs[i];
  601. spu = spu_lookup_reg(node, reg);
  602. if (!spu)
  603. continue;
  604. spu->has_mem_affinity = QS20_reg_memory[reg];
  605. if (last_spu)
  606. list_add_tail(&spu->aff_list,
  607. &last_spu->aff_list);
  608. last_spu = spu;
  609. }
  610. }
  611. }
  612. static int of_has_vicinity(void)
  613. {
  614. struct spu* spu;
  615. spu = list_entry(cbe_spu_info[0].spus.next, struct spu, cbe_list);
  616. return of_find_property(spu_devnode(spu), "vicinity", NULL) != NULL;
  617. }
  618. static struct spu *aff_devnode_spu(int cbe, struct device_node *dn)
  619. {
  620. struct spu *spu;
  621. list_for_each_entry(spu, &cbe_spu_info[cbe].spus, cbe_list)
  622. if (spu_devnode(spu) == dn)
  623. return spu;
  624. return NULL;
  625. }
  626. static struct spu *
  627. aff_node_next_to(int cbe, struct device_node *target, struct device_node *avoid)
  628. {
  629. struct spu *spu;
  630. const phandle *vic_handles;
  631. int lenp, i;
  632. list_for_each_entry(spu, &cbe_spu_info[cbe].spus, cbe_list) {
  633. if (spu_devnode(spu) == avoid)
  634. continue;
  635. vic_handles = get_property(spu_devnode(spu), "vicinity", &lenp);
  636. for (i=0; i < (lenp / sizeof(phandle)); i++) {
  637. if (vic_handles[i] == target->linux_phandle)
  638. return spu;
  639. }
  640. }
  641. return NULL;
  642. }
  643. static void init_aff_fw_vicinity_node(int cbe)
  644. {
  645. struct spu *spu, *last_spu;
  646. struct device_node *vic_dn, *last_spu_dn;
  647. phandle avoid_ph;
  648. const phandle *vic_handles;
  649. const char *name;
  650. int lenp, i, added, mem_aff;
  651. last_spu = list_entry(cbe_spu_info[cbe].spus.next, struct spu, cbe_list);
  652. avoid_ph = 0;
  653. for (added = 1; added < cbe_spu_info[cbe].n_spus; added++) {
  654. last_spu_dn = spu_devnode(last_spu);
  655. vic_handles = get_property(last_spu_dn, "vicinity", &lenp);
  656. for (i = 0; i < (lenp / sizeof(phandle)); i++) {
  657. if (vic_handles[i] == avoid_ph)
  658. continue;
  659. vic_dn = of_find_node_by_phandle(vic_handles[i]);
  660. if (!vic_dn)
  661. continue;
  662. name = get_property(vic_dn, "name", NULL);
  663. if (strcmp(name, "spe") == 0) {
  664. spu = aff_devnode_spu(cbe, vic_dn);
  665. avoid_ph = last_spu_dn->linux_phandle;
  666. }
  667. else {
  668. mem_aff = strcmp(name, "mic-tm") == 0;
  669. spu = aff_node_next_to(cbe, vic_dn, last_spu_dn);
  670. if (!spu)
  671. continue;
  672. if (mem_aff) {
  673. last_spu->has_mem_affinity = 1;
  674. spu->has_mem_affinity = 1;
  675. }
  676. avoid_ph = vic_dn->linux_phandle;
  677. }
  678. list_add_tail(&spu->aff_list, &last_spu->aff_list);
  679. last_spu = spu;
  680. break;
  681. }
  682. }
  683. }
  684. static void init_aff_fw_vicinity(void)
  685. {
  686. int cbe;
  687. /* sets has_mem_affinity for each spu, as long as the
  688. * spu->aff_list list, linking each spu to its neighbors
  689. */
  690. for (cbe = 0; cbe < MAX_NUMNODES; cbe++)
  691. init_aff_fw_vicinity_node(cbe);
  692. }
  693. static int __init init_spu_base(void)
  694. {
  695. int i, ret = 0;
  696. for (i = 0; i < MAX_NUMNODES; i++) {
  697. INIT_LIST_HEAD(&cbe_spu_info[i].spus);
  698. INIT_LIST_HEAD(&cbe_spu_info[i].free_spus);
  699. }
  700. if (!spu_management_ops)
  701. goto out;
  702. /* create sysdev class for spus */
  703. ret = sysdev_class_register(&spu_sysdev_class);
  704. if (ret)
  705. goto out;
  706. ret = spu_enumerate_spus(create_spu);
  707. if (ret < 0) {
  708. printk(KERN_WARNING "%s: Error initializing spus\n",
  709. __FUNCTION__);
  710. goto out_unregister_sysdev_class;
  711. }
  712. if (ret > 0) {
  713. /*
  714. * We cannot put the forward declaration in
  715. * <linux/linux_logo.h> because of conflicting session type
  716. * conflicts for const and __initdata with different compiler
  717. * versions
  718. */
  719. extern const struct linux_logo logo_spe_clut224;
  720. fb_append_extra_logo(&logo_spe_clut224, ret);
  721. }
  722. mutex_lock(&spu_full_list_mutex);
  723. xmon_register_spus(&spu_full_list);
  724. crash_register_spus(&spu_full_list);
  725. mutex_unlock(&spu_full_list_mutex);
  726. spu_add_sysdev_attr(&attr_stat);
  727. if (of_has_vicinity()) {
  728. init_aff_fw_vicinity();
  729. } else {
  730. long root = of_get_flat_dt_root();
  731. if (of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
  732. init_aff_QS20_harcoded();
  733. }
  734. return 0;
  735. out_unregister_sysdev_class:
  736. sysdev_class_unregister(&spu_sysdev_class);
  737. out:
  738. return ret;
  739. }
  740. module_init(init_spu_base);
  741. MODULE_LICENSE("GPL");
  742. MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");