cx88-dvb.c 27 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * MPEG Transport Stream (DVB) routines
  5. *
  6. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  7. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/fs.h>
  27. #include <linux/kthread.h>
  28. #include <linux/file.h>
  29. #include <linux/suspend.h>
  30. #include "cx88.h"
  31. #include "dvb-pll.h"
  32. #include <media/v4l2-common.h>
  33. #include "mt352.h"
  34. #include "mt352_priv.h"
  35. #include "cx88-vp3054-i2c.h"
  36. #include "zl10353.h"
  37. #include "cx22702.h"
  38. #include "or51132.h"
  39. #include "lgdt330x.h"
  40. #include "s5h1409.h"
  41. #include "xc5000.h"
  42. #include "nxt200x.h"
  43. #include "cx24123.h"
  44. #include "isl6421.h"
  45. #include "tuner-xc2028.h"
  46. #include "tuner-xc2028-types.h"
  47. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  48. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  49. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  50. MODULE_LICENSE("GPL");
  51. static unsigned int debug;
  52. module_param(debug, int, 0644);
  53. MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
  54. #define dprintk(level,fmt, arg...) if (debug >= level) \
  55. printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
  56. /* ------------------------------------------------------------------ */
  57. static int dvb_buf_setup(struct videobuf_queue *q,
  58. unsigned int *count, unsigned int *size)
  59. {
  60. struct cx8802_dev *dev = q->priv_data;
  61. dev->ts_packet_size = 188 * 4;
  62. dev->ts_packet_count = 32;
  63. *size = dev->ts_packet_size * dev->ts_packet_count;
  64. *count = 32;
  65. return 0;
  66. }
  67. static int dvb_buf_prepare(struct videobuf_queue *q,
  68. struct videobuf_buffer *vb, enum v4l2_field field)
  69. {
  70. struct cx8802_dev *dev = q->priv_data;
  71. return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
  72. }
  73. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  74. {
  75. struct cx8802_dev *dev = q->priv_data;
  76. cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
  77. }
  78. static void dvb_buf_release(struct videobuf_queue *q,
  79. struct videobuf_buffer *vb)
  80. {
  81. cx88_free_buffer(q, (struct cx88_buffer*)vb);
  82. }
  83. static struct videobuf_queue_ops dvb_qops = {
  84. .buf_setup = dvb_buf_setup,
  85. .buf_prepare = dvb_buf_prepare,
  86. .buf_queue = dvb_buf_queue,
  87. .buf_release = dvb_buf_release,
  88. };
  89. /* ------------------------------------------------------------------ */
  90. static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
  91. {
  92. struct cx8802_dev *dev= fe->dvb->priv;
  93. struct cx8802_driver *drv = NULL;
  94. int ret = 0;
  95. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  96. if (drv) {
  97. if (acquire)
  98. ret = drv->request_acquire(drv);
  99. else
  100. ret = drv->request_release(drv);
  101. }
  102. return ret;
  103. }
  104. /* ------------------------------------------------------------------ */
  105. static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
  106. {
  107. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
  108. static u8 reset [] = { RESET, 0x80 };
  109. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  110. static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
  111. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  112. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  113. mt352_write(fe, clock_config, sizeof(clock_config));
  114. udelay(200);
  115. mt352_write(fe, reset, sizeof(reset));
  116. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  117. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  118. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  119. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  120. return 0;
  121. }
  122. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  123. {
  124. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
  125. static u8 reset [] = { RESET, 0x80 };
  126. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  127. static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
  128. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  129. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  130. mt352_write(fe, clock_config, sizeof(clock_config));
  131. udelay(200);
  132. mt352_write(fe, reset, sizeof(reset));
  133. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  134. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  135. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  136. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  137. return 0;
  138. }
  139. static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
  140. {
  141. static u8 clock_config [] = { 0x89, 0x38, 0x39 };
  142. static u8 reset [] = { 0x50, 0x80 };
  143. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  144. static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  145. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  146. static u8 dntv_extra[] = { 0xB5, 0x7A };
  147. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  148. mt352_write(fe, clock_config, sizeof(clock_config));
  149. udelay(2000);
  150. mt352_write(fe, reset, sizeof(reset));
  151. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  152. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  153. udelay(2000);
  154. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  155. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  156. return 0;
  157. }
  158. static struct mt352_config dvico_fusionhdtv = {
  159. .demod_address = 0x0f,
  160. .demod_init = dvico_fusionhdtv_demod_init,
  161. };
  162. static struct mt352_config dntv_live_dvbt_config = {
  163. .demod_address = 0x0f,
  164. .demod_init = dntv_live_dvbt_demod_init,
  165. };
  166. static struct mt352_config dvico_fusionhdtv_dual = {
  167. .demod_address = 0x0f,
  168. .demod_init = dvico_dual_demod_init,
  169. };
  170. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  171. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
  172. {
  173. static u8 clock_config [] = { 0x89, 0x38, 0x38 };
  174. static u8 reset [] = { 0x50, 0x80 };
  175. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  176. static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  177. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  178. static u8 dntv_extra[] = { 0xB5, 0x7A };
  179. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  180. mt352_write(fe, clock_config, sizeof(clock_config));
  181. udelay(2000);
  182. mt352_write(fe, reset, sizeof(reset));
  183. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  184. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  185. udelay(2000);
  186. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  187. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  188. return 0;
  189. }
  190. static struct mt352_config dntv_live_dvbt_pro_config = {
  191. .demod_address = 0x0f,
  192. .no_tuner = 1,
  193. .demod_init = dntv_live_dvbt_pro_demod_init,
  194. };
  195. #endif
  196. static struct zl10353_config dvico_fusionhdtv_hybrid = {
  197. .demod_address = 0x0f,
  198. .no_tuner = 1,
  199. };
  200. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  201. .demod_address = 0x0f,
  202. .if2 = 45600,
  203. .no_tuner = 1,
  204. };
  205. static struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
  206. .demod_address = 0x0f,
  207. .if2 = 4560,
  208. .no_tuner = 1,
  209. .demod_init = dvico_fusionhdtv_demod_init,
  210. };
  211. static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  212. .demod_address = 0x0f,
  213. };
  214. static struct cx22702_config connexant_refboard_config = {
  215. .demod_address = 0x43,
  216. .output_mode = CX22702_SERIAL_OUTPUT,
  217. };
  218. static struct cx22702_config hauppauge_hvr_config = {
  219. .demod_address = 0x63,
  220. .output_mode = CX22702_SERIAL_OUTPUT,
  221. };
  222. static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  223. {
  224. struct cx8802_dev *dev= fe->dvb->priv;
  225. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  226. return 0;
  227. }
  228. static struct or51132_config pchdtv_hd3000 = {
  229. .demod_address = 0x15,
  230. .set_ts_params = or51132_set_ts_param,
  231. };
  232. static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
  233. {
  234. struct cx8802_dev *dev= fe->dvb->priv;
  235. struct cx88_core *core = dev->core;
  236. dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
  237. if (index == 0)
  238. cx_clear(MO_GP0_IO, 8);
  239. else
  240. cx_set(MO_GP0_IO, 8);
  241. return 0;
  242. }
  243. static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  244. {
  245. struct cx8802_dev *dev= fe->dvb->priv;
  246. if (is_punctured)
  247. dev->ts_gen_cntrl |= 0x04;
  248. else
  249. dev->ts_gen_cntrl &= ~0x04;
  250. return 0;
  251. }
  252. static struct lgdt330x_config fusionhdtv_3_gold = {
  253. .demod_address = 0x0e,
  254. .demod_chip = LGDT3302,
  255. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  256. .set_ts_params = lgdt330x_set_ts_param,
  257. };
  258. static struct lgdt330x_config fusionhdtv_5_gold = {
  259. .demod_address = 0x0e,
  260. .demod_chip = LGDT3303,
  261. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  262. .set_ts_params = lgdt330x_set_ts_param,
  263. };
  264. static struct lgdt330x_config pchdtv_hd5500 = {
  265. .demod_address = 0x59,
  266. .demod_chip = LGDT3303,
  267. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  268. .set_ts_params = lgdt330x_set_ts_param,
  269. };
  270. static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  271. {
  272. struct cx8802_dev *dev= fe->dvb->priv;
  273. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  274. return 0;
  275. }
  276. static struct nxt200x_config ati_hdtvwonder = {
  277. .demod_address = 0x0a,
  278. .set_ts_params = nxt200x_set_ts_param,
  279. };
  280. static int cx24123_set_ts_param(struct dvb_frontend* fe,
  281. int is_punctured)
  282. {
  283. struct cx8802_dev *dev= fe->dvb->priv;
  284. dev->ts_gen_cntrl = 0x02;
  285. return 0;
  286. }
  287. static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
  288. fe_sec_voltage_t voltage)
  289. {
  290. struct cx8802_dev *dev= fe->dvb->priv;
  291. struct cx88_core *core = dev->core;
  292. if (voltage == SEC_VOLTAGE_OFF)
  293. cx_write(MO_GP0_IO, 0x000006fb);
  294. else
  295. cx_write(MO_GP0_IO, 0x000006f9);
  296. if (core->prev_set_voltage)
  297. return core->prev_set_voltage(fe, voltage);
  298. return 0;
  299. }
  300. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  301. fe_sec_voltage_t voltage)
  302. {
  303. struct cx8802_dev *dev= fe->dvb->priv;
  304. struct cx88_core *core = dev->core;
  305. if (voltage == SEC_VOLTAGE_OFF) {
  306. dprintk(1,"LNB Voltage OFF\n");
  307. cx_write(MO_GP0_IO, 0x0000efff);
  308. }
  309. if (core->prev_set_voltage)
  310. return core->prev_set_voltage(fe, voltage);
  311. return 0;
  312. }
  313. static int cx88_xc3028_callback(void *ptr, int command, int arg)
  314. {
  315. struct cx88_core *core = ptr;
  316. switch (command) {
  317. case XC2028_TUNER_RESET:
  318. /* Send the tuner in then out of reset */
  319. dprintk(1, "%s: XC2028_TUNER_RESET %d\n", __FUNCTION__, arg);
  320. switch (core->boardnr) {
  321. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  322. /* GPIO-4 xc3028 tuner */
  323. cx_set(MO_GP0_IO, 0x00001000);
  324. cx_clear(MO_GP0_IO, 0x00000010);
  325. msleep(100);
  326. cx_set(MO_GP0_IO, 0x00000010);
  327. msleep(100);
  328. break;
  329. }
  330. break;
  331. case XC2028_RESET_CLK:
  332. dprintk(1, "%s: XC2028_RESET_CLK %d\n", __FUNCTION__, arg);
  333. break;
  334. default:
  335. dprintk(1, "%s: unknown command %d, arg %d\n", __FUNCTION__,
  336. command, arg);
  337. return -EINVAL;
  338. }
  339. return 0;
  340. }
  341. static struct cx24123_config geniatech_dvbs_config = {
  342. .demod_address = 0x55,
  343. .set_ts_params = cx24123_set_ts_param,
  344. };
  345. static struct cx24123_config hauppauge_novas_config = {
  346. .demod_address = 0x55,
  347. .set_ts_params = cx24123_set_ts_param,
  348. };
  349. static struct cx24123_config kworld_dvbs_100_config = {
  350. .demod_address = 0x15,
  351. .set_ts_params = cx24123_set_ts_param,
  352. .lnb_polarity = 1,
  353. };
  354. static struct s5h1409_config pinnacle_pctv_hd_800i_config = {
  355. .demod_address = 0x32 >> 1,
  356. .output_mode = S5H1409_PARALLEL_OUTPUT,
  357. .gpio = S5H1409_GPIO_ON,
  358. .qam_if = 44000,
  359. .inversion = S5H1409_INVERSION_OFF,
  360. .status_mode = S5H1409_DEMODLOCKING,
  361. .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
  362. };
  363. static struct s5h1409_config dvico_hdtv5_pci_nano_config = {
  364. .demod_address = 0x32 >> 1,
  365. .output_mode = S5H1409_SERIAL_OUTPUT,
  366. .gpio = S5H1409_GPIO_OFF,
  367. .inversion = S5H1409_INVERSION_OFF,
  368. .status_mode = S5H1409_DEMODLOCKING,
  369. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  370. };
  371. static struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
  372. .i2c_address = 0x64,
  373. .if_khz = 5380,
  374. .tuner_callback = cx88_tuner_callback,
  375. };
  376. static struct zl10353_config cx88_geniatech_x8000_mt = {
  377. .demod_address = (0x1e >> 1),
  378. .no_tuner = 1,
  379. };
  380. static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
  381. {
  382. struct dvb_frontend *fe;
  383. struct xc2028_config cfg = {
  384. .i2c_adap = &dev->core->i2c_adap,
  385. .i2c_addr = addr,
  386. .video_dev = dev->core,
  387. };
  388. fe = dvb_attach(xc2028_attach, dev->dvb.frontend, &cfg);
  389. if (!fe) {
  390. printk(KERN_ERR "%s/2: xc3028 attach failed\n",
  391. dev->core->name);
  392. dvb_frontend_detach(dev->dvb.frontend);
  393. dvb_unregister_frontend(dev->dvb.frontend);
  394. dev->dvb.frontend = NULL;
  395. return -EINVAL;
  396. }
  397. printk(KERN_INFO "%s/2: xc3028 attached\n",
  398. dev->core->name);
  399. return 0;
  400. }
  401. static int dvb_register(struct cx8802_dev *dev)
  402. {
  403. /* init struct videobuf_dvb */
  404. dev->dvb.name = dev->core->name;
  405. dev->ts_gen_cntrl = 0x0c;
  406. /* init frontend */
  407. switch (dev->core->boardnr) {
  408. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  409. dev->dvb.frontend = dvb_attach(cx22702_attach,
  410. &connexant_refboard_config,
  411. &dev->core->i2c_adap);
  412. if (dev->dvb.frontend != NULL) {
  413. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  414. &dev->core->i2c_adap,
  415. DVB_PLL_THOMSON_DTT759X);
  416. }
  417. break;
  418. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  419. case CX88_BOARD_CONEXANT_DVB_T1:
  420. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  421. case CX88_BOARD_WINFAST_DTV1000:
  422. dev->dvb.frontend = dvb_attach(cx22702_attach,
  423. &connexant_refboard_config,
  424. &dev->core->i2c_adap);
  425. if (dev->dvb.frontend != NULL) {
  426. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  427. &dev->core->i2c_adap,
  428. DVB_PLL_THOMSON_DTT7579);
  429. }
  430. break;
  431. case CX88_BOARD_WINFAST_DTV2000H:
  432. case CX88_BOARD_HAUPPAUGE_HVR1100:
  433. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  434. case CX88_BOARD_HAUPPAUGE_HVR1300:
  435. case CX88_BOARD_HAUPPAUGE_HVR3000:
  436. dev->dvb.frontend = dvb_attach(cx22702_attach,
  437. &hauppauge_hvr_config,
  438. &dev->core->i2c_adap);
  439. if (dev->dvb.frontend != NULL) {
  440. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  441. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  442. }
  443. break;
  444. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  445. dev->dvb.frontend = dvb_attach(mt352_attach,
  446. &dvico_fusionhdtv,
  447. &dev->core->i2c_adap);
  448. if (dev->dvb.frontend != NULL) {
  449. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  450. NULL, DVB_PLL_THOMSON_DTT7579);
  451. break;
  452. }
  453. /* ZL10353 replaces MT352 on later cards */
  454. dev->dvb.frontend = dvb_attach(zl10353_attach,
  455. &dvico_fusionhdtv_plus_v1_1,
  456. &dev->core->i2c_adap);
  457. if (dev->dvb.frontend != NULL) {
  458. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  459. NULL, DVB_PLL_THOMSON_DTT7579);
  460. }
  461. break;
  462. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  463. /* The tin box says DEE1601, but it seems to be DTT7579
  464. * compatible, with a slightly different MT352 AGC gain. */
  465. dev->dvb.frontend = dvb_attach(mt352_attach,
  466. &dvico_fusionhdtv_dual,
  467. &dev->core->i2c_adap);
  468. if (dev->dvb.frontend != NULL) {
  469. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  470. NULL, DVB_PLL_THOMSON_DTT7579);
  471. break;
  472. }
  473. /* ZL10353 replaces MT352 on later cards */
  474. dev->dvb.frontend = dvb_attach(zl10353_attach,
  475. &dvico_fusionhdtv_plus_v1_1,
  476. &dev->core->i2c_adap);
  477. if (dev->dvb.frontend != NULL) {
  478. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  479. NULL, DVB_PLL_THOMSON_DTT7579);
  480. }
  481. break;
  482. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  483. dev->dvb.frontend = dvb_attach(mt352_attach,
  484. &dvico_fusionhdtv,
  485. &dev->core->i2c_adap);
  486. if (dev->dvb.frontend != NULL) {
  487. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  488. NULL, DVB_PLL_LG_Z201);
  489. }
  490. break;
  491. case CX88_BOARD_KWORLD_DVB_T:
  492. case CX88_BOARD_DNTV_LIVE_DVB_T:
  493. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  494. dev->dvb.frontend = dvb_attach(mt352_attach,
  495. &dntv_live_dvbt_config,
  496. &dev->core->i2c_adap);
  497. if (dev->dvb.frontend != NULL) {
  498. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  499. NULL, DVB_PLL_UNKNOWN_1);
  500. }
  501. break;
  502. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  503. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  504. /* MT352 is on a secondary I2C bus made from some GPIO lines */
  505. dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
  506. &dev->vp3054->adap);
  507. if (dev->dvb.frontend != NULL) {
  508. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  509. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  510. }
  511. #else
  512. printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name);
  513. #endif
  514. break;
  515. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  516. dev->dvb.frontend = dvb_attach(zl10353_attach,
  517. &dvico_fusionhdtv_hybrid,
  518. &dev->core->i2c_adap);
  519. if (dev->dvb.frontend != NULL) {
  520. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  521. &dev->core->i2c_adap,
  522. DVB_PLL_THOMSON_FE6600);
  523. }
  524. break;
  525. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
  526. dev->dvb.frontend = dvb_attach(zl10353_attach,
  527. &dvico_fusionhdtv_xc3028,
  528. &dev->core->i2c_adap);
  529. if (dev->dvb.frontend == NULL)
  530. dev->dvb.frontend = dvb_attach(mt352_attach,
  531. &dvico_fusionhdtv_mt352_xc3028,
  532. &dev->core->i2c_adap);
  533. /*
  534. * On this board, the demod provides the I2C bus pullup.
  535. * We must not permit gate_ctrl to be performed, or
  536. * the xc3028 cannot communicate on the bus.
  537. */
  538. if (dev->dvb.frontend)
  539. dev->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  540. if (attach_xc3028(0x61, dev) < 0)
  541. return -EINVAL;
  542. break;
  543. case CX88_BOARD_PCHDTV_HD3000:
  544. dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  545. &dev->core->i2c_adap);
  546. if (dev->dvb.frontend != NULL) {
  547. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  548. &dev->core->i2c_adap,
  549. DVB_PLL_THOMSON_DTT761X);
  550. }
  551. break;
  552. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  553. dev->ts_gen_cntrl = 0x08;
  554. {
  555. /* Do a hardware reset of chip before using it. */
  556. struct cx88_core *core = dev->core;
  557. cx_clear(MO_GP0_IO, 1);
  558. mdelay(100);
  559. cx_set(MO_GP0_IO, 1);
  560. mdelay(200);
  561. /* Select RF connector callback */
  562. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  563. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  564. &fusionhdtv_3_gold,
  565. &dev->core->i2c_adap);
  566. if (dev->dvb.frontend != NULL) {
  567. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  568. &dev->core->i2c_adap,
  569. DVB_PLL_MICROTUNE_4042);
  570. }
  571. }
  572. break;
  573. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  574. dev->ts_gen_cntrl = 0x08;
  575. {
  576. /* Do a hardware reset of chip before using it. */
  577. struct cx88_core *core = dev->core;
  578. cx_clear(MO_GP0_IO, 1);
  579. mdelay(100);
  580. cx_set(MO_GP0_IO, 9);
  581. mdelay(200);
  582. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  583. &fusionhdtv_3_gold,
  584. &dev->core->i2c_adap);
  585. if (dev->dvb.frontend != NULL) {
  586. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  587. &dev->core->i2c_adap,
  588. DVB_PLL_THOMSON_DTT761X);
  589. }
  590. }
  591. break;
  592. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  593. dev->ts_gen_cntrl = 0x08;
  594. {
  595. /* Do a hardware reset of chip before using it. */
  596. struct cx88_core *core = dev->core;
  597. cx_clear(MO_GP0_IO, 1);
  598. mdelay(100);
  599. cx_set(MO_GP0_IO, 1);
  600. mdelay(200);
  601. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  602. &fusionhdtv_5_gold,
  603. &dev->core->i2c_adap);
  604. if (dev->dvb.frontend != NULL) {
  605. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  606. &dev->core->i2c_adap,
  607. DVB_PLL_LG_TDVS_H06XF);
  608. }
  609. }
  610. break;
  611. case CX88_BOARD_PCHDTV_HD5500:
  612. dev->ts_gen_cntrl = 0x08;
  613. {
  614. /* Do a hardware reset of chip before using it. */
  615. struct cx88_core *core = dev->core;
  616. cx_clear(MO_GP0_IO, 1);
  617. mdelay(100);
  618. cx_set(MO_GP0_IO, 1);
  619. mdelay(200);
  620. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  621. &pchdtv_hd5500,
  622. &dev->core->i2c_adap);
  623. if (dev->dvb.frontend != NULL) {
  624. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  625. &dev->core->i2c_adap,
  626. DVB_PLL_LG_TDVS_H06XF);
  627. }
  628. }
  629. break;
  630. case CX88_BOARD_ATI_HDTVWONDER:
  631. dev->dvb.frontend = dvb_attach(nxt200x_attach,
  632. &ati_hdtvwonder,
  633. &dev->core->i2c_adap);
  634. if (dev->dvb.frontend != NULL) {
  635. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  636. NULL, DVB_PLL_TUV1236D);
  637. }
  638. break;
  639. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  640. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  641. dev->dvb.frontend = dvb_attach(cx24123_attach,
  642. &hauppauge_novas_config,
  643. &dev->core->i2c_adap);
  644. if (dev->dvb.frontend) {
  645. dvb_attach(isl6421_attach, dev->dvb.frontend,
  646. &dev->core->i2c_adap, 0x08, 0x00, 0x00);
  647. }
  648. break;
  649. case CX88_BOARD_KWORLD_DVBS_100:
  650. dev->dvb.frontend = dvb_attach(cx24123_attach,
  651. &kworld_dvbs_100_config,
  652. &dev->core->i2c_adap);
  653. if (dev->dvb.frontend) {
  654. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  655. dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  656. }
  657. break;
  658. case CX88_BOARD_GENIATECH_DVBS:
  659. dev->dvb.frontend = dvb_attach(cx24123_attach,
  660. &geniatech_dvbs_config,
  661. &dev->core->i2c_adap);
  662. if (dev->dvb.frontend) {
  663. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  664. dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  665. }
  666. break;
  667. case CX88_BOARD_PINNACLE_PCTV_HD_800i:
  668. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  669. &pinnacle_pctv_hd_800i_config,
  670. &dev->core->i2c_adap);
  671. if (dev->dvb.frontend != NULL) {
  672. /* tuner_config.video_dev must point to
  673. * i2c_adap.algo_data
  674. */
  675. pinnacle_pctv_hd_800i_tuner_config.priv =
  676. dev->core->i2c_adap.algo_data;
  677. dvb_attach(xc5000_attach, dev->dvb.frontend,
  678. &dev->core->i2c_adap,
  679. &pinnacle_pctv_hd_800i_tuner_config);
  680. }
  681. break;
  682. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  683. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  684. &dvico_hdtv5_pci_nano_config,
  685. &dev->core->i2c_adap);
  686. if (dev->dvb.frontend != NULL) {
  687. struct dvb_frontend *fe;
  688. struct xc2028_config cfg = {
  689. .i2c_adap = &dev->core->i2c_adap,
  690. .i2c_addr = 0x61,
  691. .video_dev = dev->core,
  692. .callback = cx88_xc3028_callback,
  693. };
  694. static struct xc2028_ctrl ctl = {
  695. .fname = "xc3028-v27.fw",
  696. .max_len = 64,
  697. .scode_table = OREN538,
  698. };
  699. fe = dvb_attach(xc2028_attach,
  700. dev->dvb.frontend, &cfg);
  701. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  702. fe->ops.tuner_ops.set_config(fe, &ctl);
  703. }
  704. break;
  705. case CX88_BOARD_PINNACLE_HYBRID_PCTV:
  706. dev->dvb.frontend = dvb_attach(zl10353_attach,
  707. &cx88_geniatech_x8000_mt,
  708. &dev->core->i2c_adap);
  709. if (attach_xc3028(0x61, dev) < 0)
  710. return -EINVAL;
  711. break;
  712. case CX88_BOARD_GENIATECH_X8000_MT:
  713. dev->ts_gen_cntrl = 0x00;
  714. dev->dvb.frontend = dvb_attach(zl10353_attach,
  715. &cx88_geniatech_x8000_mt,
  716. &dev->core->i2c_adap);
  717. if (attach_xc3028(0x61, dev) < 0)
  718. return -EINVAL;
  719. break;
  720. default:
  721. printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
  722. dev->core->name);
  723. break;
  724. }
  725. if (NULL == dev->dvb.frontend) {
  726. printk(KERN_ERR
  727. "%s/2: frontend initialization failed\n",
  728. dev->core->name);
  729. return -EINVAL;
  730. }
  731. /* Ensure all frontends negotiate bus access */
  732. dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  733. /* Put the analog decoder in standby to keep it quiet */
  734. cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
  735. /* register everything */
  736. return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
  737. }
  738. /* ----------------------------------------------------------- */
  739. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  740. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  741. {
  742. struct cx88_core *core = drv->core;
  743. int err = 0;
  744. dprintk( 1, "%s\n", __FUNCTION__);
  745. switch (core->boardnr) {
  746. case CX88_BOARD_HAUPPAUGE_HVR1300:
  747. /* We arrive here with either the cx23416 or the cx22702
  748. * on the bus. Take the bus from the cx23416 and enable the
  749. * cx22702 demod
  750. */
  751. cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
  752. cx_clear(MO_GP0_IO, 0x00000004);
  753. udelay(1000);
  754. break;
  755. default:
  756. err = -ENODEV;
  757. }
  758. return err;
  759. }
  760. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  761. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  762. {
  763. struct cx88_core *core = drv->core;
  764. int err = 0;
  765. dprintk( 1, "%s\n", __FUNCTION__);
  766. switch (core->boardnr) {
  767. case CX88_BOARD_HAUPPAUGE_HVR1300:
  768. /* Do Nothing, leave the cx22702 on the bus. */
  769. break;
  770. default:
  771. err = -ENODEV;
  772. }
  773. return err;
  774. }
  775. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  776. {
  777. struct cx88_core *core = drv->core;
  778. struct cx8802_dev *dev = drv->core->dvbdev;
  779. int err;
  780. dprintk( 1, "%s\n", __FUNCTION__);
  781. dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  782. core->boardnr,
  783. core->name,
  784. core->pci_bus,
  785. core->pci_slot);
  786. err = -ENODEV;
  787. if (!(core->board.mpeg & CX88_MPEG_DVB))
  788. goto fail_core;
  789. /* If vp3054 isn't enabled, a stub will just return 0 */
  790. err = vp3054_i2c_probe(dev);
  791. if (0 != err)
  792. goto fail_core;
  793. /* dvb stuff */
  794. printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
  795. videobuf_queue_sg_init(&dev->dvb.dvbq, &dvb_qops,
  796. &dev->pci->dev, &dev->slock,
  797. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  798. V4L2_FIELD_TOP,
  799. sizeof(struct cx88_buffer),
  800. dev);
  801. err = dvb_register(dev);
  802. if (err != 0)
  803. printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
  804. core->name, err);
  805. fail_core:
  806. return err;
  807. }
  808. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  809. {
  810. struct cx8802_dev *dev = drv->core->dvbdev;
  811. /* dvb */
  812. videobuf_dvb_unregister(&dev->dvb);
  813. vp3054_i2c_remove(dev);
  814. return 0;
  815. }
  816. static struct cx8802_driver cx8802_dvb_driver = {
  817. .type_id = CX88_MPEG_DVB,
  818. .hw_access = CX8802_DRVCTL_SHARED,
  819. .probe = cx8802_dvb_probe,
  820. .remove = cx8802_dvb_remove,
  821. .advise_acquire = cx8802_dvb_advise_acquire,
  822. .advise_release = cx8802_dvb_advise_release,
  823. };
  824. static int dvb_init(void)
  825. {
  826. printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n",
  827. (CX88_VERSION_CODE >> 16) & 0xff,
  828. (CX88_VERSION_CODE >> 8) & 0xff,
  829. CX88_VERSION_CODE & 0xff);
  830. #ifdef SNAPSHOT
  831. printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
  832. SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
  833. #endif
  834. return cx8802_register_driver(&cx8802_dvb_driver);
  835. }
  836. static void dvb_fini(void)
  837. {
  838. cx8802_unregister_driver(&cx8802_dvb_driver);
  839. }
  840. module_init(dvb_init);
  841. module_exit(dvb_fini);
  842. /*
  843. * Local variables:
  844. * c-basic-offset: 8
  845. * compile-command: "make DVB=1"
  846. * End:
  847. */