vmxnet3_drv.c 85 KB

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  1. /*
  2. * Linux driver for VMware's vmxnet3 ethernet NIC.
  3. *
  4. * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; version 2 of the License and no later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13. * NON INFRINGEMENT. See the GNU General Public License for more
  14. * details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * The full GNU General Public License is included in this distribution in
  21. * the file called "COPYING".
  22. *
  23. * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
  24. *
  25. */
  26. #include <net/ip6_checksum.h>
  27. #include "vmxnet3_int.h"
  28. char vmxnet3_driver_name[] = "vmxnet3";
  29. #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
  30. /*
  31. * PCI Device ID Table
  32. * Last entry must be all 0s
  33. */
  34. static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
  35. {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
  36. {0}
  37. };
  38. MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
  39. static atomic_t devices_found;
  40. #define VMXNET3_MAX_DEVICES 10
  41. static int enable_mq = 1;
  42. static int irq_share_mode;
  43. /*
  44. * Enable/Disable the given intr
  45. */
  46. static void
  47. vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  48. {
  49. VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
  50. }
  51. static void
  52. vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  53. {
  54. VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
  55. }
  56. /*
  57. * Enable/Disable all intrs used by the device
  58. */
  59. static void
  60. vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
  61. {
  62. int i;
  63. for (i = 0; i < adapter->intr.num_intrs; i++)
  64. vmxnet3_enable_intr(adapter, i);
  65. adapter->shared->devRead.intrConf.intrCtrl &=
  66. cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
  67. }
  68. static void
  69. vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
  70. {
  71. int i;
  72. adapter->shared->devRead.intrConf.intrCtrl |=
  73. cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  74. for (i = 0; i < adapter->intr.num_intrs; i++)
  75. vmxnet3_disable_intr(adapter, i);
  76. }
  77. static void
  78. vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
  79. {
  80. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
  81. }
  82. static bool
  83. vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  84. {
  85. return tq->stopped;
  86. }
  87. static void
  88. vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  89. {
  90. tq->stopped = false;
  91. netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
  92. }
  93. static void
  94. vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  95. {
  96. tq->stopped = false;
  97. netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
  98. }
  99. static void
  100. vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  101. {
  102. tq->stopped = true;
  103. tq->num_stop++;
  104. netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
  105. }
  106. /*
  107. * Check the link state. This may start or stop the tx queue.
  108. */
  109. static void
  110. vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
  111. {
  112. u32 ret;
  113. int i;
  114. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
  115. ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  116. adapter->link_speed = ret >> 16;
  117. if (ret & 1) { /* Link is up. */
  118. printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
  119. adapter->netdev->name, adapter->link_speed);
  120. if (!netif_carrier_ok(adapter->netdev))
  121. netif_carrier_on(adapter->netdev);
  122. if (affectTxQueue) {
  123. for (i = 0; i < adapter->num_tx_queues; i++)
  124. vmxnet3_tq_start(&adapter->tx_queue[i],
  125. adapter);
  126. }
  127. } else {
  128. printk(KERN_INFO "%s: NIC Link is Down\n",
  129. adapter->netdev->name);
  130. if (netif_carrier_ok(adapter->netdev))
  131. netif_carrier_off(adapter->netdev);
  132. if (affectTxQueue) {
  133. for (i = 0; i < adapter->num_tx_queues; i++)
  134. vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
  135. }
  136. }
  137. }
  138. static void
  139. vmxnet3_process_events(struct vmxnet3_adapter *adapter)
  140. {
  141. int i;
  142. u32 events = le32_to_cpu(adapter->shared->ecr);
  143. if (!events)
  144. return;
  145. vmxnet3_ack_events(adapter, events);
  146. /* Check if link state has changed */
  147. if (events & VMXNET3_ECR_LINK)
  148. vmxnet3_check_link(adapter, true);
  149. /* Check if there is an error on xmit/recv queues */
  150. if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
  151. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  152. VMXNET3_CMD_GET_QUEUE_STATUS);
  153. for (i = 0; i < adapter->num_tx_queues; i++)
  154. if (adapter->tqd_start[i].status.stopped)
  155. dev_err(&adapter->netdev->dev,
  156. "%s: tq[%d] error 0x%x\n",
  157. adapter->netdev->name, i, le32_to_cpu(
  158. adapter->tqd_start[i].status.error));
  159. for (i = 0; i < adapter->num_rx_queues; i++)
  160. if (adapter->rqd_start[i].status.stopped)
  161. dev_err(&adapter->netdev->dev,
  162. "%s: rq[%d] error 0x%x\n",
  163. adapter->netdev->name, i,
  164. adapter->rqd_start[i].status.error);
  165. schedule_work(&adapter->work);
  166. }
  167. }
  168. #ifdef __BIG_ENDIAN_BITFIELD
  169. /*
  170. * The device expects the bitfields in shared structures to be written in
  171. * little endian. When CPU is big endian, the following routines are used to
  172. * correctly read and write into ABI.
  173. * The general technique used here is : double word bitfields are defined in
  174. * opposite order for big endian architecture. Then before reading them in
  175. * driver the complete double word is translated using le32_to_cpu. Similarly
  176. * After the driver writes into bitfields, cpu_to_le32 is used to translate the
  177. * double words into required format.
  178. * In order to avoid touching bits in shared structure more than once, temporary
  179. * descriptors are used. These are passed as srcDesc to following functions.
  180. */
  181. static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
  182. struct Vmxnet3_RxDesc *dstDesc)
  183. {
  184. u32 *src = (u32 *)srcDesc + 2;
  185. u32 *dst = (u32 *)dstDesc + 2;
  186. dstDesc->addr = le64_to_cpu(srcDesc->addr);
  187. *dst = le32_to_cpu(*src);
  188. dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
  189. }
  190. static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
  191. struct Vmxnet3_TxDesc *dstDesc)
  192. {
  193. int i;
  194. u32 *src = (u32 *)(srcDesc + 1);
  195. u32 *dst = (u32 *)(dstDesc + 1);
  196. /* Working backwards so that the gen bit is set at the end. */
  197. for (i = 2; i > 0; i--) {
  198. src--;
  199. dst--;
  200. *dst = cpu_to_le32(*src);
  201. }
  202. }
  203. static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
  204. struct Vmxnet3_RxCompDesc *dstDesc)
  205. {
  206. int i = 0;
  207. u32 *src = (u32 *)srcDesc;
  208. u32 *dst = (u32 *)dstDesc;
  209. for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
  210. *dst = le32_to_cpu(*src);
  211. src++;
  212. dst++;
  213. }
  214. }
  215. /* Used to read bitfield values from double words. */
  216. static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
  217. {
  218. u32 temp = le32_to_cpu(*bitfield);
  219. u32 mask = ((1 << size) - 1) << pos;
  220. temp &= mask;
  221. temp >>= pos;
  222. return temp;
  223. }
  224. #endif /* __BIG_ENDIAN_BITFIELD */
  225. #ifdef __BIG_ENDIAN_BITFIELD
  226. # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
  227. txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
  228. VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
  229. # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
  230. txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
  231. VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
  232. # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
  233. VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
  234. VMXNET3_TCD_GEN_SIZE)
  235. # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
  236. VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
  237. # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
  238. (dstrcd) = (tmp); \
  239. vmxnet3_RxCompToCPU((rcd), (tmp)); \
  240. } while (0)
  241. # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
  242. (dstrxd) = (tmp); \
  243. vmxnet3_RxDescToCPU((rxd), (tmp)); \
  244. } while (0)
  245. #else
  246. # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
  247. # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
  248. # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
  249. # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
  250. # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
  251. # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
  252. #endif /* __BIG_ENDIAN_BITFIELD */
  253. static void
  254. vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
  255. struct pci_dev *pdev)
  256. {
  257. if (tbi->map_type == VMXNET3_MAP_SINGLE)
  258. pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
  259. PCI_DMA_TODEVICE);
  260. else if (tbi->map_type == VMXNET3_MAP_PAGE)
  261. pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
  262. PCI_DMA_TODEVICE);
  263. else
  264. BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
  265. tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
  266. }
  267. static int
  268. vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
  269. struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
  270. {
  271. struct sk_buff *skb;
  272. int entries = 0;
  273. /* no out of order completion */
  274. BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
  275. BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
  276. skb = tq->buf_info[eop_idx].skb;
  277. BUG_ON(skb == NULL);
  278. tq->buf_info[eop_idx].skb = NULL;
  279. VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
  280. while (tq->tx_ring.next2comp != eop_idx) {
  281. vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
  282. pdev);
  283. /* update next2comp w/o tx_lock. Since we are marking more,
  284. * instead of less, tx ring entries avail, the worst case is
  285. * that the tx routine incorrectly re-queues a pkt due to
  286. * insufficient tx ring entries.
  287. */
  288. vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
  289. entries++;
  290. }
  291. dev_kfree_skb_any(skb);
  292. return entries;
  293. }
  294. static int
  295. vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
  296. struct vmxnet3_adapter *adapter)
  297. {
  298. int completed = 0;
  299. union Vmxnet3_GenericDesc *gdesc;
  300. gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
  301. while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
  302. completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
  303. &gdesc->tcd), tq, adapter->pdev,
  304. adapter);
  305. vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
  306. gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
  307. }
  308. if (completed) {
  309. spin_lock(&tq->tx_lock);
  310. if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
  311. vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
  312. VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
  313. netif_carrier_ok(adapter->netdev))) {
  314. vmxnet3_tq_wake(tq, adapter);
  315. }
  316. spin_unlock(&tq->tx_lock);
  317. }
  318. return completed;
  319. }
  320. static void
  321. vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
  322. struct vmxnet3_adapter *adapter)
  323. {
  324. int i;
  325. while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
  326. struct vmxnet3_tx_buf_info *tbi;
  327. union Vmxnet3_GenericDesc *gdesc;
  328. tbi = tq->buf_info + tq->tx_ring.next2comp;
  329. gdesc = tq->tx_ring.base + tq->tx_ring.next2comp;
  330. vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
  331. if (tbi->skb) {
  332. dev_kfree_skb_any(tbi->skb);
  333. tbi->skb = NULL;
  334. }
  335. vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
  336. }
  337. /* sanity check, verify all buffers are indeed unmapped and freed */
  338. for (i = 0; i < tq->tx_ring.size; i++) {
  339. BUG_ON(tq->buf_info[i].skb != NULL ||
  340. tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
  341. }
  342. tq->tx_ring.gen = VMXNET3_INIT_GEN;
  343. tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
  344. tq->comp_ring.gen = VMXNET3_INIT_GEN;
  345. tq->comp_ring.next2proc = 0;
  346. }
  347. static void
  348. vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
  349. struct vmxnet3_adapter *adapter)
  350. {
  351. if (tq->tx_ring.base) {
  352. pci_free_consistent(adapter->pdev, tq->tx_ring.size *
  353. sizeof(struct Vmxnet3_TxDesc),
  354. tq->tx_ring.base, tq->tx_ring.basePA);
  355. tq->tx_ring.base = NULL;
  356. }
  357. if (tq->data_ring.base) {
  358. pci_free_consistent(adapter->pdev, tq->data_ring.size *
  359. sizeof(struct Vmxnet3_TxDataDesc),
  360. tq->data_ring.base, tq->data_ring.basePA);
  361. tq->data_ring.base = NULL;
  362. }
  363. if (tq->comp_ring.base) {
  364. pci_free_consistent(adapter->pdev, tq->comp_ring.size *
  365. sizeof(struct Vmxnet3_TxCompDesc),
  366. tq->comp_ring.base, tq->comp_ring.basePA);
  367. tq->comp_ring.base = NULL;
  368. }
  369. kfree(tq->buf_info);
  370. tq->buf_info = NULL;
  371. }
  372. /* Destroy all tx queues */
  373. void
  374. vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
  375. {
  376. int i;
  377. for (i = 0; i < adapter->num_tx_queues; i++)
  378. vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
  379. }
  380. static void
  381. vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
  382. struct vmxnet3_adapter *adapter)
  383. {
  384. int i;
  385. /* reset the tx ring contents to 0 and reset the tx ring states */
  386. memset(tq->tx_ring.base, 0, tq->tx_ring.size *
  387. sizeof(struct Vmxnet3_TxDesc));
  388. tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
  389. tq->tx_ring.gen = VMXNET3_INIT_GEN;
  390. memset(tq->data_ring.base, 0, tq->data_ring.size *
  391. sizeof(struct Vmxnet3_TxDataDesc));
  392. /* reset the tx comp ring contents to 0 and reset comp ring states */
  393. memset(tq->comp_ring.base, 0, tq->comp_ring.size *
  394. sizeof(struct Vmxnet3_TxCompDesc));
  395. tq->comp_ring.next2proc = 0;
  396. tq->comp_ring.gen = VMXNET3_INIT_GEN;
  397. /* reset the bookkeeping data */
  398. memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
  399. for (i = 0; i < tq->tx_ring.size; i++)
  400. tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
  401. /* stats are not reset */
  402. }
  403. static int
  404. vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
  405. struct vmxnet3_adapter *adapter)
  406. {
  407. BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
  408. tq->comp_ring.base || tq->buf_info);
  409. tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
  410. * sizeof(struct Vmxnet3_TxDesc),
  411. &tq->tx_ring.basePA);
  412. if (!tq->tx_ring.base) {
  413. printk(KERN_ERR "%s: failed to allocate tx ring\n",
  414. adapter->netdev->name);
  415. goto err;
  416. }
  417. tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
  418. tq->data_ring.size *
  419. sizeof(struct Vmxnet3_TxDataDesc),
  420. &tq->data_ring.basePA);
  421. if (!tq->data_ring.base) {
  422. printk(KERN_ERR "%s: failed to allocate data ring\n",
  423. adapter->netdev->name);
  424. goto err;
  425. }
  426. tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
  427. tq->comp_ring.size *
  428. sizeof(struct Vmxnet3_TxCompDesc),
  429. &tq->comp_ring.basePA);
  430. if (!tq->comp_ring.base) {
  431. printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
  432. adapter->netdev->name);
  433. goto err;
  434. }
  435. tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
  436. GFP_KERNEL);
  437. if (!tq->buf_info) {
  438. printk(KERN_ERR "%s: failed to allocate tx bufinfo\n",
  439. adapter->netdev->name);
  440. goto err;
  441. }
  442. return 0;
  443. err:
  444. vmxnet3_tq_destroy(tq, adapter);
  445. return -ENOMEM;
  446. }
  447. static void
  448. vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
  449. {
  450. int i;
  451. for (i = 0; i < adapter->num_tx_queues; i++)
  452. vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
  453. }
  454. /*
  455. * starting from ring->next2fill, allocate rx buffers for the given ring
  456. * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
  457. * are allocated or allocation fails
  458. */
  459. static int
  460. vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
  461. int num_to_alloc, struct vmxnet3_adapter *adapter)
  462. {
  463. int num_allocated = 0;
  464. struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
  465. struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
  466. u32 val;
  467. while (num_allocated < num_to_alloc) {
  468. struct vmxnet3_rx_buf_info *rbi;
  469. union Vmxnet3_GenericDesc *gd;
  470. rbi = rbi_base + ring->next2fill;
  471. gd = ring->base + ring->next2fill;
  472. if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
  473. if (rbi->skb == NULL) {
  474. rbi->skb = dev_alloc_skb(rbi->len +
  475. NET_IP_ALIGN);
  476. if (unlikely(rbi->skb == NULL)) {
  477. rq->stats.rx_buf_alloc_failure++;
  478. break;
  479. }
  480. rbi->skb->dev = adapter->netdev;
  481. skb_reserve(rbi->skb, NET_IP_ALIGN);
  482. rbi->dma_addr = pci_map_single(adapter->pdev,
  483. rbi->skb->data, rbi->len,
  484. PCI_DMA_FROMDEVICE);
  485. } else {
  486. /* rx buffer skipped by the device */
  487. }
  488. val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
  489. } else {
  490. BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
  491. rbi->len != PAGE_SIZE);
  492. if (rbi->page == NULL) {
  493. rbi->page = alloc_page(GFP_ATOMIC);
  494. if (unlikely(rbi->page == NULL)) {
  495. rq->stats.rx_buf_alloc_failure++;
  496. break;
  497. }
  498. rbi->dma_addr = pci_map_page(adapter->pdev,
  499. rbi->page, 0, PAGE_SIZE,
  500. PCI_DMA_FROMDEVICE);
  501. } else {
  502. /* rx buffers skipped by the device */
  503. }
  504. val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
  505. }
  506. BUG_ON(rbi->dma_addr == 0);
  507. gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
  508. gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT)
  509. | val | rbi->len);
  510. num_allocated++;
  511. vmxnet3_cmd_ring_adv_next2fill(ring);
  512. }
  513. rq->uncommitted[ring_idx] += num_allocated;
  514. dev_dbg(&adapter->netdev->dev,
  515. "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
  516. "%u, uncommited %u\n", num_allocated, ring->next2fill,
  517. ring->next2comp, rq->uncommitted[ring_idx]);
  518. /* so that the device can distinguish a full ring and an empty ring */
  519. BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
  520. return num_allocated;
  521. }
  522. static void
  523. vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
  524. struct vmxnet3_rx_buf_info *rbi)
  525. {
  526. struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
  527. skb_shinfo(skb)->nr_frags;
  528. BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
  529. frag->page = rbi->page;
  530. frag->page_offset = 0;
  531. frag->size = rcd->len;
  532. skb->data_len += frag->size;
  533. skb_shinfo(skb)->nr_frags++;
  534. }
  535. static void
  536. vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
  537. struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
  538. struct vmxnet3_adapter *adapter)
  539. {
  540. u32 dw2, len;
  541. unsigned long buf_offset;
  542. int i;
  543. union Vmxnet3_GenericDesc *gdesc;
  544. struct vmxnet3_tx_buf_info *tbi = NULL;
  545. BUG_ON(ctx->copy_size > skb_headlen(skb));
  546. /* use the previous gen bit for the SOP desc */
  547. dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
  548. ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
  549. gdesc = ctx->sop_txd; /* both loops below can be skipped */
  550. /* no need to map the buffer if headers are copied */
  551. if (ctx->copy_size) {
  552. ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
  553. tq->tx_ring.next2fill *
  554. sizeof(struct Vmxnet3_TxDataDesc));
  555. ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
  556. ctx->sop_txd->dword[3] = 0;
  557. tbi = tq->buf_info + tq->tx_ring.next2fill;
  558. tbi->map_type = VMXNET3_MAP_NONE;
  559. dev_dbg(&adapter->netdev->dev,
  560. "txd[%u]: 0x%Lx 0x%x 0x%x\n",
  561. tq->tx_ring.next2fill,
  562. le64_to_cpu(ctx->sop_txd->txd.addr),
  563. ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
  564. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  565. /* use the right gen for non-SOP desc */
  566. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  567. }
  568. /* linear part can use multiple tx desc if it's big */
  569. len = skb_headlen(skb) - ctx->copy_size;
  570. buf_offset = ctx->copy_size;
  571. while (len) {
  572. u32 buf_size;
  573. if (len < VMXNET3_MAX_TX_BUF_SIZE) {
  574. buf_size = len;
  575. dw2 |= len;
  576. } else {
  577. buf_size = VMXNET3_MAX_TX_BUF_SIZE;
  578. /* spec says that for TxDesc.len, 0 == 2^14 */
  579. }
  580. tbi = tq->buf_info + tq->tx_ring.next2fill;
  581. tbi->map_type = VMXNET3_MAP_SINGLE;
  582. tbi->dma_addr = pci_map_single(adapter->pdev,
  583. skb->data + buf_offset, buf_size,
  584. PCI_DMA_TODEVICE);
  585. tbi->len = buf_size;
  586. gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
  587. BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
  588. gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
  589. gdesc->dword[2] = cpu_to_le32(dw2);
  590. gdesc->dword[3] = 0;
  591. dev_dbg(&adapter->netdev->dev,
  592. "txd[%u]: 0x%Lx 0x%x 0x%x\n",
  593. tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
  594. le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
  595. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  596. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  597. len -= buf_size;
  598. buf_offset += buf_size;
  599. }
  600. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  601. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
  602. tbi = tq->buf_info + tq->tx_ring.next2fill;
  603. tbi->map_type = VMXNET3_MAP_PAGE;
  604. tbi->dma_addr = pci_map_page(adapter->pdev, frag->page,
  605. frag->page_offset, frag->size,
  606. PCI_DMA_TODEVICE);
  607. tbi->len = frag->size;
  608. gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
  609. BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
  610. gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
  611. gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
  612. gdesc->dword[3] = 0;
  613. dev_dbg(&adapter->netdev->dev,
  614. "txd[%u]: 0x%llu %u %u\n",
  615. tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
  616. le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
  617. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  618. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  619. }
  620. ctx->eop_txd = gdesc;
  621. /* set the last buf_info for the pkt */
  622. tbi->skb = skb;
  623. tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
  624. }
  625. /* Init all tx queues */
  626. static void
  627. vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
  628. {
  629. int i;
  630. for (i = 0; i < adapter->num_tx_queues; i++)
  631. vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
  632. }
  633. /*
  634. * parse and copy relevant protocol headers:
  635. * For a tso pkt, relevant headers are L2/3/4 including options
  636. * For a pkt requesting csum offloading, they are L2/3 and may include L4
  637. * if it's a TCP/UDP pkt
  638. *
  639. * Returns:
  640. * -1: error happens during parsing
  641. * 0: protocol headers parsed, but too big to be copied
  642. * 1: protocol headers parsed and copied
  643. *
  644. * Other effects:
  645. * 1. related *ctx fields are updated.
  646. * 2. ctx->copy_size is # of bytes copied
  647. * 3. the portion copied is guaranteed to be in the linear part
  648. *
  649. */
  650. static int
  651. vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
  652. struct vmxnet3_tx_ctx *ctx,
  653. struct vmxnet3_adapter *adapter)
  654. {
  655. struct Vmxnet3_TxDataDesc *tdd;
  656. if (ctx->mss) {
  657. ctx->eth_ip_hdr_size = skb_transport_offset(skb);
  658. ctx->l4_hdr_size = ((struct tcphdr *)
  659. skb_transport_header(skb))->doff * 4;
  660. ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
  661. } else {
  662. unsigned int pull_size;
  663. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  664. ctx->eth_ip_hdr_size = skb_transport_offset(skb);
  665. if (ctx->ipv4) {
  666. struct iphdr *iph = (struct iphdr *)
  667. skb_network_header(skb);
  668. if (iph->protocol == IPPROTO_TCP) {
  669. pull_size = ctx->eth_ip_hdr_size +
  670. sizeof(struct tcphdr);
  671. if (unlikely(!pskb_may_pull(skb,
  672. pull_size))) {
  673. goto err;
  674. }
  675. ctx->l4_hdr_size = ((struct tcphdr *)
  676. skb_transport_header(skb))->doff * 4;
  677. } else if (iph->protocol == IPPROTO_UDP) {
  678. ctx->l4_hdr_size =
  679. sizeof(struct udphdr);
  680. } else {
  681. ctx->l4_hdr_size = 0;
  682. }
  683. } else {
  684. /* for simplicity, don't copy L4 headers */
  685. ctx->l4_hdr_size = 0;
  686. }
  687. ctx->copy_size = ctx->eth_ip_hdr_size +
  688. ctx->l4_hdr_size;
  689. } else {
  690. ctx->eth_ip_hdr_size = 0;
  691. ctx->l4_hdr_size = 0;
  692. /* copy as much as allowed */
  693. ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
  694. , skb_headlen(skb));
  695. }
  696. /* make sure headers are accessible directly */
  697. if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
  698. goto err;
  699. }
  700. if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
  701. tq->stats.oversized_hdr++;
  702. ctx->copy_size = 0;
  703. return 0;
  704. }
  705. tdd = tq->data_ring.base + tq->tx_ring.next2fill;
  706. memcpy(tdd->data, skb->data, ctx->copy_size);
  707. dev_dbg(&adapter->netdev->dev,
  708. "copy %u bytes to dataRing[%u]\n",
  709. ctx->copy_size, tq->tx_ring.next2fill);
  710. return 1;
  711. err:
  712. return -1;
  713. }
  714. static void
  715. vmxnet3_prepare_tso(struct sk_buff *skb,
  716. struct vmxnet3_tx_ctx *ctx)
  717. {
  718. struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb);
  719. if (ctx->ipv4) {
  720. struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
  721. iph->check = 0;
  722. tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
  723. IPPROTO_TCP, 0);
  724. } else {
  725. struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb);
  726. tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
  727. IPPROTO_TCP, 0);
  728. }
  729. }
  730. /*
  731. * Transmits a pkt thru a given tq
  732. * Returns:
  733. * NETDEV_TX_OK: descriptors are setup successfully
  734. * NETDEV_TX_OK: error occured, the pkt is dropped
  735. * NETDEV_TX_BUSY: tx ring is full, queue is stopped
  736. *
  737. * Side-effects:
  738. * 1. tx ring may be changed
  739. * 2. tq stats may be updated accordingly
  740. * 3. shared->txNumDeferred may be updated
  741. */
  742. static int
  743. vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
  744. struct vmxnet3_adapter *adapter, struct net_device *netdev)
  745. {
  746. int ret;
  747. u32 count;
  748. unsigned long flags;
  749. struct vmxnet3_tx_ctx ctx;
  750. union Vmxnet3_GenericDesc *gdesc;
  751. #ifdef __BIG_ENDIAN_BITFIELD
  752. /* Use temporary descriptor to avoid touching bits multiple times */
  753. union Vmxnet3_GenericDesc tempTxDesc;
  754. #endif
  755. /* conservatively estimate # of descriptors to use */
  756. count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
  757. skb_shinfo(skb)->nr_frags + 1;
  758. ctx.ipv4 = (skb->protocol == cpu_to_be16(ETH_P_IP));
  759. ctx.mss = skb_shinfo(skb)->gso_size;
  760. if (ctx.mss) {
  761. if (skb_header_cloned(skb)) {
  762. if (unlikely(pskb_expand_head(skb, 0, 0,
  763. GFP_ATOMIC) != 0)) {
  764. tq->stats.drop_tso++;
  765. goto drop_pkt;
  766. }
  767. tq->stats.copy_skb_header++;
  768. }
  769. vmxnet3_prepare_tso(skb, &ctx);
  770. } else {
  771. if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
  772. /* non-tso pkts must not use more than
  773. * VMXNET3_MAX_TXD_PER_PKT entries
  774. */
  775. if (skb_linearize(skb) != 0) {
  776. tq->stats.drop_too_many_frags++;
  777. goto drop_pkt;
  778. }
  779. tq->stats.linearized++;
  780. /* recalculate the # of descriptors to use */
  781. count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
  782. }
  783. }
  784. spin_lock_irqsave(&tq->tx_lock, flags);
  785. if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
  786. tq->stats.tx_ring_full++;
  787. dev_dbg(&adapter->netdev->dev,
  788. "tx queue stopped on %s, next2comp %u"
  789. " next2fill %u\n", adapter->netdev->name,
  790. tq->tx_ring.next2comp, tq->tx_ring.next2fill);
  791. vmxnet3_tq_stop(tq, adapter);
  792. spin_unlock_irqrestore(&tq->tx_lock, flags);
  793. return NETDEV_TX_BUSY;
  794. }
  795. ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
  796. if (ret >= 0) {
  797. BUG_ON(ret <= 0 && ctx.copy_size != 0);
  798. /* hdrs parsed, check against other limits */
  799. if (ctx.mss) {
  800. if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
  801. VMXNET3_MAX_TX_BUF_SIZE)) {
  802. goto hdr_too_big;
  803. }
  804. } else {
  805. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  806. if (unlikely(ctx.eth_ip_hdr_size +
  807. skb->csum_offset >
  808. VMXNET3_MAX_CSUM_OFFSET)) {
  809. goto hdr_too_big;
  810. }
  811. }
  812. }
  813. } else {
  814. tq->stats.drop_hdr_inspect_err++;
  815. goto drop_pkt;
  816. }
  817. /* fill tx descs related to addr & len */
  818. vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
  819. /* setup the EOP desc */
  820. ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
  821. /* setup the SOP desc */
  822. #ifdef __BIG_ENDIAN_BITFIELD
  823. gdesc = &tempTxDesc;
  824. gdesc->dword[2] = ctx.sop_txd->dword[2];
  825. gdesc->dword[3] = ctx.sop_txd->dword[3];
  826. #else
  827. gdesc = ctx.sop_txd;
  828. #endif
  829. if (ctx.mss) {
  830. gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
  831. gdesc->txd.om = VMXNET3_OM_TSO;
  832. gdesc->txd.msscof = ctx.mss;
  833. le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
  834. gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
  835. } else {
  836. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  837. gdesc->txd.hlen = ctx.eth_ip_hdr_size;
  838. gdesc->txd.om = VMXNET3_OM_CSUM;
  839. gdesc->txd.msscof = ctx.eth_ip_hdr_size +
  840. skb->csum_offset;
  841. } else {
  842. gdesc->txd.om = 0;
  843. gdesc->txd.msscof = 0;
  844. }
  845. le32_add_cpu(&tq->shared->txNumDeferred, 1);
  846. }
  847. if (vlan_tx_tag_present(skb)) {
  848. gdesc->txd.ti = 1;
  849. gdesc->txd.tci = vlan_tx_tag_get(skb);
  850. }
  851. /* finally flips the GEN bit of the SOP desc. */
  852. gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
  853. VMXNET3_TXD_GEN);
  854. #ifdef __BIG_ENDIAN_BITFIELD
  855. /* Finished updating in bitfields of Tx Desc, so write them in original
  856. * place.
  857. */
  858. vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
  859. (struct Vmxnet3_TxDesc *)ctx.sop_txd);
  860. gdesc = ctx.sop_txd;
  861. #endif
  862. dev_dbg(&adapter->netdev->dev,
  863. "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
  864. (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
  865. tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
  866. le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
  867. spin_unlock_irqrestore(&tq->tx_lock, flags);
  868. if (le32_to_cpu(tq->shared->txNumDeferred) >=
  869. le32_to_cpu(tq->shared->txThreshold)) {
  870. tq->shared->txNumDeferred = 0;
  871. VMXNET3_WRITE_BAR0_REG(adapter,
  872. VMXNET3_REG_TXPROD + tq->qid * 8,
  873. tq->tx_ring.next2fill);
  874. }
  875. return NETDEV_TX_OK;
  876. hdr_too_big:
  877. tq->stats.drop_oversized_hdr++;
  878. drop_pkt:
  879. tq->stats.drop_total++;
  880. dev_kfree_skb(skb);
  881. return NETDEV_TX_OK;
  882. }
  883. static netdev_tx_t
  884. vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  885. {
  886. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  887. BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
  888. return vmxnet3_tq_xmit(skb,
  889. &adapter->tx_queue[skb->queue_mapping],
  890. adapter, netdev);
  891. }
  892. static void
  893. vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
  894. struct sk_buff *skb,
  895. union Vmxnet3_GenericDesc *gdesc)
  896. {
  897. if (!gdesc->rcd.cnc && adapter->rxcsum) {
  898. /* typical case: TCP/UDP over IP and both csums are correct */
  899. if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
  900. VMXNET3_RCD_CSUM_OK) {
  901. skb->ip_summed = CHECKSUM_UNNECESSARY;
  902. BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
  903. BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
  904. BUG_ON(gdesc->rcd.frg);
  905. } else {
  906. if (gdesc->rcd.csum) {
  907. skb->csum = htons(gdesc->rcd.csum);
  908. skb->ip_summed = CHECKSUM_PARTIAL;
  909. } else {
  910. skb_checksum_none_assert(skb);
  911. }
  912. }
  913. } else {
  914. skb_checksum_none_assert(skb);
  915. }
  916. }
  917. static void
  918. vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
  919. struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
  920. {
  921. rq->stats.drop_err++;
  922. if (!rcd->fcs)
  923. rq->stats.drop_fcs++;
  924. rq->stats.drop_total++;
  925. /*
  926. * We do not unmap and chain the rx buffer to the skb.
  927. * We basically pretend this buffer is not used and will be recycled
  928. * by vmxnet3_rq_alloc_rx_buf()
  929. */
  930. /*
  931. * ctx->skb may be NULL if this is the first and the only one
  932. * desc for the pkt
  933. */
  934. if (ctx->skb)
  935. dev_kfree_skb_irq(ctx->skb);
  936. ctx->skb = NULL;
  937. }
  938. static int
  939. vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
  940. struct vmxnet3_adapter *adapter, int quota)
  941. {
  942. static u32 rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};
  943. u32 num_rxd = 0;
  944. struct Vmxnet3_RxCompDesc *rcd;
  945. struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
  946. #ifdef __BIG_ENDIAN_BITFIELD
  947. struct Vmxnet3_RxDesc rxCmdDesc;
  948. struct Vmxnet3_RxCompDesc rxComp;
  949. #endif
  950. vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
  951. &rxComp);
  952. while (rcd->gen == rq->comp_ring.gen) {
  953. struct vmxnet3_rx_buf_info *rbi;
  954. struct sk_buff *skb;
  955. int num_to_alloc;
  956. struct Vmxnet3_RxDesc *rxd;
  957. u32 idx, ring_idx;
  958. if (num_rxd >= quota) {
  959. /* we may stop even before we see the EOP desc of
  960. * the current pkt
  961. */
  962. break;
  963. }
  964. num_rxd++;
  965. BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
  966. idx = rcd->rxdIdx;
  967. ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
  968. vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
  969. &rxCmdDesc);
  970. rbi = rq->buf_info[ring_idx] + idx;
  971. BUG_ON(rxd->addr != rbi->dma_addr ||
  972. rxd->len != rbi->len);
  973. if (unlikely(rcd->eop && rcd->err)) {
  974. vmxnet3_rx_error(rq, rcd, ctx, adapter);
  975. goto rcd_done;
  976. }
  977. if (rcd->sop) { /* first buf of the pkt */
  978. BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
  979. rcd->rqID != rq->qid);
  980. BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
  981. BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
  982. if (unlikely(rcd->len == 0)) {
  983. /* Pretend the rx buffer is skipped. */
  984. BUG_ON(!(rcd->sop && rcd->eop));
  985. dev_dbg(&adapter->netdev->dev,
  986. "rxRing[%u][%u] 0 length\n",
  987. ring_idx, idx);
  988. goto rcd_done;
  989. }
  990. ctx->skb = rbi->skb;
  991. rbi->skb = NULL;
  992. pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
  993. PCI_DMA_FROMDEVICE);
  994. skb_put(ctx->skb, rcd->len);
  995. } else {
  996. BUG_ON(ctx->skb == NULL);
  997. /* non SOP buffer must be type 1 in most cases */
  998. if (rbi->buf_type == VMXNET3_RX_BUF_PAGE) {
  999. BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
  1000. if (rcd->len) {
  1001. pci_unmap_page(adapter->pdev,
  1002. rbi->dma_addr, rbi->len,
  1003. PCI_DMA_FROMDEVICE);
  1004. vmxnet3_append_frag(ctx->skb, rcd, rbi);
  1005. rbi->page = NULL;
  1006. }
  1007. } else {
  1008. /*
  1009. * The only time a non-SOP buffer is type 0 is
  1010. * when it's EOP and error flag is raised, which
  1011. * has already been handled.
  1012. */
  1013. BUG_ON(true);
  1014. }
  1015. }
  1016. skb = ctx->skb;
  1017. if (rcd->eop) {
  1018. skb->len += skb->data_len;
  1019. skb->truesize += skb->data_len;
  1020. vmxnet3_rx_csum(adapter, skb,
  1021. (union Vmxnet3_GenericDesc *)rcd);
  1022. skb->protocol = eth_type_trans(skb, adapter->netdev);
  1023. if (unlikely(adapter->vlan_grp && rcd->ts)) {
  1024. vlan_hwaccel_receive_skb(skb,
  1025. adapter->vlan_grp, rcd->tci);
  1026. } else {
  1027. netif_receive_skb(skb);
  1028. }
  1029. ctx->skb = NULL;
  1030. }
  1031. rcd_done:
  1032. /* device may skip some rx descs */
  1033. rq->rx_ring[ring_idx].next2comp = idx;
  1034. VMXNET3_INC_RING_IDX_ONLY(rq->rx_ring[ring_idx].next2comp,
  1035. rq->rx_ring[ring_idx].size);
  1036. /* refill rx buffers frequently to avoid starving the h/w */
  1037. num_to_alloc = vmxnet3_cmd_ring_desc_avail(rq->rx_ring +
  1038. ring_idx);
  1039. if (unlikely(num_to_alloc > VMXNET3_RX_ALLOC_THRESHOLD(rq,
  1040. ring_idx, adapter))) {
  1041. vmxnet3_rq_alloc_rx_buf(rq, ring_idx, num_to_alloc,
  1042. adapter);
  1043. /* if needed, update the register */
  1044. if (unlikely(rq->shared->updateRxProd)) {
  1045. VMXNET3_WRITE_BAR0_REG(adapter,
  1046. rxprod_reg[ring_idx] + rq->qid * 8,
  1047. rq->rx_ring[ring_idx].next2fill);
  1048. rq->uncommitted[ring_idx] = 0;
  1049. }
  1050. }
  1051. vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
  1052. vmxnet3_getRxComp(rcd,
  1053. &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
  1054. }
  1055. return num_rxd;
  1056. }
  1057. static void
  1058. vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
  1059. struct vmxnet3_adapter *adapter)
  1060. {
  1061. u32 i, ring_idx;
  1062. struct Vmxnet3_RxDesc *rxd;
  1063. for (ring_idx = 0; ring_idx < 2; ring_idx++) {
  1064. for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
  1065. #ifdef __BIG_ENDIAN_BITFIELD
  1066. struct Vmxnet3_RxDesc rxDesc;
  1067. #endif
  1068. vmxnet3_getRxDesc(rxd,
  1069. &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
  1070. if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
  1071. rq->buf_info[ring_idx][i].skb) {
  1072. pci_unmap_single(adapter->pdev, rxd->addr,
  1073. rxd->len, PCI_DMA_FROMDEVICE);
  1074. dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
  1075. rq->buf_info[ring_idx][i].skb = NULL;
  1076. } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
  1077. rq->buf_info[ring_idx][i].page) {
  1078. pci_unmap_page(adapter->pdev, rxd->addr,
  1079. rxd->len, PCI_DMA_FROMDEVICE);
  1080. put_page(rq->buf_info[ring_idx][i].page);
  1081. rq->buf_info[ring_idx][i].page = NULL;
  1082. }
  1083. }
  1084. rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
  1085. rq->rx_ring[ring_idx].next2fill =
  1086. rq->rx_ring[ring_idx].next2comp = 0;
  1087. rq->uncommitted[ring_idx] = 0;
  1088. }
  1089. rq->comp_ring.gen = VMXNET3_INIT_GEN;
  1090. rq->comp_ring.next2proc = 0;
  1091. }
  1092. static void
  1093. vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
  1094. {
  1095. int i;
  1096. for (i = 0; i < adapter->num_rx_queues; i++)
  1097. vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
  1098. }
  1099. void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
  1100. struct vmxnet3_adapter *adapter)
  1101. {
  1102. int i;
  1103. int j;
  1104. /* all rx buffers must have already been freed */
  1105. for (i = 0; i < 2; i++) {
  1106. if (rq->buf_info[i]) {
  1107. for (j = 0; j < rq->rx_ring[i].size; j++)
  1108. BUG_ON(rq->buf_info[i][j].page != NULL);
  1109. }
  1110. }
  1111. kfree(rq->buf_info[0]);
  1112. for (i = 0; i < 2; i++) {
  1113. if (rq->rx_ring[i].base) {
  1114. pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
  1115. * sizeof(struct Vmxnet3_RxDesc),
  1116. rq->rx_ring[i].base,
  1117. rq->rx_ring[i].basePA);
  1118. rq->rx_ring[i].base = NULL;
  1119. }
  1120. rq->buf_info[i] = NULL;
  1121. }
  1122. if (rq->comp_ring.base) {
  1123. pci_free_consistent(adapter->pdev, rq->comp_ring.size *
  1124. sizeof(struct Vmxnet3_RxCompDesc),
  1125. rq->comp_ring.base, rq->comp_ring.basePA);
  1126. rq->comp_ring.base = NULL;
  1127. }
  1128. }
  1129. static int
  1130. vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
  1131. struct vmxnet3_adapter *adapter)
  1132. {
  1133. int i;
  1134. /* initialize buf_info */
  1135. for (i = 0; i < rq->rx_ring[0].size; i++) {
  1136. /* 1st buf for a pkt is skbuff */
  1137. if (i % adapter->rx_buf_per_pkt == 0) {
  1138. rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
  1139. rq->buf_info[0][i].len = adapter->skb_buf_size;
  1140. } else { /* subsequent bufs for a pkt is frag */
  1141. rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
  1142. rq->buf_info[0][i].len = PAGE_SIZE;
  1143. }
  1144. }
  1145. for (i = 0; i < rq->rx_ring[1].size; i++) {
  1146. rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
  1147. rq->buf_info[1][i].len = PAGE_SIZE;
  1148. }
  1149. /* reset internal state and allocate buffers for both rings */
  1150. for (i = 0; i < 2; i++) {
  1151. rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
  1152. rq->uncommitted[i] = 0;
  1153. memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
  1154. sizeof(struct Vmxnet3_RxDesc));
  1155. rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
  1156. }
  1157. if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
  1158. adapter) == 0) {
  1159. /* at least has 1 rx buffer for the 1st ring */
  1160. return -ENOMEM;
  1161. }
  1162. vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
  1163. /* reset the comp ring */
  1164. rq->comp_ring.next2proc = 0;
  1165. memset(rq->comp_ring.base, 0, rq->comp_ring.size *
  1166. sizeof(struct Vmxnet3_RxCompDesc));
  1167. rq->comp_ring.gen = VMXNET3_INIT_GEN;
  1168. /* reset rxctx */
  1169. rq->rx_ctx.skb = NULL;
  1170. /* stats are not reset */
  1171. return 0;
  1172. }
  1173. static int
  1174. vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
  1175. {
  1176. int i, err = 0;
  1177. for (i = 0; i < adapter->num_rx_queues; i++) {
  1178. err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
  1179. if (unlikely(err)) {
  1180. dev_err(&adapter->netdev->dev, "%s: failed to "
  1181. "initialize rx queue%i\n",
  1182. adapter->netdev->name, i);
  1183. break;
  1184. }
  1185. }
  1186. return err;
  1187. }
  1188. static int
  1189. vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
  1190. {
  1191. int i;
  1192. size_t sz;
  1193. struct vmxnet3_rx_buf_info *bi;
  1194. for (i = 0; i < 2; i++) {
  1195. sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
  1196. rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
  1197. &rq->rx_ring[i].basePA);
  1198. if (!rq->rx_ring[i].base) {
  1199. printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
  1200. adapter->netdev->name, i);
  1201. goto err;
  1202. }
  1203. }
  1204. sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
  1205. rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
  1206. &rq->comp_ring.basePA);
  1207. if (!rq->comp_ring.base) {
  1208. printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
  1209. adapter->netdev->name);
  1210. goto err;
  1211. }
  1212. sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
  1213. rq->rx_ring[1].size);
  1214. bi = kzalloc(sz, GFP_KERNEL);
  1215. if (!bi) {
  1216. printk(KERN_ERR "%s: failed to allocate rx bufinfo\n",
  1217. adapter->netdev->name);
  1218. goto err;
  1219. }
  1220. rq->buf_info[0] = bi;
  1221. rq->buf_info[1] = bi + rq->rx_ring[0].size;
  1222. return 0;
  1223. err:
  1224. vmxnet3_rq_destroy(rq, adapter);
  1225. return -ENOMEM;
  1226. }
  1227. static int
  1228. vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
  1229. {
  1230. int i, err = 0;
  1231. for (i = 0; i < adapter->num_rx_queues; i++) {
  1232. err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
  1233. if (unlikely(err)) {
  1234. dev_err(&adapter->netdev->dev,
  1235. "%s: failed to create rx queue%i\n",
  1236. adapter->netdev->name, i);
  1237. goto err_out;
  1238. }
  1239. }
  1240. return err;
  1241. err_out:
  1242. vmxnet3_rq_destroy_all(adapter);
  1243. return err;
  1244. }
  1245. /* Multiple queue aware polling function for tx and rx */
  1246. static int
  1247. vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
  1248. {
  1249. int rcd_done = 0, i;
  1250. if (unlikely(adapter->shared->ecr))
  1251. vmxnet3_process_events(adapter);
  1252. for (i = 0; i < adapter->num_tx_queues; i++)
  1253. vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
  1254. for (i = 0; i < adapter->num_rx_queues; i++)
  1255. rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
  1256. adapter, budget);
  1257. return rcd_done;
  1258. }
  1259. static int
  1260. vmxnet3_poll(struct napi_struct *napi, int budget)
  1261. {
  1262. struct vmxnet3_rx_queue *rx_queue = container_of(napi,
  1263. struct vmxnet3_rx_queue, napi);
  1264. int rxd_done;
  1265. rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
  1266. if (rxd_done < budget) {
  1267. napi_complete(napi);
  1268. vmxnet3_enable_all_intrs(rx_queue->adapter);
  1269. }
  1270. return rxd_done;
  1271. }
  1272. /*
  1273. * NAPI polling function for MSI-X mode with multiple Rx queues
  1274. * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
  1275. */
  1276. static int
  1277. vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
  1278. {
  1279. struct vmxnet3_rx_queue *rq = container_of(napi,
  1280. struct vmxnet3_rx_queue, napi);
  1281. struct vmxnet3_adapter *adapter = rq->adapter;
  1282. int rxd_done;
  1283. /* When sharing interrupt with corresponding tx queue, process
  1284. * tx completions in that queue as well
  1285. */
  1286. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
  1287. struct vmxnet3_tx_queue *tq =
  1288. &adapter->tx_queue[rq - adapter->rx_queue];
  1289. vmxnet3_tq_tx_complete(tq, adapter);
  1290. }
  1291. rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
  1292. if (rxd_done < budget) {
  1293. napi_complete(napi);
  1294. vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
  1295. }
  1296. return rxd_done;
  1297. }
  1298. #ifdef CONFIG_PCI_MSI
  1299. /*
  1300. * Handle completion interrupts on tx queues
  1301. * Returns whether or not the intr is handled
  1302. */
  1303. static irqreturn_t
  1304. vmxnet3_msix_tx(int irq, void *data)
  1305. {
  1306. struct vmxnet3_tx_queue *tq = data;
  1307. struct vmxnet3_adapter *adapter = tq->adapter;
  1308. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1309. vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
  1310. /* Handle the case where only one irq is allocate for all tx queues */
  1311. if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
  1312. int i;
  1313. for (i = 0; i < adapter->num_tx_queues; i++) {
  1314. struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
  1315. vmxnet3_tq_tx_complete(txq, adapter);
  1316. }
  1317. } else {
  1318. vmxnet3_tq_tx_complete(tq, adapter);
  1319. }
  1320. vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
  1321. return IRQ_HANDLED;
  1322. }
  1323. /*
  1324. * Handle completion interrupts on rx queues. Returns whether or not the
  1325. * intr is handled
  1326. */
  1327. static irqreturn_t
  1328. vmxnet3_msix_rx(int irq, void *data)
  1329. {
  1330. struct vmxnet3_rx_queue *rq = data;
  1331. struct vmxnet3_adapter *adapter = rq->adapter;
  1332. /* disable intr if needed */
  1333. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1334. vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
  1335. napi_schedule(&rq->napi);
  1336. return IRQ_HANDLED;
  1337. }
  1338. /*
  1339. *----------------------------------------------------------------------------
  1340. *
  1341. * vmxnet3_msix_event --
  1342. *
  1343. * vmxnet3 msix event intr handler
  1344. *
  1345. * Result:
  1346. * whether or not the intr is handled
  1347. *
  1348. *----------------------------------------------------------------------------
  1349. */
  1350. static irqreturn_t
  1351. vmxnet3_msix_event(int irq, void *data)
  1352. {
  1353. struct net_device *dev = data;
  1354. struct vmxnet3_adapter *adapter = netdev_priv(dev);
  1355. /* disable intr if needed */
  1356. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1357. vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
  1358. if (adapter->shared->ecr)
  1359. vmxnet3_process_events(adapter);
  1360. vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
  1361. return IRQ_HANDLED;
  1362. }
  1363. #endif /* CONFIG_PCI_MSI */
  1364. /* Interrupt handler for vmxnet3 */
  1365. static irqreturn_t
  1366. vmxnet3_intr(int irq, void *dev_id)
  1367. {
  1368. struct net_device *dev = dev_id;
  1369. struct vmxnet3_adapter *adapter = netdev_priv(dev);
  1370. if (adapter->intr.type == VMXNET3_IT_INTX) {
  1371. u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
  1372. if (unlikely(icr == 0))
  1373. /* not ours */
  1374. return IRQ_NONE;
  1375. }
  1376. /* disable intr if needed */
  1377. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1378. vmxnet3_disable_all_intrs(adapter);
  1379. napi_schedule(&adapter->rx_queue[0].napi);
  1380. return IRQ_HANDLED;
  1381. }
  1382. #ifdef CONFIG_NET_POLL_CONTROLLER
  1383. /* netpoll callback. */
  1384. static void
  1385. vmxnet3_netpoll(struct net_device *netdev)
  1386. {
  1387. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1388. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1389. vmxnet3_disable_all_intrs(adapter);
  1390. vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
  1391. vmxnet3_enable_all_intrs(adapter);
  1392. }
  1393. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1394. static int
  1395. vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
  1396. {
  1397. struct vmxnet3_intr *intr = &adapter->intr;
  1398. int err = 0, i;
  1399. int vector = 0;
  1400. #ifdef CONFIG_PCI_MSI
  1401. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  1402. for (i = 0; i < adapter->num_tx_queues; i++) {
  1403. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
  1404. sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
  1405. adapter->netdev->name, vector);
  1406. err = request_irq(
  1407. intr->msix_entries[vector].vector,
  1408. vmxnet3_msix_tx, 0,
  1409. adapter->tx_queue[i].name,
  1410. &adapter->tx_queue[i]);
  1411. } else {
  1412. sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
  1413. adapter->netdev->name, vector);
  1414. }
  1415. if (err) {
  1416. dev_err(&adapter->netdev->dev,
  1417. "Failed to request irq for MSIX, %s, "
  1418. "error %d\n",
  1419. adapter->tx_queue[i].name, err);
  1420. return err;
  1421. }
  1422. /* Handle the case where only 1 MSIx was allocated for
  1423. * all tx queues */
  1424. if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
  1425. for (; i < adapter->num_tx_queues; i++)
  1426. adapter->tx_queue[i].comp_ring.intr_idx
  1427. = vector;
  1428. vector++;
  1429. break;
  1430. } else {
  1431. adapter->tx_queue[i].comp_ring.intr_idx
  1432. = vector++;
  1433. }
  1434. }
  1435. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
  1436. vector = 0;
  1437. for (i = 0; i < adapter->num_rx_queues; i++) {
  1438. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
  1439. sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
  1440. adapter->netdev->name, vector);
  1441. else
  1442. sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
  1443. adapter->netdev->name, vector);
  1444. err = request_irq(intr->msix_entries[vector].vector,
  1445. vmxnet3_msix_rx, 0,
  1446. adapter->rx_queue[i].name,
  1447. &(adapter->rx_queue[i]));
  1448. if (err) {
  1449. printk(KERN_ERR "Failed to request irq for MSIX"
  1450. ", %s, error %d\n",
  1451. adapter->rx_queue[i].name, err);
  1452. return err;
  1453. }
  1454. adapter->rx_queue[i].comp_ring.intr_idx = vector++;
  1455. }
  1456. sprintf(intr->event_msi_vector_name, "%s-event-%d",
  1457. adapter->netdev->name, vector);
  1458. err = request_irq(intr->msix_entries[vector].vector,
  1459. vmxnet3_msix_event, 0,
  1460. intr->event_msi_vector_name, adapter->netdev);
  1461. intr->event_intr_idx = vector;
  1462. } else if (intr->type == VMXNET3_IT_MSI) {
  1463. adapter->num_rx_queues = 1;
  1464. err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
  1465. adapter->netdev->name, adapter->netdev);
  1466. } else {
  1467. #endif
  1468. adapter->num_rx_queues = 1;
  1469. err = request_irq(adapter->pdev->irq, vmxnet3_intr,
  1470. IRQF_SHARED, adapter->netdev->name,
  1471. adapter->netdev);
  1472. #ifdef CONFIG_PCI_MSI
  1473. }
  1474. #endif
  1475. intr->num_intrs = vector + 1;
  1476. if (err) {
  1477. printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
  1478. ":%d\n", adapter->netdev->name, intr->type, err);
  1479. } else {
  1480. /* Number of rx queues will not change after this */
  1481. for (i = 0; i < adapter->num_rx_queues; i++) {
  1482. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  1483. rq->qid = i;
  1484. rq->qid2 = i + adapter->num_rx_queues;
  1485. }
  1486. /* init our intr settings */
  1487. for (i = 0; i < intr->num_intrs; i++)
  1488. intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
  1489. if (adapter->intr.type != VMXNET3_IT_MSIX) {
  1490. adapter->intr.event_intr_idx = 0;
  1491. for (i = 0; i < adapter->num_tx_queues; i++)
  1492. adapter->tx_queue[i].comp_ring.intr_idx = 0;
  1493. adapter->rx_queue[0].comp_ring.intr_idx = 0;
  1494. }
  1495. printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
  1496. "allocated\n", adapter->netdev->name, intr->type,
  1497. intr->mask_mode, intr->num_intrs);
  1498. }
  1499. return err;
  1500. }
  1501. static void
  1502. vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
  1503. {
  1504. struct vmxnet3_intr *intr = &adapter->intr;
  1505. BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
  1506. switch (intr->type) {
  1507. #ifdef CONFIG_PCI_MSI
  1508. case VMXNET3_IT_MSIX:
  1509. {
  1510. int i, vector = 0;
  1511. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
  1512. for (i = 0; i < adapter->num_tx_queues; i++) {
  1513. free_irq(intr->msix_entries[vector++].vector,
  1514. &(adapter->tx_queue[i]));
  1515. if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
  1516. break;
  1517. }
  1518. }
  1519. for (i = 0; i < adapter->num_rx_queues; i++) {
  1520. free_irq(intr->msix_entries[vector++].vector,
  1521. &(adapter->rx_queue[i]));
  1522. }
  1523. free_irq(intr->msix_entries[vector].vector,
  1524. adapter->netdev);
  1525. BUG_ON(vector >= intr->num_intrs);
  1526. break;
  1527. }
  1528. #endif
  1529. case VMXNET3_IT_MSI:
  1530. free_irq(adapter->pdev->irq, adapter->netdev);
  1531. break;
  1532. case VMXNET3_IT_INTX:
  1533. free_irq(adapter->pdev->irq, adapter->netdev);
  1534. break;
  1535. default:
  1536. BUG_ON(true);
  1537. }
  1538. }
  1539. static void
  1540. vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
  1541. {
  1542. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1543. struct Vmxnet3_DriverShared *shared = adapter->shared;
  1544. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1545. if (grp) {
  1546. /* add vlan rx stripping. */
  1547. if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) {
  1548. int i;
  1549. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1550. adapter->vlan_grp = grp;
  1551. /* update FEATURES to device */
  1552. devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
  1553. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1554. VMXNET3_CMD_UPDATE_FEATURE);
  1555. /*
  1556. * Clear entire vfTable; then enable untagged pkts.
  1557. * Note: setting one entry in vfTable to non-zero turns
  1558. * on VLAN rx filtering.
  1559. */
  1560. for (i = 0; i < VMXNET3_VFT_SIZE; i++)
  1561. vfTable[i] = 0;
  1562. VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
  1563. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1564. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1565. } else {
  1566. printk(KERN_ERR "%s: vlan_rx_register when device has "
  1567. "no NETIF_F_HW_VLAN_RX\n", netdev->name);
  1568. }
  1569. } else {
  1570. /* remove vlan rx stripping. */
  1571. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1572. adapter->vlan_grp = NULL;
  1573. if (devRead->misc.uptFeatures & UPT1_F_RXVLAN) {
  1574. int i;
  1575. for (i = 0; i < VMXNET3_VFT_SIZE; i++) {
  1576. /* clear entire vfTable; this also disables
  1577. * VLAN rx filtering
  1578. */
  1579. vfTable[i] = 0;
  1580. }
  1581. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1582. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1583. /* update FEATURES to device */
  1584. devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
  1585. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1586. VMXNET3_CMD_UPDATE_FEATURE);
  1587. }
  1588. }
  1589. }
  1590. static void
  1591. vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
  1592. {
  1593. if (adapter->vlan_grp) {
  1594. u16 vid;
  1595. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1596. bool activeVlan = false;
  1597. for (vid = 0; vid < VLAN_N_VID; vid++) {
  1598. if (vlan_group_get_device(adapter->vlan_grp, vid)) {
  1599. VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
  1600. activeVlan = true;
  1601. }
  1602. }
  1603. if (activeVlan) {
  1604. /* continue to allow untagged pkts */
  1605. VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
  1606. }
  1607. }
  1608. }
  1609. static void
  1610. vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
  1611. {
  1612. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1613. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1614. VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
  1615. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1616. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1617. }
  1618. static void
  1619. vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
  1620. {
  1621. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1622. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1623. VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
  1624. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1625. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1626. }
  1627. static u8 *
  1628. vmxnet3_copy_mc(struct net_device *netdev)
  1629. {
  1630. u8 *buf = NULL;
  1631. u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
  1632. /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
  1633. if (sz <= 0xffff) {
  1634. /* We may be called with BH disabled */
  1635. buf = kmalloc(sz, GFP_ATOMIC);
  1636. if (buf) {
  1637. struct netdev_hw_addr *ha;
  1638. int i = 0;
  1639. netdev_for_each_mc_addr(ha, netdev)
  1640. memcpy(buf + i++ * ETH_ALEN, ha->addr,
  1641. ETH_ALEN);
  1642. }
  1643. }
  1644. return buf;
  1645. }
  1646. static void
  1647. vmxnet3_set_mc(struct net_device *netdev)
  1648. {
  1649. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1650. struct Vmxnet3_RxFilterConf *rxConf =
  1651. &adapter->shared->devRead.rxFilterConf;
  1652. u8 *new_table = NULL;
  1653. u32 new_mode = VMXNET3_RXM_UCAST;
  1654. if (netdev->flags & IFF_PROMISC)
  1655. new_mode |= VMXNET3_RXM_PROMISC;
  1656. if (netdev->flags & IFF_BROADCAST)
  1657. new_mode |= VMXNET3_RXM_BCAST;
  1658. if (netdev->flags & IFF_ALLMULTI)
  1659. new_mode |= VMXNET3_RXM_ALL_MULTI;
  1660. else
  1661. if (!netdev_mc_empty(netdev)) {
  1662. new_table = vmxnet3_copy_mc(netdev);
  1663. if (new_table) {
  1664. new_mode |= VMXNET3_RXM_MCAST;
  1665. rxConf->mfTableLen = cpu_to_le16(
  1666. netdev_mc_count(netdev) * ETH_ALEN);
  1667. rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
  1668. new_table));
  1669. } else {
  1670. printk(KERN_INFO "%s: failed to copy mcast list"
  1671. ", setting ALL_MULTI\n", netdev->name);
  1672. new_mode |= VMXNET3_RXM_ALL_MULTI;
  1673. }
  1674. }
  1675. if (!(new_mode & VMXNET3_RXM_MCAST)) {
  1676. rxConf->mfTableLen = 0;
  1677. rxConf->mfTablePA = 0;
  1678. }
  1679. if (new_mode != rxConf->rxMode) {
  1680. rxConf->rxMode = cpu_to_le32(new_mode);
  1681. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1682. VMXNET3_CMD_UPDATE_RX_MODE);
  1683. }
  1684. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1685. VMXNET3_CMD_UPDATE_MAC_FILTERS);
  1686. kfree(new_table);
  1687. }
  1688. void
  1689. vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
  1690. {
  1691. int i;
  1692. for (i = 0; i < adapter->num_rx_queues; i++)
  1693. vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
  1694. }
  1695. /*
  1696. * Set up driver_shared based on settings in adapter.
  1697. */
  1698. static void
  1699. vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
  1700. {
  1701. struct Vmxnet3_DriverShared *shared = adapter->shared;
  1702. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1703. struct Vmxnet3_TxQueueConf *tqc;
  1704. struct Vmxnet3_RxQueueConf *rqc;
  1705. int i;
  1706. memset(shared, 0, sizeof(*shared));
  1707. /* driver settings */
  1708. shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
  1709. devRead->misc.driverInfo.version = cpu_to_le32(
  1710. VMXNET3_DRIVER_VERSION_NUM);
  1711. devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
  1712. VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
  1713. devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
  1714. *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
  1715. *((u32 *)&devRead->misc.driverInfo.gos));
  1716. devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
  1717. devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
  1718. devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
  1719. devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
  1720. /* set up feature flags */
  1721. if (adapter->rxcsum)
  1722. devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
  1723. if (adapter->lro) {
  1724. devRead->misc.uptFeatures |= UPT1_F_LRO;
  1725. devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
  1726. }
  1727. if ((adapter->netdev->features & NETIF_F_HW_VLAN_RX) &&
  1728. adapter->vlan_grp) {
  1729. devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
  1730. }
  1731. devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
  1732. devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
  1733. devRead->misc.queueDescLen = cpu_to_le32(
  1734. adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
  1735. adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
  1736. /* tx queue settings */
  1737. devRead->misc.numTxQueues = adapter->num_tx_queues;
  1738. for (i = 0; i < adapter->num_tx_queues; i++) {
  1739. struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
  1740. BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
  1741. tqc = &adapter->tqd_start[i].conf;
  1742. tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
  1743. tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
  1744. tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
  1745. tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
  1746. tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
  1747. tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
  1748. tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
  1749. tqc->ddLen = cpu_to_le32(
  1750. sizeof(struct vmxnet3_tx_buf_info) *
  1751. tqc->txRingSize);
  1752. tqc->intrIdx = tq->comp_ring.intr_idx;
  1753. }
  1754. /* rx queue settings */
  1755. devRead->misc.numRxQueues = adapter->num_rx_queues;
  1756. for (i = 0; i < adapter->num_rx_queues; i++) {
  1757. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  1758. rqc = &adapter->rqd_start[i].conf;
  1759. rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
  1760. rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
  1761. rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
  1762. rqc->ddPA = cpu_to_le64(virt_to_phys(
  1763. rq->buf_info));
  1764. rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
  1765. rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
  1766. rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
  1767. rqc->ddLen = cpu_to_le32(
  1768. sizeof(struct vmxnet3_rx_buf_info) *
  1769. (rqc->rxRingSize[0] +
  1770. rqc->rxRingSize[1]));
  1771. rqc->intrIdx = rq->comp_ring.intr_idx;
  1772. }
  1773. #ifdef VMXNET3_RSS
  1774. memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
  1775. if (adapter->rss) {
  1776. struct UPT1_RSSConf *rssConf = adapter->rss_conf;
  1777. devRead->misc.uptFeatures |= UPT1_F_RSS;
  1778. devRead->misc.numRxQueues = adapter->num_rx_queues;
  1779. rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
  1780. UPT1_RSS_HASH_TYPE_IPV4 |
  1781. UPT1_RSS_HASH_TYPE_TCP_IPV6 |
  1782. UPT1_RSS_HASH_TYPE_IPV6;
  1783. rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
  1784. rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
  1785. rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
  1786. get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
  1787. for (i = 0; i < rssConf->indTableSize; i++)
  1788. rssConf->indTable[i] = i % adapter->num_rx_queues;
  1789. devRead->rssConfDesc.confVer = 1;
  1790. devRead->rssConfDesc.confLen = sizeof(*rssConf);
  1791. devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
  1792. }
  1793. #endif /* VMXNET3_RSS */
  1794. /* intr settings */
  1795. devRead->intrConf.autoMask = adapter->intr.mask_mode ==
  1796. VMXNET3_IMM_AUTO;
  1797. devRead->intrConf.numIntrs = adapter->intr.num_intrs;
  1798. for (i = 0; i < adapter->intr.num_intrs; i++)
  1799. devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
  1800. devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
  1801. devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  1802. /* rx filter settings */
  1803. devRead->rxFilterConf.rxMode = 0;
  1804. vmxnet3_restore_vlan(adapter);
  1805. /* the rest are already zeroed */
  1806. }
  1807. int
  1808. vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
  1809. {
  1810. int err, i;
  1811. u32 ret;
  1812. dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
  1813. " ring sizes %u %u %u\n", adapter->netdev->name,
  1814. adapter->skb_buf_size, adapter->rx_buf_per_pkt,
  1815. adapter->tx_queue[0].tx_ring.size,
  1816. adapter->rx_queue[0].rx_ring[0].size,
  1817. adapter->rx_queue[0].rx_ring[1].size);
  1818. vmxnet3_tq_init_all(adapter);
  1819. err = vmxnet3_rq_init_all(adapter);
  1820. if (err) {
  1821. printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
  1822. adapter->netdev->name, err);
  1823. goto rq_err;
  1824. }
  1825. err = vmxnet3_request_irqs(adapter);
  1826. if (err) {
  1827. printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
  1828. adapter->netdev->name, err);
  1829. goto irq_err;
  1830. }
  1831. vmxnet3_setup_driver_shared(adapter);
  1832. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
  1833. adapter->shared_pa));
  1834. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
  1835. adapter->shared_pa));
  1836. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1837. VMXNET3_CMD_ACTIVATE_DEV);
  1838. ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  1839. if (ret != 0) {
  1840. printk(KERN_ERR "Failed to activate dev %s: error %u\n",
  1841. adapter->netdev->name, ret);
  1842. err = -EINVAL;
  1843. goto activate_err;
  1844. }
  1845. for (i = 0; i < adapter->num_rx_queues; i++) {
  1846. VMXNET3_WRITE_BAR0_REG(adapter,
  1847. VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
  1848. adapter->rx_queue[i].rx_ring[0].next2fill);
  1849. VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
  1850. (i * VMXNET3_REG_ALIGN)),
  1851. adapter->rx_queue[i].rx_ring[1].next2fill);
  1852. }
  1853. /* Apply the rx filter settins last. */
  1854. vmxnet3_set_mc(adapter->netdev);
  1855. /*
  1856. * Check link state when first activating device. It will start the
  1857. * tx queue if the link is up.
  1858. */
  1859. vmxnet3_check_link(adapter, true);
  1860. for (i = 0; i < adapter->num_rx_queues; i++)
  1861. napi_enable(&adapter->rx_queue[i].napi);
  1862. vmxnet3_enable_all_intrs(adapter);
  1863. clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
  1864. return 0;
  1865. activate_err:
  1866. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
  1867. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
  1868. vmxnet3_free_irqs(adapter);
  1869. irq_err:
  1870. rq_err:
  1871. /* free up buffers we allocated */
  1872. vmxnet3_rq_cleanup_all(adapter);
  1873. return err;
  1874. }
  1875. void
  1876. vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
  1877. {
  1878. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
  1879. }
  1880. int
  1881. vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
  1882. {
  1883. int i;
  1884. if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
  1885. return 0;
  1886. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1887. VMXNET3_CMD_QUIESCE_DEV);
  1888. vmxnet3_disable_all_intrs(adapter);
  1889. for (i = 0; i < adapter->num_rx_queues; i++)
  1890. napi_disable(&adapter->rx_queue[i].napi);
  1891. netif_tx_disable(adapter->netdev);
  1892. adapter->link_speed = 0;
  1893. netif_carrier_off(adapter->netdev);
  1894. vmxnet3_tq_cleanup_all(adapter);
  1895. vmxnet3_rq_cleanup_all(adapter);
  1896. vmxnet3_free_irqs(adapter);
  1897. return 0;
  1898. }
  1899. static void
  1900. vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
  1901. {
  1902. u32 tmp;
  1903. tmp = *(u32 *)mac;
  1904. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
  1905. tmp = (mac[5] << 8) | mac[4];
  1906. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
  1907. }
  1908. static int
  1909. vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
  1910. {
  1911. struct sockaddr *addr = p;
  1912. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1913. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1914. vmxnet3_write_mac_addr(adapter, addr->sa_data);
  1915. return 0;
  1916. }
  1917. /* ==================== initialization and cleanup routines ============ */
  1918. static int
  1919. vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
  1920. {
  1921. int err;
  1922. unsigned long mmio_start, mmio_len;
  1923. struct pci_dev *pdev = adapter->pdev;
  1924. err = pci_enable_device(pdev);
  1925. if (err) {
  1926. printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
  1927. pci_name(pdev), err);
  1928. return err;
  1929. }
  1930. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
  1931. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
  1932. printk(KERN_ERR "pci_set_consistent_dma_mask failed "
  1933. "for adapter %s\n", pci_name(pdev));
  1934. err = -EIO;
  1935. goto err_set_mask;
  1936. }
  1937. *dma64 = true;
  1938. } else {
  1939. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
  1940. printk(KERN_ERR "pci_set_dma_mask failed for adapter "
  1941. "%s\n", pci_name(pdev));
  1942. err = -EIO;
  1943. goto err_set_mask;
  1944. }
  1945. *dma64 = false;
  1946. }
  1947. err = pci_request_selected_regions(pdev, (1 << 2) - 1,
  1948. vmxnet3_driver_name);
  1949. if (err) {
  1950. printk(KERN_ERR "Failed to request region for adapter %s: "
  1951. "error %d\n", pci_name(pdev), err);
  1952. goto err_set_mask;
  1953. }
  1954. pci_set_master(pdev);
  1955. mmio_start = pci_resource_start(pdev, 0);
  1956. mmio_len = pci_resource_len(pdev, 0);
  1957. adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
  1958. if (!adapter->hw_addr0) {
  1959. printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
  1960. pci_name(pdev));
  1961. err = -EIO;
  1962. goto err_ioremap;
  1963. }
  1964. mmio_start = pci_resource_start(pdev, 1);
  1965. mmio_len = pci_resource_len(pdev, 1);
  1966. adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
  1967. if (!adapter->hw_addr1) {
  1968. printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
  1969. pci_name(pdev));
  1970. err = -EIO;
  1971. goto err_bar1;
  1972. }
  1973. return 0;
  1974. err_bar1:
  1975. iounmap(adapter->hw_addr0);
  1976. err_ioremap:
  1977. pci_release_selected_regions(pdev, (1 << 2) - 1);
  1978. err_set_mask:
  1979. pci_disable_device(pdev);
  1980. return err;
  1981. }
  1982. static void
  1983. vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
  1984. {
  1985. BUG_ON(!adapter->pdev);
  1986. iounmap(adapter->hw_addr0);
  1987. iounmap(adapter->hw_addr1);
  1988. pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
  1989. pci_disable_device(adapter->pdev);
  1990. }
  1991. static void
  1992. vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
  1993. {
  1994. size_t sz, i, ring0_size, ring1_size, comp_size;
  1995. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
  1996. if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
  1997. VMXNET3_MAX_ETH_HDR_SIZE) {
  1998. adapter->skb_buf_size = adapter->netdev->mtu +
  1999. VMXNET3_MAX_ETH_HDR_SIZE;
  2000. if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
  2001. adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
  2002. adapter->rx_buf_per_pkt = 1;
  2003. } else {
  2004. adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
  2005. sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
  2006. VMXNET3_MAX_ETH_HDR_SIZE;
  2007. adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
  2008. }
  2009. /*
  2010. * for simplicity, force the ring0 size to be a multiple of
  2011. * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
  2012. */
  2013. sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
  2014. ring0_size = adapter->rx_queue[0].rx_ring[0].size;
  2015. ring0_size = (ring0_size + sz - 1) / sz * sz;
  2016. ring0_size = min_t(u32, rq->rx_ring[0].size, VMXNET3_RX_RING_MAX_SIZE /
  2017. sz * sz);
  2018. ring1_size = adapter->rx_queue[0].rx_ring[1].size;
  2019. comp_size = ring0_size + ring1_size;
  2020. for (i = 0; i < adapter->num_rx_queues; i++) {
  2021. rq = &adapter->rx_queue[i];
  2022. rq->rx_ring[0].size = ring0_size;
  2023. rq->rx_ring[1].size = ring1_size;
  2024. rq->comp_ring.size = comp_size;
  2025. }
  2026. }
  2027. int
  2028. vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
  2029. u32 rx_ring_size, u32 rx_ring2_size)
  2030. {
  2031. int err = 0, i;
  2032. for (i = 0; i < adapter->num_tx_queues; i++) {
  2033. struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
  2034. tq->tx_ring.size = tx_ring_size;
  2035. tq->data_ring.size = tx_ring_size;
  2036. tq->comp_ring.size = tx_ring_size;
  2037. tq->shared = &adapter->tqd_start[i].ctrl;
  2038. tq->stopped = true;
  2039. tq->adapter = adapter;
  2040. tq->qid = i;
  2041. err = vmxnet3_tq_create(tq, adapter);
  2042. /*
  2043. * Too late to change num_tx_queues. We cannot do away with
  2044. * lesser number of queues than what we asked for
  2045. */
  2046. if (err)
  2047. goto queue_err;
  2048. }
  2049. adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
  2050. adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
  2051. vmxnet3_adjust_rx_ring_size(adapter);
  2052. for (i = 0; i < adapter->num_rx_queues; i++) {
  2053. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  2054. /* qid and qid2 for rx queues will be assigned later when num
  2055. * of rx queues is finalized after allocating intrs */
  2056. rq->shared = &adapter->rqd_start[i].ctrl;
  2057. rq->adapter = adapter;
  2058. err = vmxnet3_rq_create(rq, adapter);
  2059. if (err) {
  2060. if (i == 0) {
  2061. printk(KERN_ERR "Could not allocate any rx"
  2062. "queues. Aborting.\n");
  2063. goto queue_err;
  2064. } else {
  2065. printk(KERN_INFO "Number of rx queues changed "
  2066. "to : %d.\n", i);
  2067. adapter->num_rx_queues = i;
  2068. err = 0;
  2069. break;
  2070. }
  2071. }
  2072. }
  2073. return err;
  2074. queue_err:
  2075. vmxnet3_tq_destroy_all(adapter);
  2076. return err;
  2077. }
  2078. static int
  2079. vmxnet3_open(struct net_device *netdev)
  2080. {
  2081. struct vmxnet3_adapter *adapter;
  2082. int err, i;
  2083. adapter = netdev_priv(netdev);
  2084. for (i = 0; i < adapter->num_tx_queues; i++)
  2085. spin_lock_init(&adapter->tx_queue[i].tx_lock);
  2086. err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
  2087. VMXNET3_DEF_RX_RING_SIZE,
  2088. VMXNET3_DEF_RX_RING_SIZE);
  2089. if (err)
  2090. goto queue_err;
  2091. err = vmxnet3_activate_dev(adapter);
  2092. if (err)
  2093. goto activate_err;
  2094. return 0;
  2095. activate_err:
  2096. vmxnet3_rq_destroy_all(adapter);
  2097. vmxnet3_tq_destroy_all(adapter);
  2098. queue_err:
  2099. return err;
  2100. }
  2101. static int
  2102. vmxnet3_close(struct net_device *netdev)
  2103. {
  2104. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2105. /*
  2106. * Reset_work may be in the middle of resetting the device, wait for its
  2107. * completion.
  2108. */
  2109. while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2110. msleep(1);
  2111. vmxnet3_quiesce_dev(adapter);
  2112. vmxnet3_rq_destroy_all(adapter);
  2113. vmxnet3_tq_destroy_all(adapter);
  2114. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2115. return 0;
  2116. }
  2117. void
  2118. vmxnet3_force_close(struct vmxnet3_adapter *adapter)
  2119. {
  2120. int i;
  2121. /*
  2122. * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
  2123. * vmxnet3_close() will deadlock.
  2124. */
  2125. BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
  2126. /* we need to enable NAPI, otherwise dev_close will deadlock */
  2127. for (i = 0; i < adapter->num_rx_queues; i++)
  2128. napi_enable(&adapter->rx_queue[i].napi);
  2129. dev_close(adapter->netdev);
  2130. }
  2131. static int
  2132. vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
  2133. {
  2134. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2135. int err = 0;
  2136. if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
  2137. return -EINVAL;
  2138. if (new_mtu > 1500 && !adapter->jumbo_frame)
  2139. return -EINVAL;
  2140. netdev->mtu = new_mtu;
  2141. /*
  2142. * Reset_work may be in the middle of resetting the device, wait for its
  2143. * completion.
  2144. */
  2145. while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2146. msleep(1);
  2147. if (netif_running(netdev)) {
  2148. vmxnet3_quiesce_dev(adapter);
  2149. vmxnet3_reset_dev(adapter);
  2150. /* we need to re-create the rx queue based on the new mtu */
  2151. vmxnet3_rq_destroy_all(adapter);
  2152. vmxnet3_adjust_rx_ring_size(adapter);
  2153. err = vmxnet3_rq_create_all(adapter);
  2154. if (err) {
  2155. printk(KERN_ERR "%s: failed to re-create rx queues,"
  2156. " error %d. Closing it.\n", netdev->name, err);
  2157. goto out;
  2158. }
  2159. err = vmxnet3_activate_dev(adapter);
  2160. if (err) {
  2161. printk(KERN_ERR "%s: failed to re-activate, error %d. "
  2162. "Closing it\n", netdev->name, err);
  2163. goto out;
  2164. }
  2165. }
  2166. out:
  2167. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2168. if (err)
  2169. vmxnet3_force_close(adapter);
  2170. return err;
  2171. }
  2172. static void
  2173. vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
  2174. {
  2175. struct net_device *netdev = adapter->netdev;
  2176. netdev->features = NETIF_F_SG |
  2177. NETIF_F_HW_CSUM |
  2178. NETIF_F_HW_VLAN_TX |
  2179. NETIF_F_HW_VLAN_RX |
  2180. NETIF_F_HW_VLAN_FILTER |
  2181. NETIF_F_TSO |
  2182. NETIF_F_TSO6 |
  2183. NETIF_F_LRO;
  2184. printk(KERN_INFO "features: sg csum vlan jf tso tsoIPv6 lro");
  2185. adapter->rxcsum = true;
  2186. adapter->jumbo_frame = true;
  2187. adapter->lro = true;
  2188. if (dma64) {
  2189. netdev->features |= NETIF_F_HIGHDMA;
  2190. printk(" highDMA");
  2191. }
  2192. netdev->vlan_features = netdev->features;
  2193. printk("\n");
  2194. }
  2195. static void
  2196. vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
  2197. {
  2198. u32 tmp;
  2199. tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
  2200. *(u32 *)mac = tmp;
  2201. tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
  2202. mac[4] = tmp & 0xff;
  2203. mac[5] = (tmp >> 8) & 0xff;
  2204. }
  2205. #ifdef CONFIG_PCI_MSI
  2206. /*
  2207. * Enable MSIx vectors.
  2208. * Returns :
  2209. * 0 on successful enabling of required vectors,
  2210. * VMXNET3_LINUX_MIN_MSIX_VECT when only minumum number of vectors required
  2211. * could be enabled.
  2212. * number of vectors which can be enabled otherwise (this number is smaller
  2213. * than VMXNET3_LINUX_MIN_MSIX_VECT)
  2214. */
  2215. static int
  2216. vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
  2217. int vectors)
  2218. {
  2219. int err = 0, vector_threshold;
  2220. vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
  2221. while (vectors >= vector_threshold) {
  2222. err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
  2223. vectors);
  2224. if (!err) {
  2225. adapter->intr.num_intrs = vectors;
  2226. return 0;
  2227. } else if (err < 0) {
  2228. printk(KERN_ERR "Failed to enable MSI-X for %s, error"
  2229. " %d\n", adapter->netdev->name, err);
  2230. vectors = 0;
  2231. } else if (err < vector_threshold) {
  2232. break;
  2233. } else {
  2234. /* If fails to enable required number of MSI-x vectors
  2235. * try enabling 3 of them. One each for rx, tx and event
  2236. */
  2237. vectors = vector_threshold;
  2238. printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
  2239. " %d instead\n", vectors, adapter->netdev->name,
  2240. vector_threshold);
  2241. }
  2242. }
  2243. printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
  2244. " are lower than min threshold required.\n");
  2245. return err;
  2246. }
  2247. #endif /* CONFIG_PCI_MSI */
  2248. static void
  2249. vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
  2250. {
  2251. u32 cfg;
  2252. /* intr settings */
  2253. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2254. VMXNET3_CMD_GET_CONF_INTR);
  2255. cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  2256. adapter->intr.type = cfg & 0x3;
  2257. adapter->intr.mask_mode = (cfg >> 2) & 0x3;
  2258. if (adapter->intr.type == VMXNET3_IT_AUTO) {
  2259. adapter->intr.type = VMXNET3_IT_MSIX;
  2260. }
  2261. #ifdef CONFIG_PCI_MSI
  2262. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  2263. int vector, err = 0;
  2264. adapter->intr.num_intrs = (adapter->share_intr ==
  2265. VMXNET3_INTR_TXSHARE) ? 1 :
  2266. adapter->num_tx_queues;
  2267. adapter->intr.num_intrs += (adapter->share_intr ==
  2268. VMXNET3_INTR_BUDDYSHARE) ? 0 :
  2269. adapter->num_rx_queues;
  2270. adapter->intr.num_intrs += 1; /* for link event */
  2271. adapter->intr.num_intrs = (adapter->intr.num_intrs >
  2272. VMXNET3_LINUX_MIN_MSIX_VECT
  2273. ? adapter->intr.num_intrs :
  2274. VMXNET3_LINUX_MIN_MSIX_VECT);
  2275. for (vector = 0; vector < adapter->intr.num_intrs; vector++)
  2276. adapter->intr.msix_entries[vector].entry = vector;
  2277. err = vmxnet3_acquire_msix_vectors(adapter,
  2278. adapter->intr.num_intrs);
  2279. /* If we cannot allocate one MSIx vector per queue
  2280. * then limit the number of rx queues to 1
  2281. */
  2282. if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
  2283. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
  2284. || adapter->num_rx_queues != 2) {
  2285. adapter->share_intr = VMXNET3_INTR_TXSHARE;
  2286. printk(KERN_ERR "Number of rx queues : 1\n");
  2287. adapter->num_rx_queues = 1;
  2288. adapter->intr.num_intrs =
  2289. VMXNET3_LINUX_MIN_MSIX_VECT;
  2290. }
  2291. return;
  2292. }
  2293. if (!err)
  2294. return;
  2295. /* If we cannot allocate MSIx vectors use only one rx queue */
  2296. printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
  2297. "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
  2298. adapter->intr.type = VMXNET3_IT_MSI;
  2299. }
  2300. if (adapter->intr.type == VMXNET3_IT_MSI) {
  2301. int err;
  2302. err = pci_enable_msi(adapter->pdev);
  2303. if (!err) {
  2304. adapter->num_rx_queues = 1;
  2305. adapter->intr.num_intrs = 1;
  2306. return;
  2307. }
  2308. }
  2309. #endif /* CONFIG_PCI_MSI */
  2310. adapter->num_rx_queues = 1;
  2311. printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
  2312. adapter->intr.type = VMXNET3_IT_INTX;
  2313. /* INT-X related setting */
  2314. adapter->intr.num_intrs = 1;
  2315. }
  2316. static void
  2317. vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
  2318. {
  2319. if (adapter->intr.type == VMXNET3_IT_MSIX)
  2320. pci_disable_msix(adapter->pdev);
  2321. else if (adapter->intr.type == VMXNET3_IT_MSI)
  2322. pci_disable_msi(adapter->pdev);
  2323. else
  2324. BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
  2325. }
  2326. static void
  2327. vmxnet3_tx_timeout(struct net_device *netdev)
  2328. {
  2329. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2330. adapter->tx_timeout_count++;
  2331. printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
  2332. schedule_work(&adapter->work);
  2333. netif_wake_queue(adapter->netdev);
  2334. }
  2335. static void
  2336. vmxnet3_reset_work(struct work_struct *data)
  2337. {
  2338. struct vmxnet3_adapter *adapter;
  2339. adapter = container_of(data, struct vmxnet3_adapter, work);
  2340. /* if another thread is resetting the device, no need to proceed */
  2341. if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2342. return;
  2343. /* if the device is closed, we must leave it alone */
  2344. rtnl_lock();
  2345. if (netif_running(adapter->netdev)) {
  2346. printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
  2347. vmxnet3_quiesce_dev(adapter);
  2348. vmxnet3_reset_dev(adapter);
  2349. vmxnet3_activate_dev(adapter);
  2350. } else {
  2351. printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
  2352. }
  2353. rtnl_unlock();
  2354. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2355. }
  2356. static int __devinit
  2357. vmxnet3_probe_device(struct pci_dev *pdev,
  2358. const struct pci_device_id *id)
  2359. {
  2360. static const struct net_device_ops vmxnet3_netdev_ops = {
  2361. .ndo_open = vmxnet3_open,
  2362. .ndo_stop = vmxnet3_close,
  2363. .ndo_start_xmit = vmxnet3_xmit_frame,
  2364. .ndo_set_mac_address = vmxnet3_set_mac_addr,
  2365. .ndo_change_mtu = vmxnet3_change_mtu,
  2366. .ndo_get_stats = vmxnet3_get_stats,
  2367. .ndo_tx_timeout = vmxnet3_tx_timeout,
  2368. .ndo_set_multicast_list = vmxnet3_set_mc,
  2369. .ndo_vlan_rx_register = vmxnet3_vlan_rx_register,
  2370. .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
  2371. .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
  2372. #ifdef CONFIG_NET_POLL_CONTROLLER
  2373. .ndo_poll_controller = vmxnet3_netpoll,
  2374. #endif
  2375. };
  2376. int err;
  2377. bool dma64 = false; /* stupid gcc */
  2378. u32 ver;
  2379. struct net_device *netdev;
  2380. struct vmxnet3_adapter *adapter;
  2381. u8 mac[ETH_ALEN];
  2382. int size;
  2383. int num_tx_queues;
  2384. int num_rx_queues;
  2385. #ifdef VMXNET3_RSS
  2386. if (enable_mq)
  2387. num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
  2388. (int)num_online_cpus());
  2389. else
  2390. #endif
  2391. num_rx_queues = 1;
  2392. if (enable_mq)
  2393. num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
  2394. (int)num_online_cpus());
  2395. else
  2396. num_tx_queues = 1;
  2397. netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
  2398. max(num_tx_queues, num_rx_queues));
  2399. printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
  2400. num_tx_queues, num_rx_queues);
  2401. if (!netdev) {
  2402. printk(KERN_ERR "Failed to alloc ethernet device for adapter "
  2403. "%s\n", pci_name(pdev));
  2404. return -ENOMEM;
  2405. }
  2406. pci_set_drvdata(pdev, netdev);
  2407. adapter = netdev_priv(netdev);
  2408. adapter->netdev = netdev;
  2409. adapter->pdev = pdev;
  2410. adapter->shared = pci_alloc_consistent(adapter->pdev,
  2411. sizeof(struct Vmxnet3_DriverShared),
  2412. &adapter->shared_pa);
  2413. if (!adapter->shared) {
  2414. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2415. pci_name(pdev));
  2416. err = -ENOMEM;
  2417. goto err_alloc_shared;
  2418. }
  2419. adapter->num_rx_queues = num_rx_queues;
  2420. adapter->num_tx_queues = num_tx_queues;
  2421. size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
  2422. size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
  2423. adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
  2424. &adapter->queue_desc_pa);
  2425. if (!adapter->tqd_start) {
  2426. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2427. pci_name(pdev));
  2428. err = -ENOMEM;
  2429. goto err_alloc_queue_desc;
  2430. }
  2431. adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
  2432. adapter->num_tx_queues);
  2433. adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
  2434. if (adapter->pm_conf == NULL) {
  2435. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2436. pci_name(pdev));
  2437. err = -ENOMEM;
  2438. goto err_alloc_pm;
  2439. }
  2440. #ifdef VMXNET3_RSS
  2441. adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
  2442. if (adapter->rss_conf == NULL) {
  2443. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2444. pci_name(pdev));
  2445. err = -ENOMEM;
  2446. goto err_alloc_rss;
  2447. }
  2448. #endif /* VMXNET3_RSS */
  2449. err = vmxnet3_alloc_pci_resources(adapter, &dma64);
  2450. if (err < 0)
  2451. goto err_alloc_pci;
  2452. ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
  2453. if (ver & 1) {
  2454. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
  2455. } else {
  2456. printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
  2457. " %s\n", ver, pci_name(pdev));
  2458. err = -EBUSY;
  2459. goto err_ver;
  2460. }
  2461. ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
  2462. if (ver & 1) {
  2463. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
  2464. } else {
  2465. printk(KERN_ERR "Incompatible upt version (0x%x) for "
  2466. "adapter %s\n", ver, pci_name(pdev));
  2467. err = -EBUSY;
  2468. goto err_ver;
  2469. }
  2470. vmxnet3_declare_features(adapter, dma64);
  2471. adapter->dev_number = atomic_read(&devices_found);
  2472. adapter->share_intr = irq_share_mode;
  2473. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
  2474. adapter->num_tx_queues != adapter->num_rx_queues)
  2475. adapter->share_intr = VMXNET3_INTR_DONTSHARE;
  2476. vmxnet3_alloc_intr_resources(adapter);
  2477. #ifdef VMXNET3_RSS
  2478. if (adapter->num_rx_queues > 1 &&
  2479. adapter->intr.type == VMXNET3_IT_MSIX) {
  2480. adapter->rss = true;
  2481. printk(KERN_INFO "RSS is enabled.\n");
  2482. } else {
  2483. adapter->rss = false;
  2484. }
  2485. #endif
  2486. vmxnet3_read_mac_addr(adapter, mac);
  2487. memcpy(netdev->dev_addr, mac, netdev->addr_len);
  2488. netdev->netdev_ops = &vmxnet3_netdev_ops;
  2489. vmxnet3_set_ethtool_ops(netdev);
  2490. netdev->watchdog_timeo = 5 * HZ;
  2491. INIT_WORK(&adapter->work, vmxnet3_reset_work);
  2492. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  2493. int i;
  2494. for (i = 0; i < adapter->num_rx_queues; i++) {
  2495. netif_napi_add(adapter->netdev,
  2496. &adapter->rx_queue[i].napi,
  2497. vmxnet3_poll_rx_only, 64);
  2498. }
  2499. } else {
  2500. netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
  2501. vmxnet3_poll, 64);
  2502. }
  2503. netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
  2504. netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
  2505. SET_NETDEV_DEV(netdev, &pdev->dev);
  2506. err = register_netdev(netdev);
  2507. if (err) {
  2508. printk(KERN_ERR "Failed to register adapter %s\n",
  2509. pci_name(pdev));
  2510. goto err_register;
  2511. }
  2512. set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
  2513. vmxnet3_check_link(adapter, false);
  2514. atomic_inc(&devices_found);
  2515. return 0;
  2516. err_register:
  2517. vmxnet3_free_intr_resources(adapter);
  2518. err_ver:
  2519. vmxnet3_free_pci_resources(adapter);
  2520. err_alloc_pci:
  2521. #ifdef VMXNET3_RSS
  2522. kfree(adapter->rss_conf);
  2523. err_alloc_rss:
  2524. #endif
  2525. kfree(adapter->pm_conf);
  2526. err_alloc_pm:
  2527. pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
  2528. adapter->queue_desc_pa);
  2529. err_alloc_queue_desc:
  2530. pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
  2531. adapter->shared, adapter->shared_pa);
  2532. err_alloc_shared:
  2533. pci_set_drvdata(pdev, NULL);
  2534. free_netdev(netdev);
  2535. return err;
  2536. }
  2537. static void __devexit
  2538. vmxnet3_remove_device(struct pci_dev *pdev)
  2539. {
  2540. struct net_device *netdev = pci_get_drvdata(pdev);
  2541. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2542. int size = 0;
  2543. int num_rx_queues;
  2544. #ifdef VMXNET3_RSS
  2545. if (enable_mq)
  2546. num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
  2547. (int)num_online_cpus());
  2548. else
  2549. #endif
  2550. num_rx_queues = 1;
  2551. cancel_work_sync(&adapter->work);
  2552. unregister_netdev(netdev);
  2553. vmxnet3_free_intr_resources(adapter);
  2554. vmxnet3_free_pci_resources(adapter);
  2555. #ifdef VMXNET3_RSS
  2556. kfree(adapter->rss_conf);
  2557. #endif
  2558. kfree(adapter->pm_conf);
  2559. size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
  2560. size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
  2561. pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
  2562. adapter->queue_desc_pa);
  2563. pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
  2564. adapter->shared, adapter->shared_pa);
  2565. free_netdev(netdev);
  2566. }
  2567. #ifdef CONFIG_PM
  2568. static int
  2569. vmxnet3_suspend(struct device *device)
  2570. {
  2571. struct pci_dev *pdev = to_pci_dev(device);
  2572. struct net_device *netdev = pci_get_drvdata(pdev);
  2573. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2574. struct Vmxnet3_PMConf *pmConf;
  2575. struct ethhdr *ehdr;
  2576. struct arphdr *ahdr;
  2577. u8 *arpreq;
  2578. struct in_device *in_dev;
  2579. struct in_ifaddr *ifa;
  2580. int i = 0;
  2581. if (!netif_running(netdev))
  2582. return 0;
  2583. vmxnet3_disable_all_intrs(adapter);
  2584. vmxnet3_free_irqs(adapter);
  2585. vmxnet3_free_intr_resources(adapter);
  2586. netif_device_detach(netdev);
  2587. netif_tx_stop_all_queues(netdev);
  2588. /* Create wake-up filters. */
  2589. pmConf = adapter->pm_conf;
  2590. memset(pmConf, 0, sizeof(*pmConf));
  2591. if (adapter->wol & WAKE_UCAST) {
  2592. pmConf->filters[i].patternSize = ETH_ALEN;
  2593. pmConf->filters[i].maskSize = 1;
  2594. memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
  2595. pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
  2596. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
  2597. i++;
  2598. }
  2599. if (adapter->wol & WAKE_ARP) {
  2600. in_dev = in_dev_get(netdev);
  2601. if (!in_dev)
  2602. goto skip_arp;
  2603. ifa = (struct in_ifaddr *)in_dev->ifa_list;
  2604. if (!ifa)
  2605. goto skip_arp;
  2606. pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
  2607. sizeof(struct arphdr) + /* ARP header */
  2608. 2 * ETH_ALEN + /* 2 Ethernet addresses*/
  2609. 2 * sizeof(u32); /*2 IPv4 addresses */
  2610. pmConf->filters[i].maskSize =
  2611. (pmConf->filters[i].patternSize - 1) / 8 + 1;
  2612. /* ETH_P_ARP in Ethernet header. */
  2613. ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
  2614. ehdr->h_proto = htons(ETH_P_ARP);
  2615. /* ARPOP_REQUEST in ARP header. */
  2616. ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
  2617. ahdr->ar_op = htons(ARPOP_REQUEST);
  2618. arpreq = (u8 *)(ahdr + 1);
  2619. /* The Unicast IPv4 address in 'tip' field. */
  2620. arpreq += 2 * ETH_ALEN + sizeof(u32);
  2621. *(u32 *)arpreq = ifa->ifa_address;
  2622. /* The mask for the relevant bits. */
  2623. pmConf->filters[i].mask[0] = 0x00;
  2624. pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
  2625. pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
  2626. pmConf->filters[i].mask[3] = 0x00;
  2627. pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
  2628. pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
  2629. in_dev_put(in_dev);
  2630. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
  2631. i++;
  2632. }
  2633. skip_arp:
  2634. if (adapter->wol & WAKE_MAGIC)
  2635. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
  2636. pmConf->numFilters = i;
  2637. adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
  2638. adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
  2639. *pmConf));
  2640. adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
  2641. pmConf));
  2642. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2643. VMXNET3_CMD_UPDATE_PMCFG);
  2644. pci_save_state(pdev);
  2645. pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
  2646. adapter->wol);
  2647. pci_disable_device(pdev);
  2648. pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
  2649. return 0;
  2650. }
  2651. static int
  2652. vmxnet3_resume(struct device *device)
  2653. {
  2654. int err;
  2655. struct pci_dev *pdev = to_pci_dev(device);
  2656. struct net_device *netdev = pci_get_drvdata(pdev);
  2657. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2658. struct Vmxnet3_PMConf *pmConf;
  2659. if (!netif_running(netdev))
  2660. return 0;
  2661. /* Destroy wake-up filters. */
  2662. pmConf = adapter->pm_conf;
  2663. memset(pmConf, 0, sizeof(*pmConf));
  2664. adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
  2665. adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
  2666. *pmConf));
  2667. adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
  2668. pmConf));
  2669. netif_device_attach(netdev);
  2670. pci_set_power_state(pdev, PCI_D0);
  2671. pci_restore_state(pdev);
  2672. err = pci_enable_device_mem(pdev);
  2673. if (err != 0)
  2674. return err;
  2675. pci_enable_wake(pdev, PCI_D0, 0);
  2676. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2677. VMXNET3_CMD_UPDATE_PMCFG);
  2678. vmxnet3_alloc_intr_resources(adapter);
  2679. vmxnet3_request_irqs(adapter);
  2680. vmxnet3_enable_all_intrs(adapter);
  2681. return 0;
  2682. }
  2683. static const struct dev_pm_ops vmxnet3_pm_ops = {
  2684. .suspend = vmxnet3_suspend,
  2685. .resume = vmxnet3_resume,
  2686. };
  2687. #endif
  2688. static struct pci_driver vmxnet3_driver = {
  2689. .name = vmxnet3_driver_name,
  2690. .id_table = vmxnet3_pciid_table,
  2691. .probe = vmxnet3_probe_device,
  2692. .remove = __devexit_p(vmxnet3_remove_device),
  2693. #ifdef CONFIG_PM
  2694. .driver.pm = &vmxnet3_pm_ops,
  2695. #endif
  2696. };
  2697. static int __init
  2698. vmxnet3_init_module(void)
  2699. {
  2700. printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
  2701. VMXNET3_DRIVER_VERSION_REPORT);
  2702. return pci_register_driver(&vmxnet3_driver);
  2703. }
  2704. module_init(vmxnet3_init_module);
  2705. static void
  2706. vmxnet3_exit_module(void)
  2707. {
  2708. pci_unregister_driver(&vmxnet3_driver);
  2709. }
  2710. module_exit(vmxnet3_exit_module);
  2711. MODULE_AUTHOR("VMware, Inc.");
  2712. MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
  2713. MODULE_LICENSE("GPL v2");
  2714. MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);