lcd.c 35 KB

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  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #include <linux/via-core.h>
  19. #include <linux/via_i2c.h>
  20. #include "global.h"
  21. #define viafb_compact_res(x, y) (((x)<<16)|(y))
  22. /* CLE266 Software Power Sequence */
  23. /* {Mask}, {Data}, {Delay} */
  24. static const int PowerSequenceOn[3][3] = {
  25. {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01}
  26. };
  27. static const int PowerSequenceOff[3][3] = {
  28. {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01}
  29. };
  30. static struct _lcd_scaling_factor lcd_scaling_factor = {
  31. /* LCD Horizontal Scaling Factor Register */
  32. {LCD_HOR_SCALING_FACTOR_REG_NUM,
  33. {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
  34. /* LCD Vertical Scaling Factor Register */
  35. {LCD_VER_SCALING_FACTOR_REG_NUM,
  36. {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
  37. };
  38. static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
  39. /* LCD Horizontal Scaling Factor Register */
  40. {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
  41. /* LCD Vertical Scaling Factor Register */
  42. {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
  43. };
  44. static int check_lvds_chip(int device_id_subaddr, int device_id);
  45. static bool lvds_identify_integratedlvds(void);
  46. static void __devinit fp_id_to_vindex(int panel_id);
  47. static int lvds_register_read(int index);
  48. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  49. int panel_vres);
  50. static void via_pitch_alignment_patch_lcd(
  51. struct lvds_setting_information *plvds_setting_info,
  52. struct lvds_chip_information
  53. *plvds_chip_info);
  54. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  55. *plvds_setting_info,
  56. struct lvds_chip_information *plvds_chip_info);
  57. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  58. *plvds_setting_info,
  59. struct lvds_chip_information *plvds_chip_info);
  60. static void lcd_patch_skew(struct lvds_setting_information
  61. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
  62. static void integrated_lvds_disable(struct lvds_setting_information
  63. *plvds_setting_info,
  64. struct lvds_chip_information *plvds_chip_info);
  65. static void integrated_lvds_enable(struct lvds_setting_information
  66. *plvds_setting_info,
  67. struct lvds_chip_information *plvds_chip_info);
  68. static void lcd_powersequence_off(void);
  69. static void lcd_powersequence_on(void);
  70. static void fill_lcd_format(void);
  71. static void check_diport_of_integrated_lvds(
  72. struct lvds_chip_information *plvds_chip_info,
  73. struct lvds_setting_information
  74. *plvds_setting_info);
  75. static struct display_timing lcd_centering_timging(struct display_timing
  76. mode_crt_reg,
  77. struct display_timing panel_crt_reg);
  78. static int check_lvds_chip(int device_id_subaddr, int device_id)
  79. {
  80. if (lvds_register_read(device_id_subaddr) == device_id)
  81. return OK;
  82. else
  83. return FAIL;
  84. }
  85. void __devinit viafb_init_lcd_size(void)
  86. {
  87. DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
  88. fp_id_to_vindex(viafb_lcd_panel_id);
  89. viaparinfo->lvds_setting_info2->lcd_panel_id =
  90. viaparinfo->lvds_setting_info->lcd_panel_id;
  91. viaparinfo->lvds_setting_info2->lcd_panel_hres =
  92. viaparinfo->lvds_setting_info->lcd_panel_hres;
  93. viaparinfo->lvds_setting_info2->lcd_panel_vres =
  94. viaparinfo->lvds_setting_info->lcd_panel_vres;
  95. viaparinfo->lvds_setting_info2->device_lcd_dualedge =
  96. viaparinfo->lvds_setting_info->device_lcd_dualedge;
  97. viaparinfo->lvds_setting_info2->LCDDithering =
  98. viaparinfo->lvds_setting_info->LCDDithering;
  99. }
  100. static bool lvds_identify_integratedlvds(void)
  101. {
  102. if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
  103. /* Two dual channel LCD (Internal LVDS + External LVDS): */
  104. /* If we have an external LVDS, such as VT1636, we should
  105. have its chip ID already. */
  106. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  107. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  108. INTEGRATED_LVDS;
  109. DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
  110. "(Internal LVDS + External LVDS)\n");
  111. } else {
  112. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  113. INTEGRATED_LVDS;
  114. DEBUG_MSG(KERN_INFO "Not found external LVDS, "
  115. "so can't support two dual channel LVDS!\n");
  116. }
  117. } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
  118. /* Two single channel LCD (Internal LVDS + Internal LVDS): */
  119. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  120. INTEGRATED_LVDS;
  121. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  122. INTEGRATED_LVDS;
  123. DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
  124. "(Internal LVDS + Internal LVDS)\n");
  125. } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
  126. /* If we have found external LVDS, just use it,
  127. otherwise, we will use internal LVDS as default. */
  128. if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  129. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  130. INTEGRATED_LVDS;
  131. DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
  132. }
  133. } else {
  134. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  135. NON_LVDS_TRANSMITTER;
  136. DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
  137. return false;
  138. }
  139. return true;
  140. }
  141. int __devinit viafb_lvds_trasmitter_identify(void)
  142. {
  143. if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
  144. viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
  145. DEBUG_MSG(KERN_INFO
  146. "Found VIA VT1636 LVDS on port i2c 0x31\n");
  147. } else {
  148. if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
  149. viaparinfo->chip_info->lvds_chip_info.i2c_port =
  150. VIA_PORT_2C;
  151. DEBUG_MSG(KERN_INFO
  152. "Found VIA VT1636 LVDS on port gpio 0x2c\n");
  153. }
  154. }
  155. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
  156. lvds_identify_integratedlvds();
  157. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  158. return true;
  159. /* Check for VT1631: */
  160. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
  161. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  162. VT1631_LVDS_I2C_ADDR;
  163. if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
  164. DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
  165. DEBUG_MSG(KERN_INFO "\n %2d",
  166. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  167. DEBUG_MSG(KERN_INFO "\n %2d",
  168. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  169. return OK;
  170. }
  171. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  172. NON_LVDS_TRANSMITTER;
  173. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  174. VT1631_LVDS_I2C_ADDR;
  175. return FAIL;
  176. }
  177. static void __devinit fp_id_to_vindex(int panel_id)
  178. {
  179. DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
  180. if (panel_id > LCD_PANEL_ID_MAXIMUM)
  181. viafb_lcd_panel_id = panel_id =
  182. viafb_read_reg(VIACR, CR3F) & 0x0F;
  183. switch (panel_id) {
  184. case 0x0:
  185. viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
  186. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  187. viaparinfo->lvds_setting_info->lcd_panel_id =
  188. LCD_PANEL_ID0_640X480;
  189. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  190. viaparinfo->lvds_setting_info->LCDDithering = 1;
  191. break;
  192. case 0x1:
  193. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  194. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  195. viaparinfo->lvds_setting_info->lcd_panel_id =
  196. LCD_PANEL_ID1_800X600;
  197. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  198. viaparinfo->lvds_setting_info->LCDDithering = 1;
  199. break;
  200. case 0x2:
  201. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  202. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  203. viaparinfo->lvds_setting_info->lcd_panel_id =
  204. LCD_PANEL_ID2_1024X768;
  205. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  206. viaparinfo->lvds_setting_info->LCDDithering = 1;
  207. break;
  208. case 0x3:
  209. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  210. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  211. viaparinfo->lvds_setting_info->lcd_panel_id =
  212. LCD_PANEL_ID3_1280X768;
  213. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  214. viaparinfo->lvds_setting_info->LCDDithering = 1;
  215. break;
  216. case 0x4:
  217. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  218. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  219. viaparinfo->lvds_setting_info->lcd_panel_id =
  220. LCD_PANEL_ID4_1280X1024;
  221. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  222. viaparinfo->lvds_setting_info->LCDDithering = 1;
  223. break;
  224. case 0x5:
  225. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  226. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  227. viaparinfo->lvds_setting_info->lcd_panel_id =
  228. LCD_PANEL_ID5_1400X1050;
  229. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  230. viaparinfo->lvds_setting_info->LCDDithering = 1;
  231. break;
  232. case 0x6:
  233. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  234. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  235. viaparinfo->lvds_setting_info->lcd_panel_id =
  236. LCD_PANEL_ID6_1600X1200;
  237. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  238. viaparinfo->lvds_setting_info->LCDDithering = 1;
  239. break;
  240. case 0x8:
  241. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  242. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  243. viaparinfo->lvds_setting_info->lcd_panel_id =
  244. LCD_PANEL_IDA_800X480;
  245. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  246. viaparinfo->lvds_setting_info->LCDDithering = 1;
  247. break;
  248. case 0x9:
  249. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  250. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  251. viaparinfo->lvds_setting_info->lcd_panel_id =
  252. LCD_PANEL_ID2_1024X768;
  253. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  254. viaparinfo->lvds_setting_info->LCDDithering = 1;
  255. break;
  256. case 0xA:
  257. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  258. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  259. viaparinfo->lvds_setting_info->lcd_panel_id =
  260. LCD_PANEL_ID2_1024X768;
  261. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  262. viaparinfo->lvds_setting_info->LCDDithering = 0;
  263. break;
  264. case 0xB:
  265. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  266. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  267. viaparinfo->lvds_setting_info->lcd_panel_id =
  268. LCD_PANEL_ID2_1024X768;
  269. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  270. viaparinfo->lvds_setting_info->LCDDithering = 0;
  271. break;
  272. case 0xC:
  273. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  274. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  275. viaparinfo->lvds_setting_info->lcd_panel_id =
  276. LCD_PANEL_ID3_1280X768;
  277. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  278. viaparinfo->lvds_setting_info->LCDDithering = 0;
  279. break;
  280. case 0xD:
  281. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  282. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  283. viaparinfo->lvds_setting_info->lcd_panel_id =
  284. LCD_PANEL_ID4_1280X1024;
  285. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  286. viaparinfo->lvds_setting_info->LCDDithering = 0;
  287. break;
  288. case 0xE:
  289. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  290. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  291. viaparinfo->lvds_setting_info->lcd_panel_id =
  292. LCD_PANEL_ID5_1400X1050;
  293. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  294. viaparinfo->lvds_setting_info->LCDDithering = 0;
  295. break;
  296. case 0xF:
  297. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  298. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  299. viaparinfo->lvds_setting_info->lcd_panel_id =
  300. LCD_PANEL_ID6_1600X1200;
  301. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  302. viaparinfo->lvds_setting_info->LCDDithering = 0;
  303. break;
  304. case 0x10:
  305. viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
  306. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  307. viaparinfo->lvds_setting_info->lcd_panel_id =
  308. LCD_PANEL_ID7_1366X768;
  309. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  310. viaparinfo->lvds_setting_info->LCDDithering = 0;
  311. break;
  312. case 0x11:
  313. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  314. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  315. viaparinfo->lvds_setting_info->lcd_panel_id =
  316. LCD_PANEL_ID8_1024X600;
  317. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  318. viaparinfo->lvds_setting_info->LCDDithering = 1;
  319. break;
  320. case 0x12:
  321. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  322. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  323. viaparinfo->lvds_setting_info->lcd_panel_id =
  324. LCD_PANEL_ID3_1280X768;
  325. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  326. viaparinfo->lvds_setting_info->LCDDithering = 1;
  327. break;
  328. case 0x13:
  329. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  330. viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
  331. viaparinfo->lvds_setting_info->lcd_panel_id =
  332. LCD_PANEL_ID9_1280X800;
  333. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  334. viaparinfo->lvds_setting_info->LCDDithering = 1;
  335. break;
  336. case 0x14:
  337. viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
  338. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  339. viaparinfo->lvds_setting_info->lcd_panel_id =
  340. LCD_PANEL_IDB_1360X768;
  341. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  342. viaparinfo->lvds_setting_info->LCDDithering = 0;
  343. break;
  344. case 0x15:
  345. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  346. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  347. viaparinfo->lvds_setting_info->lcd_panel_id =
  348. LCD_PANEL_ID3_1280X768;
  349. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  350. viaparinfo->lvds_setting_info->LCDDithering = 0;
  351. break;
  352. case 0x16:
  353. viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
  354. viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
  355. viaparinfo->lvds_setting_info->lcd_panel_id =
  356. LCD_PANEL_IDC_480X640;
  357. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  358. viaparinfo->lvds_setting_info->LCDDithering = 1;
  359. break;
  360. case 0x17:
  361. /* OLPC XO-1.5 panel */
  362. viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
  363. viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
  364. viaparinfo->lvds_setting_info->lcd_panel_id =
  365. LCD_PANEL_IDD_1200X900;
  366. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  367. viaparinfo->lvds_setting_info->LCDDithering = 0;
  368. break;
  369. default:
  370. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  371. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  372. viaparinfo->lvds_setting_info->lcd_panel_id =
  373. LCD_PANEL_ID1_800X600;
  374. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  375. viaparinfo->lvds_setting_info->LCDDithering = 1;
  376. }
  377. }
  378. static int lvds_register_read(int index)
  379. {
  380. u8 data;
  381. viafb_i2c_readbyte(VIA_PORT_2C,
  382. (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
  383. (u8) index, &data);
  384. return data;
  385. }
  386. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  387. int panel_vres)
  388. {
  389. int reg_value = 0;
  390. int viafb_load_reg_num;
  391. struct io_register *reg = NULL;
  392. DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
  393. /* LCD Scaling Enable */
  394. viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
  395. /* Check if expansion for horizontal */
  396. if (set_hres < panel_hres) {
  397. /* Load Horizontal Scaling Factor */
  398. switch (viaparinfo->chip_info->gfx_chip_name) {
  399. case UNICHROME_CLE266:
  400. case UNICHROME_K400:
  401. reg_value =
  402. CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  403. viafb_load_reg_num =
  404. lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
  405. reg_num;
  406. reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
  407. viafb_load_reg(reg_value,
  408. viafb_load_reg_num, reg, VIACR);
  409. break;
  410. case UNICHROME_K800:
  411. case UNICHROME_PM800:
  412. case UNICHROME_CN700:
  413. case UNICHROME_CX700:
  414. case UNICHROME_K8M890:
  415. case UNICHROME_P4M890:
  416. case UNICHROME_P4M900:
  417. case UNICHROME_CN750:
  418. case UNICHROME_VX800:
  419. case UNICHROME_VX855:
  420. case UNICHROME_VX900:
  421. reg_value =
  422. K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  423. /* Horizontal scaling enabled */
  424. viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
  425. viafb_load_reg_num =
  426. lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
  427. reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
  428. viafb_load_reg(reg_value,
  429. viafb_load_reg_num, reg, VIACR);
  430. break;
  431. }
  432. DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
  433. } else {
  434. /* Horizontal scaling disabled */
  435. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
  436. }
  437. /* Check if expansion for vertical */
  438. if (set_vres < panel_vres) {
  439. /* Load Vertical Scaling Factor */
  440. switch (viaparinfo->chip_info->gfx_chip_name) {
  441. case UNICHROME_CLE266:
  442. case UNICHROME_K400:
  443. reg_value =
  444. CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  445. viafb_load_reg_num =
  446. lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
  447. reg_num;
  448. reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
  449. viafb_load_reg(reg_value,
  450. viafb_load_reg_num, reg, VIACR);
  451. break;
  452. case UNICHROME_K800:
  453. case UNICHROME_PM800:
  454. case UNICHROME_CN700:
  455. case UNICHROME_CX700:
  456. case UNICHROME_K8M890:
  457. case UNICHROME_P4M890:
  458. case UNICHROME_P4M900:
  459. case UNICHROME_CN750:
  460. case UNICHROME_VX800:
  461. case UNICHROME_VX855:
  462. case UNICHROME_VX900:
  463. reg_value =
  464. K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  465. /* Vertical scaling enabled */
  466. viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
  467. viafb_load_reg_num =
  468. lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
  469. reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
  470. viafb_load_reg(reg_value,
  471. viafb_load_reg_num, reg, VIACR);
  472. break;
  473. }
  474. DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
  475. } else {
  476. /* Vertical scaling disabled */
  477. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
  478. }
  479. }
  480. static void via_pitch_alignment_patch_lcd(
  481. struct lvds_setting_information *plvds_setting_info,
  482. struct lvds_chip_information
  483. *plvds_chip_info)
  484. {
  485. unsigned char cr13, cr35, cr65, cr66, cr67;
  486. unsigned long dwScreenPitch = 0;
  487. unsigned long dwPitch;
  488. dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
  489. if (dwPitch & 0x1F) {
  490. dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
  491. if (plvds_setting_info->iga_path == IGA2) {
  492. if (plvds_setting_info->bpp > 8) {
  493. cr66 = (unsigned char)(dwScreenPitch & 0xFF);
  494. viafb_write_reg(CR66, VIACR, cr66);
  495. cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
  496. cr67 |=
  497. (unsigned
  498. char)((dwScreenPitch & 0x300) >> 8);
  499. viafb_write_reg(CR67, VIACR, cr67);
  500. }
  501. /* Fetch Count */
  502. cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
  503. cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
  504. viafb_write_reg(CR67, VIACR, cr67);
  505. cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
  506. cr65 += 2;
  507. viafb_write_reg(CR65, VIACR, cr65);
  508. } else {
  509. if (plvds_setting_info->bpp > 8) {
  510. cr13 = (unsigned char)(dwScreenPitch & 0xFF);
  511. viafb_write_reg(CR13, VIACR, cr13);
  512. cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
  513. cr35 |=
  514. (unsigned
  515. char)((dwScreenPitch & 0x700) >> 3);
  516. viafb_write_reg(CR35, VIACR, cr35);
  517. }
  518. }
  519. }
  520. }
  521. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  522. *plvds_setting_info,
  523. struct lvds_chip_information *plvds_chip_info)
  524. {
  525. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  526. switch (viaparinfo->chip_info->gfx_chip_name) {
  527. case UNICHROME_P4M900:
  528. viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
  529. plvds_chip_info);
  530. break;
  531. case UNICHROME_P4M890:
  532. viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
  533. plvds_chip_info);
  534. break;
  535. }
  536. }
  537. }
  538. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  539. *plvds_setting_info,
  540. struct lvds_chip_information *plvds_chip_info)
  541. {
  542. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  543. switch (viaparinfo->chip_info->gfx_chip_name) {
  544. case UNICHROME_CX700:
  545. viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
  546. plvds_chip_info);
  547. break;
  548. }
  549. }
  550. }
  551. static void lcd_patch_skew(struct lvds_setting_information
  552. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
  553. {
  554. DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
  555. switch (plvds_chip_info->output_interface) {
  556. case INTERFACE_DVP0:
  557. lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
  558. break;
  559. case INTERFACE_DVP1:
  560. lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
  561. break;
  562. case INTERFACE_DFP_LOW:
  563. if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
  564. viafb_write_reg_mask(CR99, VIACR, 0x08,
  565. BIT0 + BIT1 + BIT2 + BIT3);
  566. }
  567. break;
  568. }
  569. }
  570. /* LCD Set Mode */
  571. void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
  572. struct lvds_setting_information *plvds_setting_info,
  573. struct lvds_chip_information *plvds_chip_info)
  574. {
  575. int set_iga = plvds_setting_info->iga_path;
  576. int mode_bpp = plvds_setting_info->bpp;
  577. int set_hres = plvds_setting_info->h_active;
  578. int set_vres = plvds_setting_info->v_active;
  579. int panel_hres = plvds_setting_info->lcd_panel_hres;
  580. int panel_vres = plvds_setting_info->lcd_panel_vres;
  581. u32 pll_D_N;
  582. struct display_timing mode_crt_reg, panel_crt_reg;
  583. struct crt_mode_table *panel_crt_table = NULL;
  584. struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
  585. panel_vres);
  586. DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
  587. /* Get mode table */
  588. mode_crt_reg = mode_crt_table->crtc;
  589. /* Get panel table Pointer */
  590. panel_crt_table = vmode_tbl->crtc;
  591. panel_crt_reg = panel_crt_table->crtc;
  592. DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
  593. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
  594. viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
  595. plvds_setting_info->vclk = panel_crt_table->clk;
  596. if (set_iga == IGA1) {
  597. /* IGA1 doesn't have LCD scaling, so set it as centering. */
  598. viafb_load_crtc_timing(lcd_centering_timging
  599. (mode_crt_reg, panel_crt_reg), IGA1);
  600. } else {
  601. /* Expansion */
  602. if (plvds_setting_info->display_method == LCD_EXPANDSION
  603. && (set_hres < panel_hres || set_vres < panel_vres)) {
  604. /* expansion timing IGA2 loaded panel set timing*/
  605. viafb_load_crtc_timing(panel_crt_reg, IGA2);
  606. DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
  607. load_lcd_scaling(set_hres, set_vres, panel_hres,
  608. panel_vres);
  609. DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
  610. } else { /* Centering */
  611. /* centering timing IGA2 always loaded panel
  612. and mode releative timing */
  613. viafb_load_crtc_timing(lcd_centering_timging
  614. (mode_crt_reg, panel_crt_reg), IGA2);
  615. viafb_write_reg_mask(CR79, VIACR, 0x00,
  616. BIT0 + BIT1 + BIT2);
  617. /* LCD scaling disabled */
  618. }
  619. }
  620. /* Fetch count for IGA2 only */
  621. viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
  622. if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
  623. && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
  624. viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
  625. fill_lcd_format();
  626. pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
  627. DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
  628. viafb_set_vclock(pll_D_N, set_iga);
  629. lcd_patch_skew(plvds_setting_info, plvds_chip_info);
  630. /* If K8M800, enable LCD Prefetch Mode. */
  631. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
  632. || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
  633. viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
  634. /* Patch for non 32bit alignment mode */
  635. via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
  636. }
  637. static void integrated_lvds_disable(struct lvds_setting_information
  638. *plvds_setting_info,
  639. struct lvds_chip_information *plvds_chip_info)
  640. {
  641. bool turn_off_first_powersequence = false;
  642. bool turn_off_second_powersequence = false;
  643. if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
  644. turn_off_first_powersequence = true;
  645. if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
  646. turn_off_first_powersequence = true;
  647. if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
  648. turn_off_second_powersequence = true;
  649. if (turn_off_second_powersequence) {
  650. /* Use second power sequence control: */
  651. /* Turn off power sequence. */
  652. viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
  653. /* Turn off back light. */
  654. viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
  655. }
  656. if (turn_off_first_powersequence) {
  657. /* Use first power sequence control: */
  658. /* Turn off power sequence. */
  659. viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
  660. /* Turn off back light. */
  661. viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
  662. }
  663. /* Power off LVDS channel. */
  664. switch (plvds_chip_info->output_interface) {
  665. case INTERFACE_LVDS0:
  666. {
  667. viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
  668. break;
  669. }
  670. case INTERFACE_LVDS1:
  671. {
  672. viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
  673. break;
  674. }
  675. case INTERFACE_LVDS0LVDS1:
  676. {
  677. viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
  678. break;
  679. }
  680. }
  681. }
  682. static void integrated_lvds_enable(struct lvds_setting_information
  683. *plvds_setting_info,
  684. struct lvds_chip_information *plvds_chip_info)
  685. {
  686. DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
  687. plvds_chip_info->output_interface);
  688. if (plvds_setting_info->lcd_mode == LCD_SPWG)
  689. viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
  690. else
  691. viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
  692. switch (plvds_chip_info->output_interface) {
  693. case INTERFACE_LVDS0LVDS1:
  694. case INTERFACE_LVDS0:
  695. /* Use first power sequence control: */
  696. /* Use hardware control power sequence. */
  697. viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
  698. /* Turn on back light. */
  699. viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
  700. /* Turn on hardware power sequence. */
  701. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  702. break;
  703. case INTERFACE_LVDS1:
  704. /* Use second power sequence control: */
  705. /* Use hardware control power sequence. */
  706. viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
  707. /* Turn on back light. */
  708. viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
  709. /* Turn on hardware power sequence. */
  710. viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
  711. break;
  712. }
  713. /* Power on LVDS channel. */
  714. switch (plvds_chip_info->output_interface) {
  715. case INTERFACE_LVDS0:
  716. {
  717. viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
  718. break;
  719. }
  720. case INTERFACE_LVDS1:
  721. {
  722. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
  723. break;
  724. }
  725. case INTERFACE_LVDS0LVDS1:
  726. {
  727. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
  728. break;
  729. }
  730. }
  731. }
  732. void viafb_lcd_disable(void)
  733. {
  734. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  735. lcd_powersequence_off();
  736. /* DI1 pad off */
  737. viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
  738. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  739. if (viafb_LCD2_ON
  740. && (INTEGRATED_LVDS ==
  741. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  742. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  743. &viaparinfo->chip_info->lvds_chip_info2);
  744. if (INTEGRATED_LVDS ==
  745. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  746. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  747. &viaparinfo->chip_info->lvds_chip_info);
  748. if (VT1636_LVDS == viaparinfo->chip_info->
  749. lvds_chip_info.lvds_chip_name)
  750. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  751. &viaparinfo->chip_info->lvds_chip_info);
  752. } else if (VT1636_LVDS ==
  753. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  754. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  755. &viaparinfo->chip_info->lvds_chip_info);
  756. } else {
  757. /* Backlight off */
  758. viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
  759. /* 24 bit DI data paht off */
  760. viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
  761. }
  762. /* Disable expansion bit */
  763. viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
  764. /* Simultaneout disabled */
  765. viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
  766. }
  767. static void set_lcd_output_path(int set_iga, int output_interface)
  768. {
  769. switch (output_interface) {
  770. case INTERFACE_DFP:
  771. if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
  772. || (UNICHROME_P4M890 ==
  773. viaparinfo->chip_info->gfx_chip_name))
  774. viafb_write_reg_mask(CR97, VIACR, 0x84,
  775. BIT7 + BIT2 + BIT1 + BIT0);
  776. case INTERFACE_DVP0:
  777. case INTERFACE_DVP1:
  778. case INTERFACE_DFP_HIGH:
  779. case INTERFACE_DFP_LOW:
  780. if (set_iga == IGA2)
  781. viafb_write_reg(CR91, VIACR, 0x00);
  782. break;
  783. }
  784. }
  785. void viafb_lcd_enable(void)
  786. {
  787. viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
  788. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  789. set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path,
  790. viaparinfo->chip_info->lvds_chip_info.output_interface);
  791. if (viafb_LCD2_ON)
  792. set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path,
  793. viaparinfo->chip_info->
  794. lvds_chip_info2.output_interface);
  795. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  796. /* DI1 pad on */
  797. viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
  798. lcd_powersequence_on();
  799. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  800. if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
  801. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  802. integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
  803. &viaparinfo->chip_info->lvds_chip_info2);
  804. if (INTEGRATED_LVDS ==
  805. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  806. integrated_lvds_enable(viaparinfo->lvds_setting_info,
  807. &viaparinfo->chip_info->lvds_chip_info);
  808. if (VT1636_LVDS == viaparinfo->chip_info->
  809. lvds_chip_info.lvds_chip_name)
  810. viafb_enable_lvds_vt1636(viaparinfo->
  811. lvds_setting_info, &viaparinfo->chip_info->
  812. lvds_chip_info);
  813. } else if (VT1636_LVDS ==
  814. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  815. viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
  816. &viaparinfo->chip_info->lvds_chip_info);
  817. } else {
  818. /* Backlight on */
  819. viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
  820. /* 24 bit DI data paht on */
  821. viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
  822. /* LCD enabled */
  823. viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
  824. }
  825. }
  826. static void lcd_powersequence_off(void)
  827. {
  828. int i, mask, data;
  829. /* Software control power sequence */
  830. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  831. for (i = 0; i < 3; i++) {
  832. mask = PowerSequenceOff[0][i];
  833. data = PowerSequenceOff[1][i] & mask;
  834. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  835. udelay(PowerSequenceOff[2][i]);
  836. }
  837. /* Disable LCD */
  838. viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
  839. }
  840. static void lcd_powersequence_on(void)
  841. {
  842. int i, mask, data;
  843. /* Software control power sequence */
  844. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  845. /* Enable LCD */
  846. viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
  847. for (i = 0; i < 3; i++) {
  848. mask = PowerSequenceOn[0][i];
  849. data = PowerSequenceOn[1][i] & mask;
  850. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  851. udelay(PowerSequenceOn[2][i]);
  852. }
  853. udelay(1);
  854. }
  855. static void fill_lcd_format(void)
  856. {
  857. u8 bdithering = 0, bdual = 0;
  858. if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
  859. bdual = BIT4;
  860. if (viaparinfo->lvds_setting_info->LCDDithering)
  861. bdithering = BIT0;
  862. /* Dual & Dithering */
  863. viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
  864. }
  865. static void check_diport_of_integrated_lvds(
  866. struct lvds_chip_information *plvds_chip_info,
  867. struct lvds_setting_information
  868. *plvds_setting_info)
  869. {
  870. /* Determine LCD DI Port by hardware layout. */
  871. switch (viafb_display_hardware_layout) {
  872. case HW_LAYOUT_LCD_ONLY:
  873. {
  874. if (plvds_setting_info->device_lcd_dualedge) {
  875. plvds_chip_info->output_interface =
  876. INTERFACE_LVDS0LVDS1;
  877. } else {
  878. plvds_chip_info->output_interface =
  879. INTERFACE_LVDS0;
  880. }
  881. break;
  882. }
  883. case HW_LAYOUT_DVI_ONLY:
  884. {
  885. plvds_chip_info->output_interface = INTERFACE_NONE;
  886. break;
  887. }
  888. case HW_LAYOUT_LCD1_LCD2:
  889. case HW_LAYOUT_LCD_EXTERNAL_LCD2:
  890. {
  891. plvds_chip_info->output_interface =
  892. INTERFACE_LVDS0LVDS1;
  893. break;
  894. }
  895. case HW_LAYOUT_LCD_DVI:
  896. {
  897. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  898. break;
  899. }
  900. default:
  901. {
  902. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  903. break;
  904. }
  905. }
  906. DEBUG_MSG(KERN_INFO
  907. "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
  908. viafb_display_hardware_layout,
  909. plvds_chip_info->output_interface);
  910. }
  911. void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information
  912. *plvds_chip_info,
  913. struct lvds_setting_information
  914. *plvds_setting_info)
  915. {
  916. if (INTERFACE_NONE != plvds_chip_info->output_interface) {
  917. /*Do nothing, lcd port is specified by module parameter */
  918. return;
  919. }
  920. switch (plvds_chip_info->lvds_chip_name) {
  921. case VT1636_LVDS:
  922. switch (viaparinfo->chip_info->gfx_chip_name) {
  923. case UNICHROME_CX700:
  924. plvds_chip_info->output_interface = INTERFACE_DVP1;
  925. break;
  926. case UNICHROME_CN700:
  927. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  928. break;
  929. default:
  930. plvds_chip_info->output_interface = INTERFACE_DVP0;
  931. break;
  932. }
  933. break;
  934. case INTEGRATED_LVDS:
  935. check_diport_of_integrated_lvds(plvds_chip_info,
  936. plvds_setting_info);
  937. break;
  938. default:
  939. switch (viaparinfo->chip_info->gfx_chip_name) {
  940. case UNICHROME_K8M890:
  941. case UNICHROME_P4M900:
  942. case UNICHROME_P4M890:
  943. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  944. break;
  945. default:
  946. plvds_chip_info->output_interface = INTERFACE_DFP;
  947. break;
  948. }
  949. break;
  950. }
  951. }
  952. static struct display_timing lcd_centering_timging(struct display_timing
  953. mode_crt_reg,
  954. struct display_timing panel_crt_reg)
  955. {
  956. struct display_timing crt_reg;
  957. crt_reg.hor_total = panel_crt_reg.hor_total;
  958. crt_reg.hor_addr = mode_crt_reg.hor_addr;
  959. crt_reg.hor_blank_start =
  960. (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
  961. crt_reg.hor_addr;
  962. crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
  963. crt_reg.hor_sync_start =
  964. (panel_crt_reg.hor_sync_start -
  965. panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
  966. crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
  967. crt_reg.ver_total = panel_crt_reg.ver_total;
  968. crt_reg.ver_addr = mode_crt_reg.ver_addr;
  969. crt_reg.ver_blank_start =
  970. (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
  971. crt_reg.ver_addr;
  972. crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
  973. crt_reg.ver_sync_start =
  974. (panel_crt_reg.ver_sync_start -
  975. panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
  976. crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
  977. return crt_reg;
  978. }
  979. bool viafb_lcd_get_mobile_state(bool *mobile)
  980. {
  981. unsigned char __iomem *romptr, *tableptr, *biosptr;
  982. u8 core_base;
  983. /* Rom address */
  984. const u32 romaddr = 0x000C0000;
  985. u16 start_pattern;
  986. biosptr = ioremap(romaddr, 0x10000);
  987. start_pattern = readw(biosptr);
  988. /* Compare pattern */
  989. if (start_pattern == 0xAA55) {
  990. /* Get the start of Table */
  991. /* 0x1B means BIOS offset position */
  992. romptr = biosptr + 0x1B;
  993. tableptr = biosptr + readw(romptr);
  994. /* Get the start of biosver structure */
  995. /* 18 means BIOS version position. */
  996. romptr = tableptr + 18;
  997. romptr = biosptr + readw(romptr);
  998. /* The offset should be 44, but the
  999. actual image is less three char. */
  1000. /* pRom += 44; */
  1001. romptr += 41;
  1002. core_base = readb(romptr);
  1003. if (core_base & 0x8)
  1004. *mobile = false;
  1005. else
  1006. *mobile = true;
  1007. /* release memory */
  1008. iounmap(biosptr);
  1009. return true;
  1010. } else {
  1011. iounmap(biosptr);
  1012. return false;
  1013. }
  1014. }