qeth_core_main.c 123 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm-s390/ebcdic.h>
  21. #include <asm-s390/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. static struct device *qeth_core_root_dev;
  47. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  48. static struct lock_class_key qdio_out_skb_queue_key;
  49. static void qeth_send_control_data_cb(struct qeth_channel *,
  50. struct qeth_cmd_buffer *);
  51. static int qeth_issue_next_read(struct qeth_card *);
  52. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  53. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  54. static void qeth_free_buffer_pool(struct qeth_card *);
  55. static int qeth_qdio_establish(struct qeth_card *);
  56. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  57. struct qdio_buffer *buffer, int is_tso,
  58. int *next_element_to_fill)
  59. {
  60. struct skb_frag_struct *frag;
  61. int fragno;
  62. unsigned long addr;
  63. int element, cnt, dlen;
  64. fragno = skb_shinfo(skb)->nr_frags;
  65. element = *next_element_to_fill;
  66. dlen = 0;
  67. if (is_tso)
  68. buffer->element[element].flags =
  69. SBAL_FLAGS_MIDDLE_FRAG;
  70. else
  71. buffer->element[element].flags =
  72. SBAL_FLAGS_FIRST_FRAG;
  73. dlen = skb->len - skb->data_len;
  74. if (dlen) {
  75. buffer->element[element].addr = skb->data;
  76. buffer->element[element].length = dlen;
  77. element++;
  78. }
  79. for (cnt = 0; cnt < fragno; cnt++) {
  80. frag = &skb_shinfo(skb)->frags[cnt];
  81. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  82. frag->page_offset;
  83. buffer->element[element].addr = (char *)addr;
  84. buffer->element[element].length = frag->size;
  85. if (cnt < (fragno - 1))
  86. buffer->element[element].flags =
  87. SBAL_FLAGS_MIDDLE_FRAG;
  88. else
  89. buffer->element[element].flags =
  90. SBAL_FLAGS_LAST_FRAG;
  91. element++;
  92. }
  93. *next_element_to_fill = element;
  94. }
  95. static inline const char *qeth_get_cardname(struct qeth_card *card)
  96. {
  97. if (card->info.guestlan) {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSAE:
  100. return " Guest LAN QDIO";
  101. case QETH_CARD_TYPE_IQD:
  102. return " Guest LAN Hiper";
  103. default:
  104. return " unknown";
  105. }
  106. } else {
  107. switch (card->info.type) {
  108. case QETH_CARD_TYPE_OSAE:
  109. return " OSD Express";
  110. case QETH_CARD_TYPE_IQD:
  111. return " HiperSockets";
  112. case QETH_CARD_TYPE_OSN:
  113. return " OSN QDIO";
  114. default:
  115. return " unknown";
  116. }
  117. }
  118. return " n/a";
  119. }
  120. /* max length to be returned: 14 */
  121. const char *qeth_get_cardname_short(struct qeth_card *card)
  122. {
  123. if (card->info.guestlan) {
  124. switch (card->info.type) {
  125. case QETH_CARD_TYPE_OSAE:
  126. return "GuestLAN QDIO";
  127. case QETH_CARD_TYPE_IQD:
  128. return "GuestLAN Hiper";
  129. default:
  130. return "unknown";
  131. }
  132. } else {
  133. switch (card->info.type) {
  134. case QETH_CARD_TYPE_OSAE:
  135. switch (card->info.link_type) {
  136. case QETH_LINK_TYPE_FAST_ETH:
  137. return "OSD_100";
  138. case QETH_LINK_TYPE_HSTR:
  139. return "HSTR";
  140. case QETH_LINK_TYPE_GBIT_ETH:
  141. return "OSD_1000";
  142. case QETH_LINK_TYPE_10GBIT_ETH:
  143. return "OSD_10GIG";
  144. case QETH_LINK_TYPE_LANE_ETH100:
  145. return "OSD_FE_LANE";
  146. case QETH_LINK_TYPE_LANE_TR:
  147. return "OSD_TR_LANE";
  148. case QETH_LINK_TYPE_LANE_ETH1000:
  149. return "OSD_GbE_LANE";
  150. case QETH_LINK_TYPE_LANE:
  151. return "OSD_ATM_LANE";
  152. default:
  153. return "OSD_Express";
  154. }
  155. case QETH_CARD_TYPE_IQD:
  156. return "HiperSockets";
  157. case QETH_CARD_TYPE_OSN:
  158. return "OSN";
  159. default:
  160. return "unknown";
  161. }
  162. }
  163. return "n/a";
  164. }
  165. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  166. int clear_start_mask)
  167. {
  168. unsigned long flags;
  169. spin_lock_irqsave(&card->thread_mask_lock, flags);
  170. card->thread_allowed_mask = threads;
  171. if (clear_start_mask)
  172. card->thread_start_mask &= threads;
  173. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  174. wake_up(&card->wait_q);
  175. }
  176. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  177. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  178. {
  179. unsigned long flags;
  180. int rc = 0;
  181. spin_lock_irqsave(&card->thread_mask_lock, flags);
  182. rc = (card->thread_running_mask & threads);
  183. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  184. return rc;
  185. }
  186. EXPORT_SYMBOL_GPL(qeth_threads_running);
  187. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  188. {
  189. return wait_event_interruptible(card->wait_q,
  190. qeth_threads_running(card, threads) == 0);
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  193. void qeth_clear_working_pool_list(struct qeth_card *card)
  194. {
  195. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  196. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  197. list_for_each_entry_safe(pool_entry, tmp,
  198. &card->qdio.in_buf_pool.entry_list, list){
  199. list_del(&pool_entry->list);
  200. }
  201. }
  202. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  203. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  204. {
  205. struct qeth_buffer_pool_entry *pool_entry;
  206. void *ptr;
  207. int i, j;
  208. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  209. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  210. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  211. if (!pool_entry) {
  212. qeth_free_buffer_pool(card);
  213. return -ENOMEM;
  214. }
  215. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  216. ptr = (void *) __get_free_page(GFP_KERNEL);
  217. if (!ptr) {
  218. while (j > 0)
  219. free_page((unsigned long)
  220. pool_entry->elements[--j]);
  221. kfree(pool_entry);
  222. qeth_free_buffer_pool(card);
  223. return -ENOMEM;
  224. }
  225. pool_entry->elements[j] = ptr;
  226. }
  227. list_add(&pool_entry->init_list,
  228. &card->qdio.init_pool.entry_list);
  229. }
  230. return 0;
  231. }
  232. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  233. {
  234. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  235. if ((card->state != CARD_STATE_DOWN) &&
  236. (card->state != CARD_STATE_RECOVER))
  237. return -EPERM;
  238. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  239. qeth_clear_working_pool_list(card);
  240. qeth_free_buffer_pool(card);
  241. card->qdio.in_buf_pool.buf_count = bufcnt;
  242. card->qdio.init_pool.buf_count = bufcnt;
  243. return qeth_alloc_buffer_pool(card);
  244. }
  245. int qeth_set_large_send(struct qeth_card *card,
  246. enum qeth_large_send_types type)
  247. {
  248. int rc = 0;
  249. if (card->dev == NULL) {
  250. card->options.large_send = type;
  251. return 0;
  252. }
  253. if (card->state == CARD_STATE_UP)
  254. netif_tx_disable(card->dev);
  255. card->options.large_send = type;
  256. switch (card->options.large_send) {
  257. case QETH_LARGE_SEND_EDDP:
  258. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  259. NETIF_F_HW_CSUM;
  260. break;
  261. case QETH_LARGE_SEND_TSO:
  262. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  263. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  264. NETIF_F_HW_CSUM;
  265. } else {
  266. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  267. NETIF_F_HW_CSUM);
  268. card->options.large_send = QETH_LARGE_SEND_NO;
  269. rc = -EOPNOTSUPP;
  270. }
  271. break;
  272. default: /* includes QETH_LARGE_SEND_NO */
  273. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  274. NETIF_F_HW_CSUM);
  275. break;
  276. }
  277. if (card->state == CARD_STATE_UP)
  278. netif_wake_queue(card->dev);
  279. return rc;
  280. }
  281. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  282. static int qeth_issue_next_read(struct qeth_card *card)
  283. {
  284. int rc;
  285. struct qeth_cmd_buffer *iob;
  286. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  287. if (card->read.state != CH_STATE_UP)
  288. return -EIO;
  289. iob = qeth_get_buffer(&card->read);
  290. if (!iob) {
  291. PRINT_WARN("issue_next_read failed: no iob available!\n");
  292. return -ENOMEM;
  293. }
  294. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  295. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  296. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  297. (addr_t) iob, 0, 0);
  298. if (rc) {
  299. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  300. atomic_set(&card->read.irq_pending, 0);
  301. qeth_schedule_recovery(card);
  302. wake_up(&card->wait_q);
  303. }
  304. return rc;
  305. }
  306. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  307. {
  308. struct qeth_reply *reply;
  309. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  310. if (reply) {
  311. atomic_set(&reply->refcnt, 1);
  312. atomic_set(&reply->received, 0);
  313. reply->card = card;
  314. };
  315. return reply;
  316. }
  317. static void qeth_get_reply(struct qeth_reply *reply)
  318. {
  319. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  320. atomic_inc(&reply->refcnt);
  321. }
  322. static void qeth_put_reply(struct qeth_reply *reply)
  323. {
  324. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  325. if (atomic_dec_and_test(&reply->refcnt))
  326. kfree(reply);
  327. }
  328. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  329. struct qeth_card *card)
  330. {
  331. char *ipa_name;
  332. int com = cmd->hdr.command;
  333. ipa_name = qeth_get_ipa_cmd_name(com);
  334. if (rc)
  335. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  336. ipa_name, com, QETH_CARD_IFNAME(card),
  337. rc, qeth_get_ipa_msg(rc));
  338. else
  339. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  340. ipa_name, com, QETH_CARD_IFNAME(card));
  341. }
  342. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  343. struct qeth_cmd_buffer *iob)
  344. {
  345. struct qeth_ipa_cmd *cmd = NULL;
  346. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  347. if (IS_IPA(iob->data)) {
  348. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  349. if (IS_IPA_REPLY(cmd)) {
  350. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  351. cmd->hdr.command > IPA_CMD_MODCCID)
  352. qeth_issue_ipa_msg(cmd,
  353. cmd->hdr.return_code, card);
  354. return cmd;
  355. } else {
  356. switch (cmd->hdr.command) {
  357. case IPA_CMD_STOPLAN:
  358. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  359. "there is a network problem or "
  360. "someone pulled the cable or "
  361. "disabled the port.\n",
  362. QETH_CARD_IFNAME(card),
  363. card->info.chpid);
  364. card->lan_online = 0;
  365. if (card->dev && netif_carrier_ok(card->dev))
  366. netif_carrier_off(card->dev);
  367. return NULL;
  368. case IPA_CMD_STARTLAN:
  369. PRINT_INFO("Link reestablished on %s "
  370. "(CHPID 0x%X). Scheduling "
  371. "IP address reset.\n",
  372. QETH_CARD_IFNAME(card),
  373. card->info.chpid);
  374. netif_carrier_on(card->dev);
  375. card->lan_online = 1;
  376. qeth_schedule_recovery(card);
  377. return NULL;
  378. case IPA_CMD_MODCCID:
  379. return cmd;
  380. case IPA_CMD_REGISTER_LOCAL_ADDR:
  381. QETH_DBF_TEXT(TRACE, 3, "irla");
  382. break;
  383. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  384. QETH_DBF_TEXT(TRACE, 3, "urla");
  385. break;
  386. default:
  387. PRINT_WARN("Received data is IPA "
  388. "but not a reply!\n");
  389. break;
  390. }
  391. }
  392. }
  393. return cmd;
  394. }
  395. void qeth_clear_ipacmd_list(struct qeth_card *card)
  396. {
  397. struct qeth_reply *reply, *r;
  398. unsigned long flags;
  399. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  400. spin_lock_irqsave(&card->lock, flags);
  401. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  402. qeth_get_reply(reply);
  403. reply->rc = -EIO;
  404. atomic_inc(&reply->received);
  405. list_del_init(&reply->list);
  406. wake_up(&reply->wait_q);
  407. qeth_put_reply(reply);
  408. }
  409. spin_unlock_irqrestore(&card->lock, flags);
  410. }
  411. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  412. static int qeth_check_idx_response(unsigned char *buffer)
  413. {
  414. if (!buffer)
  415. return 0;
  416. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  417. if ((buffer[2] & 0xc0) == 0xc0) {
  418. PRINT_WARN("received an IDX TERMINATE "
  419. "with cause code 0x%02x%s\n",
  420. buffer[4],
  421. ((buffer[4] == 0x22) ?
  422. " -- try another portname" : ""));
  423. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  424. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  425. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  426. return -EIO;
  427. }
  428. return 0;
  429. }
  430. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  431. __u32 len)
  432. {
  433. struct qeth_card *card;
  434. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  435. card = CARD_FROM_CDEV(channel->ccwdev);
  436. if (channel == &card->read)
  437. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  438. else
  439. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  440. channel->ccw.count = len;
  441. channel->ccw.cda = (__u32) __pa(iob);
  442. }
  443. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. __u8 index;
  446. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  447. index = channel->io_buf_no;
  448. do {
  449. if (channel->iob[index].state == BUF_STATE_FREE) {
  450. channel->iob[index].state = BUF_STATE_LOCKED;
  451. channel->io_buf_no = (channel->io_buf_no + 1) %
  452. QETH_CMD_BUFFER_NO;
  453. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  454. return channel->iob + index;
  455. }
  456. index = (index + 1) % QETH_CMD_BUFFER_NO;
  457. } while (index != channel->io_buf_no);
  458. return NULL;
  459. }
  460. void qeth_release_buffer(struct qeth_channel *channel,
  461. struct qeth_cmd_buffer *iob)
  462. {
  463. unsigned long flags;
  464. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  465. spin_lock_irqsave(&channel->iob_lock, flags);
  466. memset(iob->data, 0, QETH_BUFSIZE);
  467. iob->state = BUF_STATE_FREE;
  468. iob->callback = qeth_send_control_data_cb;
  469. iob->rc = 0;
  470. spin_unlock_irqrestore(&channel->iob_lock, flags);
  471. }
  472. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  473. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  474. {
  475. struct qeth_cmd_buffer *buffer = NULL;
  476. unsigned long flags;
  477. spin_lock_irqsave(&channel->iob_lock, flags);
  478. buffer = __qeth_get_buffer(channel);
  479. spin_unlock_irqrestore(&channel->iob_lock, flags);
  480. return buffer;
  481. }
  482. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  483. {
  484. struct qeth_cmd_buffer *buffer;
  485. wait_event(channel->wait_q,
  486. ((buffer = qeth_get_buffer(channel)) != NULL));
  487. return buffer;
  488. }
  489. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  490. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  491. {
  492. int cnt;
  493. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  494. qeth_release_buffer(channel, &channel->iob[cnt]);
  495. channel->buf_no = 0;
  496. channel->io_buf_no = 0;
  497. }
  498. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  499. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  500. struct qeth_cmd_buffer *iob)
  501. {
  502. struct qeth_card *card;
  503. struct qeth_reply *reply, *r;
  504. struct qeth_ipa_cmd *cmd;
  505. unsigned long flags;
  506. int keep_reply;
  507. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  508. card = CARD_FROM_CDEV(channel->ccwdev);
  509. if (qeth_check_idx_response(iob->data)) {
  510. qeth_clear_ipacmd_list(card);
  511. qeth_schedule_recovery(card);
  512. goto out;
  513. }
  514. cmd = qeth_check_ipa_data(card, iob);
  515. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  516. goto out;
  517. /*in case of OSN : check if cmd is set */
  518. if (card->info.type == QETH_CARD_TYPE_OSN &&
  519. cmd &&
  520. cmd->hdr.command != IPA_CMD_STARTLAN &&
  521. card->osn_info.assist_cb != NULL) {
  522. card->osn_info.assist_cb(card->dev, cmd);
  523. goto out;
  524. }
  525. spin_lock_irqsave(&card->lock, flags);
  526. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  527. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  528. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  529. qeth_get_reply(reply);
  530. list_del_init(&reply->list);
  531. spin_unlock_irqrestore(&card->lock, flags);
  532. keep_reply = 0;
  533. if (reply->callback != NULL) {
  534. if (cmd) {
  535. reply->offset = (__u16)((char *)cmd -
  536. (char *)iob->data);
  537. keep_reply = reply->callback(card,
  538. reply,
  539. (unsigned long)cmd);
  540. } else
  541. keep_reply = reply->callback(card,
  542. reply,
  543. (unsigned long)iob);
  544. }
  545. if (cmd)
  546. reply->rc = (u16) cmd->hdr.return_code;
  547. else if (iob->rc)
  548. reply->rc = iob->rc;
  549. if (keep_reply) {
  550. spin_lock_irqsave(&card->lock, flags);
  551. list_add_tail(&reply->list,
  552. &card->cmd_waiter_list);
  553. spin_unlock_irqrestore(&card->lock, flags);
  554. } else {
  555. atomic_inc(&reply->received);
  556. wake_up(&reply->wait_q);
  557. }
  558. qeth_put_reply(reply);
  559. goto out;
  560. }
  561. }
  562. spin_unlock_irqrestore(&card->lock, flags);
  563. out:
  564. memcpy(&card->seqno.pdu_hdr_ack,
  565. QETH_PDU_HEADER_SEQ_NO(iob->data),
  566. QETH_SEQ_NO_LENGTH);
  567. qeth_release_buffer(channel, iob);
  568. }
  569. static int qeth_setup_channel(struct qeth_channel *channel)
  570. {
  571. int cnt;
  572. QETH_DBF_TEXT(SETUP, 2, "setupch");
  573. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  574. channel->iob[cnt].data = (char *)
  575. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  576. if (channel->iob[cnt].data == NULL)
  577. break;
  578. channel->iob[cnt].state = BUF_STATE_FREE;
  579. channel->iob[cnt].channel = channel;
  580. channel->iob[cnt].callback = qeth_send_control_data_cb;
  581. channel->iob[cnt].rc = 0;
  582. }
  583. if (cnt < QETH_CMD_BUFFER_NO) {
  584. while (cnt-- > 0)
  585. kfree(channel->iob[cnt].data);
  586. return -ENOMEM;
  587. }
  588. channel->buf_no = 0;
  589. channel->io_buf_no = 0;
  590. atomic_set(&channel->irq_pending, 0);
  591. spin_lock_init(&channel->iob_lock);
  592. init_waitqueue_head(&channel->wait_q);
  593. return 0;
  594. }
  595. static int qeth_set_thread_start_bit(struct qeth_card *card,
  596. unsigned long thread)
  597. {
  598. unsigned long flags;
  599. spin_lock_irqsave(&card->thread_mask_lock, flags);
  600. if (!(card->thread_allowed_mask & thread) ||
  601. (card->thread_start_mask & thread)) {
  602. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  603. return -EPERM;
  604. }
  605. card->thread_start_mask |= thread;
  606. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  607. return 0;
  608. }
  609. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  610. {
  611. unsigned long flags;
  612. spin_lock_irqsave(&card->thread_mask_lock, flags);
  613. card->thread_start_mask &= ~thread;
  614. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  615. wake_up(&card->wait_q);
  616. }
  617. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  618. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  619. {
  620. unsigned long flags;
  621. spin_lock_irqsave(&card->thread_mask_lock, flags);
  622. card->thread_running_mask &= ~thread;
  623. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  624. wake_up(&card->wait_q);
  625. }
  626. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  627. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  628. {
  629. unsigned long flags;
  630. int rc = 0;
  631. spin_lock_irqsave(&card->thread_mask_lock, flags);
  632. if (card->thread_start_mask & thread) {
  633. if ((card->thread_allowed_mask & thread) &&
  634. !(card->thread_running_mask & thread)) {
  635. rc = 1;
  636. card->thread_start_mask &= ~thread;
  637. card->thread_running_mask |= thread;
  638. } else
  639. rc = -EPERM;
  640. }
  641. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  642. return rc;
  643. }
  644. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  645. {
  646. int rc = 0;
  647. wait_event(card->wait_q,
  648. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  649. return rc;
  650. }
  651. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  652. void qeth_schedule_recovery(struct qeth_card *card)
  653. {
  654. QETH_DBF_TEXT(TRACE, 2, "startrec");
  655. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  656. schedule_work(&card->kernel_thread_starter);
  657. }
  658. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  659. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  660. {
  661. int dstat, cstat;
  662. char *sense;
  663. sense = (char *) irb->ecw;
  664. cstat = irb->scsw.cmd.cstat;
  665. dstat = irb->scsw.cmd.dstat;
  666. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  667. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  668. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  669. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  670. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  671. cdev->dev.bus_id, dstat, cstat);
  672. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  673. 16, 1, irb, 64, 1);
  674. return 1;
  675. }
  676. if (dstat & DEV_STAT_UNIT_CHECK) {
  677. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  678. SENSE_RESETTING_EVENT_FLAG) {
  679. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  680. return 1;
  681. }
  682. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  683. SENSE_COMMAND_REJECT_FLAG) {
  684. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  685. return 0;
  686. }
  687. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  688. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  689. return 1;
  690. }
  691. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  692. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  693. return 0;
  694. }
  695. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  696. return 1;
  697. }
  698. return 0;
  699. }
  700. static long __qeth_check_irb_error(struct ccw_device *cdev,
  701. unsigned long intparm, struct irb *irb)
  702. {
  703. if (!IS_ERR(irb))
  704. return 0;
  705. switch (PTR_ERR(irb)) {
  706. case -EIO:
  707. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  708. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  709. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  710. break;
  711. case -ETIMEDOUT:
  712. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  713. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  714. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  715. if (intparm == QETH_RCD_PARM) {
  716. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  717. if (card && (card->data.ccwdev == cdev)) {
  718. card->data.state = CH_STATE_DOWN;
  719. wake_up(&card->wait_q);
  720. }
  721. }
  722. break;
  723. default:
  724. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  725. cdev->dev.bus_id);
  726. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  727. QETH_DBF_TEXT(TRACE, 2, " rc???");
  728. }
  729. return PTR_ERR(irb);
  730. }
  731. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  732. struct irb *irb)
  733. {
  734. int rc;
  735. int cstat, dstat;
  736. struct qeth_cmd_buffer *buffer;
  737. struct qeth_channel *channel;
  738. struct qeth_card *card;
  739. struct qeth_cmd_buffer *iob;
  740. __u8 index;
  741. QETH_DBF_TEXT(TRACE, 5, "irq");
  742. if (__qeth_check_irb_error(cdev, intparm, irb))
  743. return;
  744. cstat = irb->scsw.cmd.cstat;
  745. dstat = irb->scsw.cmd.dstat;
  746. card = CARD_FROM_CDEV(cdev);
  747. if (!card)
  748. return;
  749. if (card->read.ccwdev == cdev) {
  750. channel = &card->read;
  751. QETH_DBF_TEXT(TRACE, 5, "read");
  752. } else if (card->write.ccwdev == cdev) {
  753. channel = &card->write;
  754. QETH_DBF_TEXT(TRACE, 5, "write");
  755. } else {
  756. channel = &card->data;
  757. QETH_DBF_TEXT(TRACE, 5, "data");
  758. }
  759. atomic_set(&channel->irq_pending, 0);
  760. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  761. channel->state = CH_STATE_STOPPED;
  762. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  763. channel->state = CH_STATE_HALTED;
  764. /*let's wake up immediately on data channel*/
  765. if ((channel == &card->data) && (intparm != 0) &&
  766. (intparm != QETH_RCD_PARM))
  767. goto out;
  768. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  769. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  770. /* we don't have to handle this further */
  771. intparm = 0;
  772. }
  773. if (intparm == QETH_HALT_CHANNEL_PARM) {
  774. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  775. /* we don't have to handle this further */
  776. intparm = 0;
  777. }
  778. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  779. (dstat & DEV_STAT_UNIT_CHECK) ||
  780. (cstat)) {
  781. if (irb->esw.esw0.erw.cons) {
  782. /* TODO: we should make this s390dbf */
  783. PRINT_WARN("sense data available on channel %s.\n",
  784. CHANNEL_ID(channel));
  785. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  786. print_hex_dump(KERN_WARNING, "qeth: irb ",
  787. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  788. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  789. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  790. }
  791. if (intparm == QETH_RCD_PARM) {
  792. channel->state = CH_STATE_DOWN;
  793. goto out;
  794. }
  795. rc = qeth_get_problem(cdev, irb);
  796. if (rc) {
  797. qeth_schedule_recovery(card);
  798. goto out;
  799. }
  800. }
  801. if (intparm == QETH_RCD_PARM) {
  802. channel->state = CH_STATE_RCD_DONE;
  803. goto out;
  804. }
  805. if (intparm) {
  806. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  807. buffer->state = BUF_STATE_PROCESSED;
  808. }
  809. if (channel == &card->data)
  810. return;
  811. if (channel == &card->read &&
  812. channel->state == CH_STATE_UP)
  813. qeth_issue_next_read(card);
  814. iob = channel->iob;
  815. index = channel->buf_no;
  816. while (iob[index].state == BUF_STATE_PROCESSED) {
  817. if (iob[index].callback != NULL)
  818. iob[index].callback(channel, iob + index);
  819. index = (index + 1) % QETH_CMD_BUFFER_NO;
  820. }
  821. channel->buf_no = index;
  822. out:
  823. wake_up(&card->wait_q);
  824. return;
  825. }
  826. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  827. struct qeth_qdio_out_buffer *buf)
  828. {
  829. int i;
  830. struct sk_buff *skb;
  831. /* is PCI flag set on buffer? */
  832. if (buf->buffer->element[0].flags & 0x40)
  833. atomic_dec(&queue->set_pci_flags_count);
  834. skb = skb_dequeue(&buf->skb_list);
  835. while (skb) {
  836. atomic_dec(&skb->users);
  837. dev_kfree_skb_any(skb);
  838. skb = skb_dequeue(&buf->skb_list);
  839. }
  840. qeth_eddp_buf_release_contexts(buf);
  841. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  842. buf->buffer->element[i].length = 0;
  843. buf->buffer->element[i].addr = NULL;
  844. buf->buffer->element[i].flags = 0;
  845. }
  846. buf->next_element_to_fill = 0;
  847. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  848. }
  849. void qeth_clear_qdio_buffers(struct qeth_card *card)
  850. {
  851. int i, j;
  852. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  853. /* clear outbound buffers to free skbs */
  854. for (i = 0; i < card->qdio.no_out_queues; ++i)
  855. if (card->qdio.out_qs[i]) {
  856. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  857. qeth_clear_output_buffer(card->qdio.out_qs[i],
  858. &card->qdio.out_qs[i]->bufs[j]);
  859. }
  860. }
  861. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  862. static void qeth_free_buffer_pool(struct qeth_card *card)
  863. {
  864. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  865. int i = 0;
  866. QETH_DBF_TEXT(TRACE, 5, "freepool");
  867. list_for_each_entry_safe(pool_entry, tmp,
  868. &card->qdio.init_pool.entry_list, init_list){
  869. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  870. free_page((unsigned long)pool_entry->elements[i]);
  871. list_del(&pool_entry->init_list);
  872. kfree(pool_entry);
  873. }
  874. }
  875. static void qeth_free_qdio_buffers(struct qeth_card *card)
  876. {
  877. int i, j;
  878. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  879. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  880. QETH_QDIO_UNINITIALIZED)
  881. return;
  882. kfree(card->qdio.in_q);
  883. card->qdio.in_q = NULL;
  884. /* inbound buffer pool */
  885. qeth_free_buffer_pool(card);
  886. /* free outbound qdio_qs */
  887. if (card->qdio.out_qs) {
  888. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  889. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  890. qeth_clear_output_buffer(card->qdio.out_qs[i],
  891. &card->qdio.out_qs[i]->bufs[j]);
  892. kfree(card->qdio.out_qs[i]);
  893. }
  894. kfree(card->qdio.out_qs);
  895. card->qdio.out_qs = NULL;
  896. }
  897. }
  898. static void qeth_clean_channel(struct qeth_channel *channel)
  899. {
  900. int cnt;
  901. QETH_DBF_TEXT(SETUP, 2, "freech");
  902. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  903. kfree(channel->iob[cnt].data);
  904. }
  905. static int qeth_is_1920_device(struct qeth_card *card)
  906. {
  907. int single_queue = 0;
  908. struct ccw_device *ccwdev;
  909. struct channelPath_dsc {
  910. u8 flags;
  911. u8 lsn;
  912. u8 desc;
  913. u8 chpid;
  914. u8 swla;
  915. u8 zeroes;
  916. u8 chla;
  917. u8 chpp;
  918. } *chp_dsc;
  919. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  920. ccwdev = card->data.ccwdev;
  921. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  922. if (chp_dsc != NULL) {
  923. /* CHPP field bit 6 == 1 -> single queue */
  924. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  925. kfree(chp_dsc);
  926. }
  927. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  928. return single_queue;
  929. }
  930. static void qeth_init_qdio_info(struct qeth_card *card)
  931. {
  932. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  933. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  934. /* inbound */
  935. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  936. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  937. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  938. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  939. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  940. }
  941. static void qeth_set_intial_options(struct qeth_card *card)
  942. {
  943. card->options.route4.type = NO_ROUTER;
  944. card->options.route6.type = NO_ROUTER;
  945. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  946. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  947. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  948. card->options.fake_broadcast = 0;
  949. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  950. card->options.fake_ll = 0;
  951. card->options.performance_stats = 0;
  952. card->options.rx_sg_cb = QETH_RX_SG_CB;
  953. }
  954. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  955. {
  956. unsigned long flags;
  957. int rc = 0;
  958. spin_lock_irqsave(&card->thread_mask_lock, flags);
  959. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  960. (u8) card->thread_start_mask,
  961. (u8) card->thread_allowed_mask,
  962. (u8) card->thread_running_mask);
  963. rc = (card->thread_start_mask & thread);
  964. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  965. return rc;
  966. }
  967. static void qeth_start_kernel_thread(struct work_struct *work)
  968. {
  969. struct qeth_card *card = container_of(work, struct qeth_card,
  970. kernel_thread_starter);
  971. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  972. if (card->read.state != CH_STATE_UP &&
  973. card->write.state != CH_STATE_UP)
  974. return;
  975. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  976. kthread_run(card->discipline.recover, (void *) card,
  977. "qeth_recover");
  978. }
  979. static int qeth_setup_card(struct qeth_card *card)
  980. {
  981. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  982. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  983. card->read.state = CH_STATE_DOWN;
  984. card->write.state = CH_STATE_DOWN;
  985. card->data.state = CH_STATE_DOWN;
  986. card->state = CARD_STATE_DOWN;
  987. card->lan_online = 0;
  988. card->use_hard_stop = 0;
  989. card->dev = NULL;
  990. spin_lock_init(&card->vlanlock);
  991. spin_lock_init(&card->mclock);
  992. card->vlangrp = NULL;
  993. spin_lock_init(&card->lock);
  994. spin_lock_init(&card->ip_lock);
  995. spin_lock_init(&card->thread_mask_lock);
  996. card->thread_start_mask = 0;
  997. card->thread_allowed_mask = 0;
  998. card->thread_running_mask = 0;
  999. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1000. INIT_LIST_HEAD(&card->ip_list);
  1001. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1002. if (!card->ip_tbd_list) {
  1003. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1004. return -ENOMEM;
  1005. }
  1006. INIT_LIST_HEAD(card->ip_tbd_list);
  1007. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1008. init_waitqueue_head(&card->wait_q);
  1009. /* intial options */
  1010. qeth_set_intial_options(card);
  1011. /* IP address takeover */
  1012. INIT_LIST_HEAD(&card->ipato.entries);
  1013. card->ipato.enabled = 0;
  1014. card->ipato.invert4 = 0;
  1015. card->ipato.invert6 = 0;
  1016. /* init QDIO stuff */
  1017. qeth_init_qdio_info(card);
  1018. return 0;
  1019. }
  1020. static struct qeth_card *qeth_alloc_card(void)
  1021. {
  1022. struct qeth_card *card;
  1023. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1024. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1025. if (!card)
  1026. return NULL;
  1027. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1028. if (qeth_setup_channel(&card->read)) {
  1029. kfree(card);
  1030. return NULL;
  1031. }
  1032. if (qeth_setup_channel(&card->write)) {
  1033. qeth_clean_channel(&card->read);
  1034. kfree(card);
  1035. return NULL;
  1036. }
  1037. card->options.layer2 = -1;
  1038. return card;
  1039. }
  1040. static int qeth_determine_card_type(struct qeth_card *card)
  1041. {
  1042. int i = 0;
  1043. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1044. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1045. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1046. while (known_devices[i][4]) {
  1047. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1048. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1049. card->info.type = known_devices[i][4];
  1050. card->qdio.no_out_queues = known_devices[i][8];
  1051. card->info.is_multicast_different = known_devices[i][9];
  1052. if (qeth_is_1920_device(card)) {
  1053. PRINT_INFO("Priority Queueing not able "
  1054. "due to hardware limitations!\n");
  1055. card->qdio.no_out_queues = 1;
  1056. card->qdio.default_out_queue = 0;
  1057. }
  1058. return 0;
  1059. }
  1060. i++;
  1061. }
  1062. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1063. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1064. return -ENOENT;
  1065. }
  1066. static int qeth_clear_channel(struct qeth_channel *channel)
  1067. {
  1068. unsigned long flags;
  1069. struct qeth_card *card;
  1070. int rc;
  1071. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1072. card = CARD_FROM_CDEV(channel->ccwdev);
  1073. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1074. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1075. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1076. if (rc)
  1077. return rc;
  1078. rc = wait_event_interruptible_timeout(card->wait_q,
  1079. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1080. if (rc == -ERESTARTSYS)
  1081. return rc;
  1082. if (channel->state != CH_STATE_STOPPED)
  1083. return -ETIME;
  1084. channel->state = CH_STATE_DOWN;
  1085. return 0;
  1086. }
  1087. static int qeth_halt_channel(struct qeth_channel *channel)
  1088. {
  1089. unsigned long flags;
  1090. struct qeth_card *card;
  1091. int rc;
  1092. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1093. card = CARD_FROM_CDEV(channel->ccwdev);
  1094. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1095. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1096. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1097. if (rc)
  1098. return rc;
  1099. rc = wait_event_interruptible_timeout(card->wait_q,
  1100. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1101. if (rc == -ERESTARTSYS)
  1102. return rc;
  1103. if (channel->state != CH_STATE_HALTED)
  1104. return -ETIME;
  1105. return 0;
  1106. }
  1107. static int qeth_halt_channels(struct qeth_card *card)
  1108. {
  1109. int rc1 = 0, rc2 = 0, rc3 = 0;
  1110. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1111. rc1 = qeth_halt_channel(&card->read);
  1112. rc2 = qeth_halt_channel(&card->write);
  1113. rc3 = qeth_halt_channel(&card->data);
  1114. if (rc1)
  1115. return rc1;
  1116. if (rc2)
  1117. return rc2;
  1118. return rc3;
  1119. }
  1120. static int qeth_clear_channels(struct qeth_card *card)
  1121. {
  1122. int rc1 = 0, rc2 = 0, rc3 = 0;
  1123. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1124. rc1 = qeth_clear_channel(&card->read);
  1125. rc2 = qeth_clear_channel(&card->write);
  1126. rc3 = qeth_clear_channel(&card->data);
  1127. if (rc1)
  1128. return rc1;
  1129. if (rc2)
  1130. return rc2;
  1131. return rc3;
  1132. }
  1133. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1134. {
  1135. int rc = 0;
  1136. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1137. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1138. if (halt)
  1139. rc = qeth_halt_channels(card);
  1140. if (rc)
  1141. return rc;
  1142. return qeth_clear_channels(card);
  1143. }
  1144. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1145. {
  1146. int rc = 0;
  1147. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1148. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1149. QETH_QDIO_CLEANING)) {
  1150. case QETH_QDIO_ESTABLISHED:
  1151. if (card->info.type == QETH_CARD_TYPE_IQD)
  1152. rc = qdio_cleanup(CARD_DDEV(card),
  1153. QDIO_FLAG_CLEANUP_USING_HALT);
  1154. else
  1155. rc = qdio_cleanup(CARD_DDEV(card),
  1156. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1157. if (rc)
  1158. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1159. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1160. break;
  1161. case QETH_QDIO_CLEANING:
  1162. return rc;
  1163. default:
  1164. break;
  1165. }
  1166. rc = qeth_clear_halt_card(card, use_halt);
  1167. if (rc)
  1168. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1169. card->state = CARD_STATE_DOWN;
  1170. return rc;
  1171. }
  1172. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1173. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1174. int *length)
  1175. {
  1176. struct ciw *ciw;
  1177. char *rcd_buf;
  1178. int ret;
  1179. struct qeth_channel *channel = &card->data;
  1180. unsigned long flags;
  1181. /*
  1182. * scan for RCD command in extended SenseID data
  1183. */
  1184. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1185. if (!ciw || ciw->cmd == 0)
  1186. return -EOPNOTSUPP;
  1187. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1188. if (!rcd_buf)
  1189. return -ENOMEM;
  1190. channel->ccw.cmd_code = ciw->cmd;
  1191. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1192. channel->ccw.count = ciw->count;
  1193. channel->ccw.flags = CCW_FLAG_SLI;
  1194. channel->state = CH_STATE_RCD;
  1195. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1196. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1197. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1198. QETH_RCD_TIMEOUT);
  1199. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1200. if (!ret)
  1201. wait_event(card->wait_q,
  1202. (channel->state == CH_STATE_RCD_DONE ||
  1203. channel->state == CH_STATE_DOWN));
  1204. if (channel->state == CH_STATE_DOWN)
  1205. ret = -EIO;
  1206. else
  1207. channel->state = CH_STATE_DOWN;
  1208. if (ret) {
  1209. kfree(rcd_buf);
  1210. *buffer = NULL;
  1211. *length = 0;
  1212. } else {
  1213. *length = ciw->count;
  1214. *buffer = rcd_buf;
  1215. }
  1216. return ret;
  1217. }
  1218. static int qeth_get_unitaddr(struct qeth_card *card)
  1219. {
  1220. int length;
  1221. char *prcd;
  1222. int rc;
  1223. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1224. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1225. if (rc) {
  1226. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1227. CARD_DDEV_ID(card), rc);
  1228. return rc;
  1229. }
  1230. card->info.chpid = prcd[30];
  1231. card->info.unit_addr2 = prcd[31];
  1232. card->info.cula = prcd[63];
  1233. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1234. (prcd[0x11] == _ascebc['M']));
  1235. kfree(prcd);
  1236. return 0;
  1237. }
  1238. static void qeth_init_tokens(struct qeth_card *card)
  1239. {
  1240. card->token.issuer_rm_w = 0x00010103UL;
  1241. card->token.cm_filter_w = 0x00010108UL;
  1242. card->token.cm_connection_w = 0x0001010aUL;
  1243. card->token.ulp_filter_w = 0x0001010bUL;
  1244. card->token.ulp_connection_w = 0x0001010dUL;
  1245. }
  1246. static void qeth_init_func_level(struct qeth_card *card)
  1247. {
  1248. if (card->ipato.enabled) {
  1249. if (card->info.type == QETH_CARD_TYPE_IQD)
  1250. card->info.func_level =
  1251. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1252. else
  1253. card->info.func_level =
  1254. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1255. } else {
  1256. if (card->info.type == QETH_CARD_TYPE_IQD)
  1257. /*FIXME:why do we have same values for dis and ena for
  1258. osae??? */
  1259. card->info.func_level =
  1260. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1261. else
  1262. card->info.func_level =
  1263. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1264. }
  1265. }
  1266. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1267. void (*idx_reply_cb)(struct qeth_channel *,
  1268. struct qeth_cmd_buffer *))
  1269. {
  1270. struct qeth_cmd_buffer *iob;
  1271. unsigned long flags;
  1272. int rc;
  1273. struct qeth_card *card;
  1274. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1275. card = CARD_FROM_CDEV(channel->ccwdev);
  1276. iob = qeth_get_buffer(channel);
  1277. iob->callback = idx_reply_cb;
  1278. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1279. channel->ccw.count = QETH_BUFSIZE;
  1280. channel->ccw.cda = (__u32) __pa(iob->data);
  1281. wait_event(card->wait_q,
  1282. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1283. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1284. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1285. rc = ccw_device_start(channel->ccwdev,
  1286. &channel->ccw, (addr_t) iob, 0, 0);
  1287. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1288. if (rc) {
  1289. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1290. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1291. atomic_set(&channel->irq_pending, 0);
  1292. wake_up(&card->wait_q);
  1293. return rc;
  1294. }
  1295. rc = wait_event_interruptible_timeout(card->wait_q,
  1296. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1297. if (rc == -ERESTARTSYS)
  1298. return rc;
  1299. if (channel->state != CH_STATE_UP) {
  1300. rc = -ETIME;
  1301. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1302. qeth_clear_cmd_buffers(channel);
  1303. } else
  1304. rc = 0;
  1305. return rc;
  1306. }
  1307. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1308. void (*idx_reply_cb)(struct qeth_channel *,
  1309. struct qeth_cmd_buffer *))
  1310. {
  1311. struct qeth_card *card;
  1312. struct qeth_cmd_buffer *iob;
  1313. unsigned long flags;
  1314. __u16 temp;
  1315. __u8 tmp;
  1316. int rc;
  1317. struct ccw_dev_id temp_devid;
  1318. card = CARD_FROM_CDEV(channel->ccwdev);
  1319. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1320. iob = qeth_get_buffer(channel);
  1321. iob->callback = idx_reply_cb;
  1322. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1323. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1324. channel->ccw.cda = (__u32) __pa(iob->data);
  1325. if (channel == &card->write) {
  1326. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1327. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1328. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1329. card->seqno.trans_hdr++;
  1330. } else {
  1331. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1332. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1333. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1334. }
  1335. tmp = ((__u8)card->info.portno) | 0x80;
  1336. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1337. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1338. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1339. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1340. &card->info.func_level, sizeof(__u16));
  1341. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1342. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1343. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1344. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1345. wait_event(card->wait_q,
  1346. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1347. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1348. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1349. rc = ccw_device_start(channel->ccwdev,
  1350. &channel->ccw, (addr_t) iob, 0, 0);
  1351. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1352. if (rc) {
  1353. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1354. rc);
  1355. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1356. atomic_set(&channel->irq_pending, 0);
  1357. wake_up(&card->wait_q);
  1358. return rc;
  1359. }
  1360. rc = wait_event_interruptible_timeout(card->wait_q,
  1361. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1362. if (rc == -ERESTARTSYS)
  1363. return rc;
  1364. if (channel->state != CH_STATE_ACTIVATING) {
  1365. PRINT_WARN("IDX activate timed out!\n");
  1366. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1367. qeth_clear_cmd_buffers(channel);
  1368. return -ETIME;
  1369. }
  1370. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1371. }
  1372. static int qeth_peer_func_level(int level)
  1373. {
  1374. if ((level & 0xff) == 8)
  1375. return (level & 0xff) + 0x400;
  1376. if (((level >> 8) & 3) == 1)
  1377. return (level & 0xff) + 0x200;
  1378. return level;
  1379. }
  1380. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1381. struct qeth_cmd_buffer *iob)
  1382. {
  1383. struct qeth_card *card;
  1384. __u16 temp;
  1385. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1386. if (channel->state == CH_STATE_DOWN) {
  1387. channel->state = CH_STATE_ACTIVATING;
  1388. goto out;
  1389. }
  1390. card = CARD_FROM_CDEV(channel->ccwdev);
  1391. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1392. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1393. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1394. "adapter exclusively used by another host\n",
  1395. CARD_WDEV_ID(card));
  1396. else
  1397. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1398. "negative reply\n", CARD_WDEV_ID(card));
  1399. goto out;
  1400. }
  1401. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1402. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1403. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1404. "function level mismatch "
  1405. "(sent: 0x%x, received: 0x%x)\n",
  1406. CARD_WDEV_ID(card), card->info.func_level, temp);
  1407. goto out;
  1408. }
  1409. channel->state = CH_STATE_UP;
  1410. out:
  1411. qeth_release_buffer(channel, iob);
  1412. }
  1413. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1414. struct qeth_cmd_buffer *iob)
  1415. {
  1416. struct qeth_card *card;
  1417. __u16 temp;
  1418. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1419. if (channel->state == CH_STATE_DOWN) {
  1420. channel->state = CH_STATE_ACTIVATING;
  1421. goto out;
  1422. }
  1423. card = CARD_FROM_CDEV(channel->ccwdev);
  1424. if (qeth_check_idx_response(iob->data))
  1425. goto out;
  1426. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1427. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1428. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1429. "adapter exclusively used by another host\n",
  1430. CARD_RDEV_ID(card));
  1431. else
  1432. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1433. "negative reply\n", CARD_RDEV_ID(card));
  1434. goto out;
  1435. }
  1436. /**
  1437. * temporary fix for microcode bug
  1438. * to revert it,replace OR by AND
  1439. */
  1440. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1441. (card->info.type == QETH_CARD_TYPE_OSAE))
  1442. card->info.portname_required = 1;
  1443. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1444. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1445. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1446. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1447. CARD_RDEV_ID(card), card->info.func_level, temp);
  1448. goto out;
  1449. }
  1450. memcpy(&card->token.issuer_rm_r,
  1451. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1452. QETH_MPC_TOKEN_LENGTH);
  1453. memcpy(&card->info.mcl_level[0],
  1454. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1455. channel->state = CH_STATE_UP;
  1456. out:
  1457. qeth_release_buffer(channel, iob);
  1458. }
  1459. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1460. struct qeth_cmd_buffer *iob)
  1461. {
  1462. qeth_setup_ccw(&card->write, iob->data, len);
  1463. iob->callback = qeth_release_buffer;
  1464. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1465. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1466. card->seqno.trans_hdr++;
  1467. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1468. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1469. card->seqno.pdu_hdr++;
  1470. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1471. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1472. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1473. }
  1474. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1475. int qeth_send_control_data(struct qeth_card *card, int len,
  1476. struct qeth_cmd_buffer *iob,
  1477. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1478. unsigned long),
  1479. void *reply_param)
  1480. {
  1481. int rc;
  1482. unsigned long flags;
  1483. struct qeth_reply *reply = NULL;
  1484. unsigned long timeout;
  1485. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1486. reply = qeth_alloc_reply(card);
  1487. if (!reply) {
  1488. return -ENOMEM;
  1489. }
  1490. reply->callback = reply_cb;
  1491. reply->param = reply_param;
  1492. if (card->state == CARD_STATE_DOWN)
  1493. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1494. else
  1495. reply->seqno = card->seqno.ipa++;
  1496. init_waitqueue_head(&reply->wait_q);
  1497. spin_lock_irqsave(&card->lock, flags);
  1498. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1499. spin_unlock_irqrestore(&card->lock, flags);
  1500. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1501. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1502. qeth_prepare_control_data(card, len, iob);
  1503. if (IS_IPA(iob->data))
  1504. timeout = jiffies + QETH_IPA_TIMEOUT;
  1505. else
  1506. timeout = jiffies + QETH_TIMEOUT;
  1507. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1508. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1509. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1510. (addr_t) iob, 0, 0);
  1511. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1512. if (rc) {
  1513. PRINT_WARN("qeth_send_control_data: "
  1514. "ccw_device_start rc = %i\n", rc);
  1515. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1516. spin_lock_irqsave(&card->lock, flags);
  1517. list_del_init(&reply->list);
  1518. qeth_put_reply(reply);
  1519. spin_unlock_irqrestore(&card->lock, flags);
  1520. qeth_release_buffer(iob->channel, iob);
  1521. atomic_set(&card->write.irq_pending, 0);
  1522. wake_up(&card->wait_q);
  1523. return rc;
  1524. }
  1525. while (!atomic_read(&reply->received)) {
  1526. if (time_after(jiffies, timeout)) {
  1527. spin_lock_irqsave(&reply->card->lock, flags);
  1528. list_del_init(&reply->list);
  1529. spin_unlock_irqrestore(&reply->card->lock, flags);
  1530. reply->rc = -ETIME;
  1531. atomic_inc(&reply->received);
  1532. wake_up(&reply->wait_q);
  1533. }
  1534. cpu_relax();
  1535. };
  1536. rc = reply->rc;
  1537. qeth_put_reply(reply);
  1538. return rc;
  1539. }
  1540. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1541. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1542. unsigned long data)
  1543. {
  1544. struct qeth_cmd_buffer *iob;
  1545. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1546. iob = (struct qeth_cmd_buffer *) data;
  1547. memcpy(&card->token.cm_filter_r,
  1548. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1549. QETH_MPC_TOKEN_LENGTH);
  1550. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1551. return 0;
  1552. }
  1553. static int qeth_cm_enable(struct qeth_card *card)
  1554. {
  1555. int rc;
  1556. struct qeth_cmd_buffer *iob;
  1557. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1558. iob = qeth_wait_for_buffer(&card->write);
  1559. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1560. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1561. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1562. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1563. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1564. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1565. qeth_cm_enable_cb, NULL);
  1566. return rc;
  1567. }
  1568. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1569. unsigned long data)
  1570. {
  1571. struct qeth_cmd_buffer *iob;
  1572. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1573. iob = (struct qeth_cmd_buffer *) data;
  1574. memcpy(&card->token.cm_connection_r,
  1575. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1576. QETH_MPC_TOKEN_LENGTH);
  1577. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1578. return 0;
  1579. }
  1580. static int qeth_cm_setup(struct qeth_card *card)
  1581. {
  1582. int rc;
  1583. struct qeth_cmd_buffer *iob;
  1584. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1585. iob = qeth_wait_for_buffer(&card->write);
  1586. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1587. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1588. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1589. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1590. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1591. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1592. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1593. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1594. qeth_cm_setup_cb, NULL);
  1595. return rc;
  1596. }
  1597. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1598. {
  1599. switch (card->info.type) {
  1600. case QETH_CARD_TYPE_UNKNOWN:
  1601. return 1500;
  1602. case QETH_CARD_TYPE_IQD:
  1603. return card->info.max_mtu;
  1604. case QETH_CARD_TYPE_OSAE:
  1605. switch (card->info.link_type) {
  1606. case QETH_LINK_TYPE_HSTR:
  1607. case QETH_LINK_TYPE_LANE_TR:
  1608. return 2000;
  1609. default:
  1610. return 1492;
  1611. }
  1612. default:
  1613. return 1500;
  1614. }
  1615. }
  1616. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1617. {
  1618. switch (cardtype) {
  1619. case QETH_CARD_TYPE_UNKNOWN:
  1620. case QETH_CARD_TYPE_OSAE:
  1621. case QETH_CARD_TYPE_OSN:
  1622. return 61440;
  1623. case QETH_CARD_TYPE_IQD:
  1624. return 57344;
  1625. default:
  1626. return 1500;
  1627. }
  1628. }
  1629. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1630. {
  1631. switch (cardtype) {
  1632. case QETH_CARD_TYPE_IQD:
  1633. return 1;
  1634. default:
  1635. return 0;
  1636. }
  1637. }
  1638. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1639. {
  1640. switch (framesize) {
  1641. case 0x4000:
  1642. return 8192;
  1643. case 0x6000:
  1644. return 16384;
  1645. case 0xa000:
  1646. return 32768;
  1647. case 0xffff:
  1648. return 57344;
  1649. default:
  1650. return 0;
  1651. }
  1652. }
  1653. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1654. {
  1655. switch (card->info.type) {
  1656. case QETH_CARD_TYPE_OSAE:
  1657. return ((mtu >= 576) && (mtu <= 61440));
  1658. case QETH_CARD_TYPE_IQD:
  1659. return ((mtu >= 576) &&
  1660. (mtu <= card->info.max_mtu + 4096 - 32));
  1661. case QETH_CARD_TYPE_OSN:
  1662. case QETH_CARD_TYPE_UNKNOWN:
  1663. default:
  1664. return 1;
  1665. }
  1666. }
  1667. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1668. unsigned long data)
  1669. {
  1670. __u16 mtu, framesize;
  1671. __u16 len;
  1672. __u8 link_type;
  1673. struct qeth_cmd_buffer *iob;
  1674. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1675. iob = (struct qeth_cmd_buffer *) data;
  1676. memcpy(&card->token.ulp_filter_r,
  1677. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1678. QETH_MPC_TOKEN_LENGTH);
  1679. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1680. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1681. mtu = qeth_get_mtu_outof_framesize(framesize);
  1682. if (!mtu) {
  1683. iob->rc = -EINVAL;
  1684. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1685. return 0;
  1686. }
  1687. card->info.max_mtu = mtu;
  1688. card->info.initial_mtu = mtu;
  1689. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1690. } else {
  1691. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1692. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1693. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1694. }
  1695. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1696. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1697. memcpy(&link_type,
  1698. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1699. card->info.link_type = link_type;
  1700. } else
  1701. card->info.link_type = 0;
  1702. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1703. return 0;
  1704. }
  1705. static int qeth_ulp_enable(struct qeth_card *card)
  1706. {
  1707. int rc;
  1708. char prot_type;
  1709. struct qeth_cmd_buffer *iob;
  1710. /*FIXME: trace view callbacks*/
  1711. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1712. iob = qeth_wait_for_buffer(&card->write);
  1713. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1714. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1715. (__u8) card->info.portno;
  1716. if (card->options.layer2)
  1717. if (card->info.type == QETH_CARD_TYPE_OSN)
  1718. prot_type = QETH_PROT_OSN2;
  1719. else
  1720. prot_type = QETH_PROT_LAYER2;
  1721. else
  1722. prot_type = QETH_PROT_TCPIP;
  1723. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1724. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1725. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1726. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1727. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1728. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1729. card->info.portname, 9);
  1730. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1731. qeth_ulp_enable_cb, NULL);
  1732. return rc;
  1733. }
  1734. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1735. unsigned long data)
  1736. {
  1737. struct qeth_cmd_buffer *iob;
  1738. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1739. iob = (struct qeth_cmd_buffer *) data;
  1740. memcpy(&card->token.ulp_connection_r,
  1741. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1742. QETH_MPC_TOKEN_LENGTH);
  1743. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1744. return 0;
  1745. }
  1746. static int qeth_ulp_setup(struct qeth_card *card)
  1747. {
  1748. int rc;
  1749. __u16 temp;
  1750. struct qeth_cmd_buffer *iob;
  1751. struct ccw_dev_id dev_id;
  1752. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1753. iob = qeth_wait_for_buffer(&card->write);
  1754. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1755. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1756. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1757. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1758. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1759. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1760. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1761. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1762. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1763. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1764. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1765. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1766. qeth_ulp_setup_cb, NULL);
  1767. return rc;
  1768. }
  1769. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1770. {
  1771. int i, j;
  1772. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1773. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1774. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1775. return 0;
  1776. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1777. GFP_KERNEL);
  1778. if (!card->qdio.in_q)
  1779. goto out_nomem;
  1780. QETH_DBF_TEXT(SETUP, 2, "inq");
  1781. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1782. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1783. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1784. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1785. card->qdio.in_q->bufs[i].buffer =
  1786. &card->qdio.in_q->qdio_bufs[i];
  1787. /* inbound buffer pool */
  1788. if (qeth_alloc_buffer_pool(card))
  1789. goto out_freeinq;
  1790. /* outbound */
  1791. card->qdio.out_qs =
  1792. kmalloc(card->qdio.no_out_queues *
  1793. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1794. if (!card->qdio.out_qs)
  1795. goto out_freepool;
  1796. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1797. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1798. GFP_KERNEL);
  1799. if (!card->qdio.out_qs[i])
  1800. goto out_freeoutq;
  1801. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1802. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1803. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1804. card->qdio.out_qs[i]->queue_no = i;
  1805. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1806. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1807. card->qdio.out_qs[i]->bufs[j].buffer =
  1808. &card->qdio.out_qs[i]->qdio_bufs[j];
  1809. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1810. skb_list);
  1811. lockdep_set_class(
  1812. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1813. &qdio_out_skb_queue_key);
  1814. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1815. }
  1816. }
  1817. return 0;
  1818. out_freeoutq:
  1819. while (i > 0)
  1820. kfree(card->qdio.out_qs[--i]);
  1821. kfree(card->qdio.out_qs);
  1822. card->qdio.out_qs = NULL;
  1823. out_freepool:
  1824. qeth_free_buffer_pool(card);
  1825. out_freeinq:
  1826. kfree(card->qdio.in_q);
  1827. card->qdio.in_q = NULL;
  1828. out_nomem:
  1829. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1830. return -ENOMEM;
  1831. }
  1832. static void qeth_create_qib_param_field(struct qeth_card *card,
  1833. char *param_field)
  1834. {
  1835. param_field[0] = _ascebc['P'];
  1836. param_field[1] = _ascebc['C'];
  1837. param_field[2] = _ascebc['I'];
  1838. param_field[3] = _ascebc['T'];
  1839. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1840. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1841. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1842. }
  1843. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1844. char *param_field)
  1845. {
  1846. param_field[16] = _ascebc['B'];
  1847. param_field[17] = _ascebc['L'];
  1848. param_field[18] = _ascebc['K'];
  1849. param_field[19] = _ascebc['T'];
  1850. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1851. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1852. *((unsigned int *) (&param_field[28])) =
  1853. card->info.blkt.inter_packet_jumbo;
  1854. }
  1855. static int qeth_qdio_activate(struct qeth_card *card)
  1856. {
  1857. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1858. return qdio_activate(CARD_DDEV(card), 0);
  1859. }
  1860. static int qeth_dm_act(struct qeth_card *card)
  1861. {
  1862. int rc;
  1863. struct qeth_cmd_buffer *iob;
  1864. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1865. iob = qeth_wait_for_buffer(&card->write);
  1866. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1867. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1868. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1869. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1870. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1871. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1872. return rc;
  1873. }
  1874. static int qeth_mpc_initialize(struct qeth_card *card)
  1875. {
  1876. int rc;
  1877. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1878. rc = qeth_issue_next_read(card);
  1879. if (rc) {
  1880. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1881. return rc;
  1882. }
  1883. rc = qeth_cm_enable(card);
  1884. if (rc) {
  1885. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1886. goto out_qdio;
  1887. }
  1888. rc = qeth_cm_setup(card);
  1889. if (rc) {
  1890. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1891. goto out_qdio;
  1892. }
  1893. rc = qeth_ulp_enable(card);
  1894. if (rc) {
  1895. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1896. goto out_qdio;
  1897. }
  1898. rc = qeth_ulp_setup(card);
  1899. if (rc) {
  1900. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1901. goto out_qdio;
  1902. }
  1903. rc = qeth_alloc_qdio_buffers(card);
  1904. if (rc) {
  1905. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1906. goto out_qdio;
  1907. }
  1908. rc = qeth_qdio_establish(card);
  1909. if (rc) {
  1910. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1911. qeth_free_qdio_buffers(card);
  1912. goto out_qdio;
  1913. }
  1914. rc = qeth_qdio_activate(card);
  1915. if (rc) {
  1916. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1917. goto out_qdio;
  1918. }
  1919. rc = qeth_dm_act(card);
  1920. if (rc) {
  1921. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1922. goto out_qdio;
  1923. }
  1924. return 0;
  1925. out_qdio:
  1926. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1927. return rc;
  1928. }
  1929. static void qeth_print_status_with_portname(struct qeth_card *card)
  1930. {
  1931. char dbf_text[15];
  1932. int i;
  1933. sprintf(dbf_text, "%s", card->info.portname + 1);
  1934. for (i = 0; i < 8; i++)
  1935. dbf_text[i] =
  1936. (char) _ebcasc[(__u8) dbf_text[i]];
  1937. dbf_text[8] = 0;
  1938. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1939. "with link type %s (portname: %s)\n",
  1940. CARD_RDEV_ID(card),
  1941. CARD_WDEV_ID(card),
  1942. CARD_DDEV_ID(card),
  1943. qeth_get_cardname(card),
  1944. (card->info.mcl_level[0]) ? " (level: " : "",
  1945. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1946. (card->info.mcl_level[0]) ? ")" : "",
  1947. qeth_get_cardname_short(card),
  1948. dbf_text);
  1949. }
  1950. static void qeth_print_status_no_portname(struct qeth_card *card)
  1951. {
  1952. if (card->info.portname[0])
  1953. PRINT_INFO("Device %s/%s/%s is a%s "
  1954. "card%s%s%s\nwith link type %s "
  1955. "(no portname needed by interface).\n",
  1956. CARD_RDEV_ID(card),
  1957. CARD_WDEV_ID(card),
  1958. CARD_DDEV_ID(card),
  1959. qeth_get_cardname(card),
  1960. (card->info.mcl_level[0]) ? " (level: " : "",
  1961. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1962. (card->info.mcl_level[0]) ? ")" : "",
  1963. qeth_get_cardname_short(card));
  1964. else
  1965. PRINT_INFO("Device %s/%s/%s is a%s "
  1966. "card%s%s%s\nwith link type %s.\n",
  1967. CARD_RDEV_ID(card),
  1968. CARD_WDEV_ID(card),
  1969. CARD_DDEV_ID(card),
  1970. qeth_get_cardname(card),
  1971. (card->info.mcl_level[0]) ? " (level: " : "",
  1972. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1973. (card->info.mcl_level[0]) ? ")" : "",
  1974. qeth_get_cardname_short(card));
  1975. }
  1976. void qeth_print_status_message(struct qeth_card *card)
  1977. {
  1978. switch (card->info.type) {
  1979. case QETH_CARD_TYPE_OSAE:
  1980. /* VM will use a non-zero first character
  1981. * to indicate a HiperSockets like reporting
  1982. * of the level OSA sets the first character to zero
  1983. * */
  1984. if (!card->info.mcl_level[0]) {
  1985. sprintf(card->info.mcl_level, "%02x%02x",
  1986. card->info.mcl_level[2],
  1987. card->info.mcl_level[3]);
  1988. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1989. break;
  1990. }
  1991. /* fallthrough */
  1992. case QETH_CARD_TYPE_IQD:
  1993. if (card->info.guestlan) {
  1994. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  1995. card->info.mcl_level[0]];
  1996. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  1997. card->info.mcl_level[1]];
  1998. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  1999. card->info.mcl_level[2]];
  2000. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2001. card->info.mcl_level[3]];
  2002. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2003. }
  2004. break;
  2005. default:
  2006. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2007. }
  2008. if (card->info.portname_required)
  2009. qeth_print_status_with_portname(card);
  2010. else
  2011. qeth_print_status_no_portname(card);
  2012. }
  2013. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2014. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2015. {
  2016. struct qeth_buffer_pool_entry *entry;
  2017. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2018. list_for_each_entry(entry,
  2019. &card->qdio.init_pool.entry_list, init_list) {
  2020. qeth_put_buffer_pool_entry(card, entry);
  2021. }
  2022. }
  2023. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2024. struct qeth_card *card)
  2025. {
  2026. struct list_head *plh;
  2027. struct qeth_buffer_pool_entry *entry;
  2028. int i, free;
  2029. struct page *page;
  2030. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2031. return NULL;
  2032. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2033. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2034. free = 1;
  2035. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2036. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2037. free = 0;
  2038. break;
  2039. }
  2040. }
  2041. if (free) {
  2042. list_del_init(&entry->list);
  2043. return entry;
  2044. }
  2045. }
  2046. /* no free buffer in pool so take first one and swap pages */
  2047. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2048. struct qeth_buffer_pool_entry, list);
  2049. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2050. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2051. page = alloc_page(GFP_ATOMIC);
  2052. if (!page) {
  2053. return NULL;
  2054. } else {
  2055. free_page((unsigned long)entry->elements[i]);
  2056. entry->elements[i] = page_address(page);
  2057. if (card->options.performance_stats)
  2058. card->perf_stats.sg_alloc_page_rx++;
  2059. }
  2060. }
  2061. }
  2062. list_del_init(&entry->list);
  2063. return entry;
  2064. }
  2065. static int qeth_init_input_buffer(struct qeth_card *card,
  2066. struct qeth_qdio_buffer *buf)
  2067. {
  2068. struct qeth_buffer_pool_entry *pool_entry;
  2069. int i;
  2070. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2071. if (!pool_entry)
  2072. return 1;
  2073. /*
  2074. * since the buffer is accessed only from the input_tasklet
  2075. * there shouldn't be a need to synchronize; also, since we use
  2076. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2077. * buffers
  2078. */
  2079. BUG_ON(!pool_entry);
  2080. buf->pool_entry = pool_entry;
  2081. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2082. buf->buffer->element[i].length = PAGE_SIZE;
  2083. buf->buffer->element[i].addr = pool_entry->elements[i];
  2084. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2085. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2086. else
  2087. buf->buffer->element[i].flags = 0;
  2088. }
  2089. return 0;
  2090. }
  2091. int qeth_init_qdio_queues(struct qeth_card *card)
  2092. {
  2093. int i, j;
  2094. int rc;
  2095. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2096. /* inbound queue */
  2097. memset(card->qdio.in_q->qdio_bufs, 0,
  2098. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2099. qeth_initialize_working_pool_list(card);
  2100. /*give only as many buffers to hardware as we have buffer pool entries*/
  2101. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2102. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2103. card->qdio.in_q->next_buf_to_init =
  2104. card->qdio.in_buf_pool.buf_count - 1;
  2105. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2106. card->qdio.in_buf_pool.buf_count - 1, NULL);
  2107. if (rc) {
  2108. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2109. return rc;
  2110. }
  2111. rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0);
  2112. if (rc) {
  2113. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2114. return rc;
  2115. }
  2116. /* outbound queue */
  2117. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2118. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2119. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2120. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2121. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2122. &card->qdio.out_qs[i]->bufs[j]);
  2123. }
  2124. card->qdio.out_qs[i]->card = card;
  2125. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2126. card->qdio.out_qs[i]->do_pack = 0;
  2127. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2128. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2129. atomic_set(&card->qdio.out_qs[i]->state,
  2130. QETH_OUT_Q_UNLOCKED);
  2131. }
  2132. return 0;
  2133. }
  2134. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2135. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2136. {
  2137. switch (link_type) {
  2138. case QETH_LINK_TYPE_HSTR:
  2139. return 2;
  2140. default:
  2141. return 1;
  2142. }
  2143. }
  2144. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2145. struct qeth_ipa_cmd *cmd, __u8 command,
  2146. enum qeth_prot_versions prot)
  2147. {
  2148. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2149. cmd->hdr.command = command;
  2150. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2151. cmd->hdr.seqno = card->seqno.ipa;
  2152. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2153. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2154. if (card->options.layer2)
  2155. cmd->hdr.prim_version_no = 2;
  2156. else
  2157. cmd->hdr.prim_version_no = 1;
  2158. cmd->hdr.param_count = 1;
  2159. cmd->hdr.prot_version = prot;
  2160. cmd->hdr.ipa_supported = 0;
  2161. cmd->hdr.ipa_enabled = 0;
  2162. }
  2163. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2164. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2165. {
  2166. struct qeth_cmd_buffer *iob;
  2167. struct qeth_ipa_cmd *cmd;
  2168. iob = qeth_wait_for_buffer(&card->write);
  2169. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2170. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2171. return iob;
  2172. }
  2173. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2174. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2175. char prot_type)
  2176. {
  2177. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2178. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2179. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2180. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2181. }
  2182. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2183. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2184. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2185. unsigned long),
  2186. void *reply_param)
  2187. {
  2188. int rc;
  2189. char prot_type;
  2190. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2191. if (card->options.layer2)
  2192. if (card->info.type == QETH_CARD_TYPE_OSN)
  2193. prot_type = QETH_PROT_OSN2;
  2194. else
  2195. prot_type = QETH_PROT_LAYER2;
  2196. else
  2197. prot_type = QETH_PROT_TCPIP;
  2198. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2199. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2200. iob, reply_cb, reply_param);
  2201. return rc;
  2202. }
  2203. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2204. static int qeth_send_startstoplan(struct qeth_card *card,
  2205. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2206. {
  2207. int rc;
  2208. struct qeth_cmd_buffer *iob;
  2209. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2210. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2211. return rc;
  2212. }
  2213. int qeth_send_startlan(struct qeth_card *card)
  2214. {
  2215. int rc;
  2216. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2217. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2218. return rc;
  2219. }
  2220. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2221. int qeth_send_stoplan(struct qeth_card *card)
  2222. {
  2223. int rc = 0;
  2224. /*
  2225. * TODO: according to the IPA format document page 14,
  2226. * TCP/IP (we!) never issue a STOPLAN
  2227. * is this right ?!?
  2228. */
  2229. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2230. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2231. return rc;
  2232. }
  2233. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2234. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2235. struct qeth_reply *reply, unsigned long data)
  2236. {
  2237. struct qeth_ipa_cmd *cmd;
  2238. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2239. cmd = (struct qeth_ipa_cmd *) data;
  2240. if (cmd->hdr.return_code == 0)
  2241. cmd->hdr.return_code =
  2242. cmd->data.setadapterparms.hdr.return_code;
  2243. return 0;
  2244. }
  2245. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2246. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2247. struct qeth_reply *reply, unsigned long data)
  2248. {
  2249. struct qeth_ipa_cmd *cmd;
  2250. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2251. cmd = (struct qeth_ipa_cmd *) data;
  2252. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2253. card->info.link_type =
  2254. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2255. card->options.adp.supported_funcs =
  2256. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2257. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2258. }
  2259. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2260. __u32 command, __u32 cmdlen)
  2261. {
  2262. struct qeth_cmd_buffer *iob;
  2263. struct qeth_ipa_cmd *cmd;
  2264. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2265. QETH_PROT_IPV4);
  2266. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2267. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2268. cmd->data.setadapterparms.hdr.command_code = command;
  2269. cmd->data.setadapterparms.hdr.used_total = 1;
  2270. cmd->data.setadapterparms.hdr.seq_no = 1;
  2271. return iob;
  2272. }
  2273. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2274. int qeth_query_setadapterparms(struct qeth_card *card)
  2275. {
  2276. int rc;
  2277. struct qeth_cmd_buffer *iob;
  2278. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2279. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2280. sizeof(struct qeth_ipacmd_setadpparms));
  2281. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2282. return rc;
  2283. }
  2284. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2285. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2286. unsigned int siga_error, const char *dbftext)
  2287. {
  2288. if (qdio_error || siga_error) {
  2289. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2290. QETH_DBF_TEXT(QERR, 2, dbftext);
  2291. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2292. buf->element[15].flags & 0xff);
  2293. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2294. buf->element[14].flags & 0xff);
  2295. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2296. QETH_DBF_TEXT_(QERR, 2, " serr=%X", siga_error);
  2297. return 1;
  2298. }
  2299. return 0;
  2300. }
  2301. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2302. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2303. {
  2304. struct qeth_qdio_q *queue = card->qdio.in_q;
  2305. int count;
  2306. int i;
  2307. int rc;
  2308. int newcount = 0;
  2309. count = (index < queue->next_buf_to_init)?
  2310. card->qdio.in_buf_pool.buf_count -
  2311. (queue->next_buf_to_init - index) :
  2312. card->qdio.in_buf_pool.buf_count -
  2313. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2314. /* only requeue at a certain threshold to avoid SIGAs */
  2315. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2316. for (i = queue->next_buf_to_init;
  2317. i < queue->next_buf_to_init + count; ++i) {
  2318. if (qeth_init_input_buffer(card,
  2319. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2320. break;
  2321. } else {
  2322. newcount++;
  2323. }
  2324. }
  2325. if (newcount < count) {
  2326. /* we are in memory shortage so we switch back to
  2327. traditional skb allocation and drop packages */
  2328. atomic_set(&card->force_alloc_skb, 3);
  2329. count = newcount;
  2330. } else {
  2331. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2332. }
  2333. /*
  2334. * according to old code it should be avoided to requeue all
  2335. * 128 buffers in order to benefit from PCI avoidance.
  2336. * this function keeps at least one buffer (the buffer at
  2337. * 'index') un-requeued -> this buffer is the first buffer that
  2338. * will be requeued the next time
  2339. */
  2340. if (card->options.performance_stats) {
  2341. card->perf_stats.inbound_do_qdio_cnt++;
  2342. card->perf_stats.inbound_do_qdio_start_time =
  2343. qeth_get_micros();
  2344. }
  2345. rc = do_QDIO(CARD_DDEV(card),
  2346. QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT,
  2347. 0, queue->next_buf_to_init, count, NULL);
  2348. if (card->options.performance_stats)
  2349. card->perf_stats.inbound_do_qdio_time +=
  2350. qeth_get_micros() -
  2351. card->perf_stats.inbound_do_qdio_start_time;
  2352. if (rc) {
  2353. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2354. "return %i (device %s).\n",
  2355. rc, CARD_DDEV_ID(card));
  2356. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2357. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2358. }
  2359. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2360. QDIO_MAX_BUFFERS_PER_Q;
  2361. }
  2362. }
  2363. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2364. static int qeth_handle_send_error(struct qeth_card *card,
  2365. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err,
  2366. unsigned int siga_err)
  2367. {
  2368. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2369. int cc = siga_err & 3;
  2370. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2371. qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr");
  2372. switch (cc) {
  2373. case 0:
  2374. if (qdio_err) {
  2375. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2376. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2377. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2378. (u16)qdio_err, (u8)sbalf15);
  2379. return QETH_SEND_ERROR_LINK_FAILURE;
  2380. }
  2381. return QETH_SEND_ERROR_NONE;
  2382. case 2:
  2383. if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) {
  2384. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2385. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2386. return QETH_SEND_ERROR_KICK_IT;
  2387. }
  2388. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2389. return QETH_SEND_ERROR_RETRY;
  2390. return QETH_SEND_ERROR_LINK_FAILURE;
  2391. /* look at qdio_error and sbalf 15 */
  2392. case 1:
  2393. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2394. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2395. return QETH_SEND_ERROR_LINK_FAILURE;
  2396. case 3:
  2397. default:
  2398. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2399. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2400. return QETH_SEND_ERROR_KICK_IT;
  2401. }
  2402. }
  2403. /*
  2404. * Switched to packing state if the number of used buffers on a queue
  2405. * reaches a certain limit.
  2406. */
  2407. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2408. {
  2409. if (!queue->do_pack) {
  2410. if (atomic_read(&queue->used_buffers)
  2411. >= QETH_HIGH_WATERMARK_PACK){
  2412. /* switch non-PACKING -> PACKING */
  2413. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2414. if (queue->card->options.performance_stats)
  2415. queue->card->perf_stats.sc_dp_p++;
  2416. queue->do_pack = 1;
  2417. }
  2418. }
  2419. }
  2420. /*
  2421. * Switches from packing to non-packing mode. If there is a packing
  2422. * buffer on the queue this buffer will be prepared to be flushed.
  2423. * In that case 1 is returned to inform the caller. If no buffer
  2424. * has to be flushed, zero is returned.
  2425. */
  2426. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2427. {
  2428. struct qeth_qdio_out_buffer *buffer;
  2429. int flush_count = 0;
  2430. if (queue->do_pack) {
  2431. if (atomic_read(&queue->used_buffers)
  2432. <= QETH_LOW_WATERMARK_PACK) {
  2433. /* switch PACKING -> non-PACKING */
  2434. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2435. if (queue->card->options.performance_stats)
  2436. queue->card->perf_stats.sc_p_dp++;
  2437. queue->do_pack = 0;
  2438. /* flush packing buffers */
  2439. buffer = &queue->bufs[queue->next_buf_to_fill];
  2440. if ((atomic_read(&buffer->state) ==
  2441. QETH_QDIO_BUF_EMPTY) &&
  2442. (buffer->next_element_to_fill > 0)) {
  2443. atomic_set(&buffer->state,
  2444. QETH_QDIO_BUF_PRIMED);
  2445. flush_count++;
  2446. queue->next_buf_to_fill =
  2447. (queue->next_buf_to_fill + 1) %
  2448. QDIO_MAX_BUFFERS_PER_Q;
  2449. }
  2450. }
  2451. }
  2452. return flush_count;
  2453. }
  2454. /*
  2455. * Called to flush a packing buffer if no more pci flags are on the queue.
  2456. * Checks if there is a packing buffer and prepares it to be flushed.
  2457. * In that case returns 1, otherwise zero.
  2458. */
  2459. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2460. {
  2461. struct qeth_qdio_out_buffer *buffer;
  2462. buffer = &queue->bufs[queue->next_buf_to_fill];
  2463. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2464. (buffer->next_element_to_fill > 0)) {
  2465. /* it's a packing buffer */
  2466. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2467. queue->next_buf_to_fill =
  2468. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2469. return 1;
  2470. }
  2471. return 0;
  2472. }
  2473. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int,
  2474. int index, int count)
  2475. {
  2476. struct qeth_qdio_out_buffer *buf;
  2477. int rc;
  2478. int i;
  2479. unsigned int qdio_flags;
  2480. for (i = index; i < index + count; ++i) {
  2481. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2482. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2483. SBAL_FLAGS_LAST_ENTRY;
  2484. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2485. continue;
  2486. if (!queue->do_pack) {
  2487. if ((atomic_read(&queue->used_buffers) >=
  2488. (QETH_HIGH_WATERMARK_PACK -
  2489. QETH_WATERMARK_PACK_FUZZ)) &&
  2490. !atomic_read(&queue->set_pci_flags_count)) {
  2491. /* it's likely that we'll go to packing
  2492. * mode soon */
  2493. atomic_inc(&queue->set_pci_flags_count);
  2494. buf->buffer->element[0].flags |= 0x40;
  2495. }
  2496. } else {
  2497. if (!atomic_read(&queue->set_pci_flags_count)) {
  2498. /*
  2499. * there's no outstanding PCI any more, so we
  2500. * have to request a PCI to be sure the the PCI
  2501. * will wake at some time in the future then we
  2502. * can flush packed buffers that might still be
  2503. * hanging around, which can happen if no
  2504. * further send was requested by the stack
  2505. */
  2506. atomic_inc(&queue->set_pci_flags_count);
  2507. buf->buffer->element[0].flags |= 0x40;
  2508. }
  2509. }
  2510. }
  2511. queue->card->dev->trans_start = jiffies;
  2512. if (queue->card->options.performance_stats) {
  2513. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2514. queue->card->perf_stats.outbound_do_qdio_start_time =
  2515. qeth_get_micros();
  2516. }
  2517. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2518. if (under_int)
  2519. qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT;
  2520. if (atomic_read(&queue->set_pci_flags_count))
  2521. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2522. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2523. queue->queue_no, index, count, NULL);
  2524. if (queue->card->options.performance_stats)
  2525. queue->card->perf_stats.outbound_do_qdio_time +=
  2526. qeth_get_micros() -
  2527. queue->card->perf_stats.outbound_do_qdio_start_time;
  2528. if (rc) {
  2529. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2530. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2531. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2532. queue->card->stats.tx_errors += count;
  2533. /* this must not happen under normal circumstances. if it
  2534. * happens something is really wrong -> recover */
  2535. qeth_schedule_recovery(queue->card);
  2536. return;
  2537. }
  2538. atomic_add(count, &queue->used_buffers);
  2539. if (queue->card->options.performance_stats)
  2540. queue->card->perf_stats.bufs_sent += count;
  2541. }
  2542. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2543. {
  2544. int index;
  2545. int flush_cnt = 0;
  2546. int q_was_packing = 0;
  2547. /*
  2548. * check if weed have to switch to non-packing mode or if
  2549. * we have to get a pci flag out on the queue
  2550. */
  2551. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2552. !atomic_read(&queue->set_pci_flags_count)) {
  2553. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2554. QETH_OUT_Q_UNLOCKED) {
  2555. /*
  2556. * If we get in here, there was no action in
  2557. * do_send_packet. So, we check if there is a
  2558. * packing buffer to be flushed here.
  2559. */
  2560. netif_stop_queue(queue->card->dev);
  2561. index = queue->next_buf_to_fill;
  2562. q_was_packing = queue->do_pack;
  2563. /* queue->do_pack may change */
  2564. barrier();
  2565. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2566. if (!flush_cnt &&
  2567. !atomic_read(&queue->set_pci_flags_count))
  2568. flush_cnt +=
  2569. qeth_flush_buffers_on_no_pci(queue);
  2570. if (queue->card->options.performance_stats &&
  2571. q_was_packing)
  2572. queue->card->perf_stats.bufs_sent_pack +=
  2573. flush_cnt;
  2574. if (flush_cnt)
  2575. qeth_flush_buffers(queue, 1, index, flush_cnt);
  2576. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2577. }
  2578. }
  2579. }
  2580. void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status,
  2581. unsigned int qdio_error, unsigned int siga_error,
  2582. unsigned int __queue, int first_element, int count,
  2583. unsigned long card_ptr)
  2584. {
  2585. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2586. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2587. struct qeth_qdio_out_buffer *buffer;
  2588. int i;
  2589. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2590. if (status & QDIO_STATUS_LOOK_FOR_ERROR) {
  2591. if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) {
  2592. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2593. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2594. QETH_DBF_TEXT_(TRACE, 2, "%08x", status);
  2595. netif_stop_queue(card->dev);
  2596. qeth_schedule_recovery(card);
  2597. return;
  2598. }
  2599. }
  2600. if (card->options.performance_stats) {
  2601. card->perf_stats.outbound_handler_cnt++;
  2602. card->perf_stats.outbound_handler_start_time =
  2603. qeth_get_micros();
  2604. }
  2605. for (i = first_element; i < (first_element + count); ++i) {
  2606. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2607. /*we only handle the KICK_IT error by doing a recovery */
  2608. if (qeth_handle_send_error(card, buffer,
  2609. qdio_error, siga_error)
  2610. == QETH_SEND_ERROR_KICK_IT){
  2611. netif_stop_queue(card->dev);
  2612. qeth_schedule_recovery(card);
  2613. return;
  2614. }
  2615. qeth_clear_output_buffer(queue, buffer);
  2616. }
  2617. atomic_sub(count, &queue->used_buffers);
  2618. /* check if we need to do something on this outbound queue */
  2619. if (card->info.type != QETH_CARD_TYPE_IQD)
  2620. qeth_check_outbound_queue(queue);
  2621. netif_wake_queue(queue->card->dev);
  2622. if (card->options.performance_stats)
  2623. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2624. card->perf_stats.outbound_handler_start_time;
  2625. }
  2626. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2627. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2628. {
  2629. int cast_type = RTN_UNSPEC;
  2630. if (card->info.type == QETH_CARD_TYPE_OSN)
  2631. return cast_type;
  2632. if (skb->dst && skb->dst->neighbour) {
  2633. cast_type = skb->dst->neighbour->type;
  2634. if ((cast_type == RTN_BROADCAST) ||
  2635. (cast_type == RTN_MULTICAST) ||
  2636. (cast_type == RTN_ANYCAST))
  2637. return cast_type;
  2638. else
  2639. return RTN_UNSPEC;
  2640. }
  2641. /* try something else */
  2642. if (skb->protocol == ETH_P_IPV6)
  2643. return (skb_network_header(skb)[24] == 0xff) ?
  2644. RTN_MULTICAST : 0;
  2645. else if (skb->protocol == ETH_P_IP)
  2646. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2647. RTN_MULTICAST : 0;
  2648. /* ... */
  2649. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2650. return RTN_BROADCAST;
  2651. else {
  2652. u16 hdr_mac;
  2653. hdr_mac = *((u16 *)skb->data);
  2654. /* tr multicast? */
  2655. switch (card->info.link_type) {
  2656. case QETH_LINK_TYPE_HSTR:
  2657. case QETH_LINK_TYPE_LANE_TR:
  2658. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2659. (hdr_mac == QETH_TR_MAC_C))
  2660. return RTN_MULTICAST;
  2661. break;
  2662. /* eth or so multicast? */
  2663. default:
  2664. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2665. (hdr_mac == QETH_ETH_MAC_V6))
  2666. return RTN_MULTICAST;
  2667. }
  2668. }
  2669. return cast_type;
  2670. }
  2671. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2672. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2673. int ipv, int cast_type)
  2674. {
  2675. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2676. return card->qdio.default_out_queue;
  2677. switch (card->qdio.no_out_queues) {
  2678. case 4:
  2679. if (cast_type && card->info.is_multicast_different)
  2680. return card->info.is_multicast_different &
  2681. (card->qdio.no_out_queues - 1);
  2682. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2683. const u8 tos = ip_hdr(skb)->tos;
  2684. if (card->qdio.do_prio_queueing ==
  2685. QETH_PRIO_Q_ING_TOS) {
  2686. if (tos & IP_TOS_NOTIMPORTANT)
  2687. return 3;
  2688. if (tos & IP_TOS_HIGHRELIABILITY)
  2689. return 2;
  2690. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2691. return 1;
  2692. if (tos & IP_TOS_LOWDELAY)
  2693. return 0;
  2694. }
  2695. if (card->qdio.do_prio_queueing ==
  2696. QETH_PRIO_Q_ING_PREC)
  2697. return 3 - (tos >> 6);
  2698. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2699. /* TODO: IPv6!!! */
  2700. }
  2701. return card->qdio.default_out_queue;
  2702. case 1: /* fallthrough for single-out-queue 1920-device */
  2703. default:
  2704. return card->qdio.default_out_queue;
  2705. }
  2706. }
  2707. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2708. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2709. struct sk_buff *skb, int elems)
  2710. {
  2711. int elements_needed = 0;
  2712. if (skb_shinfo(skb)->nr_frags > 0)
  2713. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2714. if (elements_needed == 0)
  2715. elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
  2716. + skb->len) >> PAGE_SHIFT);
  2717. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2718. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2719. "(Number=%d / Length=%d). Discarded.\n",
  2720. (elements_needed+elems), skb->len);
  2721. return 0;
  2722. }
  2723. return elements_needed;
  2724. }
  2725. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2726. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2727. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill)
  2728. {
  2729. int length = skb->len;
  2730. int length_here;
  2731. int element;
  2732. char *data;
  2733. int first_lap ;
  2734. element = *next_element_to_fill;
  2735. data = skb->data;
  2736. first_lap = (is_tso == 0 ? 1 : 0);
  2737. while (length > 0) {
  2738. /* length_here is the remaining amount of data in this page */
  2739. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2740. if (length < length_here)
  2741. length_here = length;
  2742. buffer->element[element].addr = data;
  2743. buffer->element[element].length = length_here;
  2744. length -= length_here;
  2745. if (!length) {
  2746. if (first_lap)
  2747. buffer->element[element].flags = 0;
  2748. else
  2749. buffer->element[element].flags =
  2750. SBAL_FLAGS_LAST_FRAG;
  2751. } else {
  2752. if (first_lap)
  2753. buffer->element[element].flags =
  2754. SBAL_FLAGS_FIRST_FRAG;
  2755. else
  2756. buffer->element[element].flags =
  2757. SBAL_FLAGS_MIDDLE_FRAG;
  2758. }
  2759. data += length_here;
  2760. element++;
  2761. first_lap = 0;
  2762. }
  2763. *next_element_to_fill = element;
  2764. }
  2765. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2766. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
  2767. {
  2768. struct qdio_buffer *buffer;
  2769. struct qeth_hdr_tso *hdr;
  2770. int flush_cnt = 0, hdr_len, large_send = 0;
  2771. buffer = buf->buffer;
  2772. atomic_inc(&skb->users);
  2773. skb_queue_tail(&buf->skb_list, skb);
  2774. hdr = (struct qeth_hdr_tso *) skb->data;
  2775. /*check first on TSO ....*/
  2776. if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2777. int element = buf->next_element_to_fill;
  2778. hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
  2779. /*fill first buffer entry only with header information */
  2780. buffer->element[element].addr = skb->data;
  2781. buffer->element[element].length = hdr_len;
  2782. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2783. buf->next_element_to_fill++;
  2784. skb->data += hdr_len;
  2785. skb->len -= hdr_len;
  2786. large_send = 1;
  2787. }
  2788. if (skb_shinfo(skb)->nr_frags == 0)
  2789. __qeth_fill_buffer(skb, buffer, large_send,
  2790. (int *)&buf->next_element_to_fill);
  2791. else
  2792. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2793. (int *)&buf->next_element_to_fill);
  2794. if (!queue->do_pack) {
  2795. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2796. /* set state to PRIMED -> will be flushed */
  2797. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2798. flush_cnt = 1;
  2799. } else {
  2800. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2801. if (queue->card->options.performance_stats)
  2802. queue->card->perf_stats.skbs_sent_pack++;
  2803. if (buf->next_element_to_fill >=
  2804. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2805. /*
  2806. * packed buffer if full -> set state PRIMED
  2807. * -> will be flushed
  2808. */
  2809. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2810. flush_cnt = 1;
  2811. }
  2812. }
  2813. return flush_cnt;
  2814. }
  2815. int qeth_do_send_packet_fast(struct qeth_card *card,
  2816. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2817. struct qeth_hdr *hdr, int elements_needed,
  2818. struct qeth_eddp_context *ctx)
  2819. {
  2820. struct qeth_qdio_out_buffer *buffer;
  2821. int buffers_needed = 0;
  2822. int flush_cnt = 0;
  2823. int index;
  2824. /* spin until we get the queue ... */
  2825. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2826. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2827. /* ... now we've got the queue */
  2828. index = queue->next_buf_to_fill;
  2829. buffer = &queue->bufs[queue->next_buf_to_fill];
  2830. /*
  2831. * check if buffer is empty to make sure that we do not 'overtake'
  2832. * ourselves and try to fill a buffer that is already primed
  2833. */
  2834. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2835. goto out;
  2836. if (ctx == NULL)
  2837. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2838. QDIO_MAX_BUFFERS_PER_Q;
  2839. else {
  2840. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2841. ctx);
  2842. if (buffers_needed < 0)
  2843. goto out;
  2844. queue->next_buf_to_fill =
  2845. (queue->next_buf_to_fill + buffers_needed) %
  2846. QDIO_MAX_BUFFERS_PER_Q;
  2847. }
  2848. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2849. if (ctx == NULL) {
  2850. qeth_fill_buffer(queue, buffer, skb);
  2851. qeth_flush_buffers(queue, 0, index, 1);
  2852. } else {
  2853. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2854. WARN_ON(buffers_needed != flush_cnt);
  2855. qeth_flush_buffers(queue, 0, index, flush_cnt);
  2856. }
  2857. return 0;
  2858. out:
  2859. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2860. return -EBUSY;
  2861. }
  2862. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2863. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2864. struct sk_buff *skb, struct qeth_hdr *hdr,
  2865. int elements_needed, struct qeth_eddp_context *ctx)
  2866. {
  2867. struct qeth_qdio_out_buffer *buffer;
  2868. int start_index;
  2869. int flush_count = 0;
  2870. int do_pack = 0;
  2871. int tmp;
  2872. int rc = 0;
  2873. /* spin until we get the queue ... */
  2874. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2875. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2876. start_index = queue->next_buf_to_fill;
  2877. buffer = &queue->bufs[queue->next_buf_to_fill];
  2878. /*
  2879. * check if buffer is empty to make sure that we do not 'overtake'
  2880. * ourselves and try to fill a buffer that is already primed
  2881. */
  2882. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2883. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2884. return -EBUSY;
  2885. }
  2886. /* check if we need to switch packing state of this queue */
  2887. qeth_switch_to_packing_if_needed(queue);
  2888. if (queue->do_pack) {
  2889. do_pack = 1;
  2890. if (ctx == NULL) {
  2891. /* does packet fit in current buffer? */
  2892. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2893. buffer->next_element_to_fill) < elements_needed) {
  2894. /* ... no -> set state PRIMED */
  2895. atomic_set(&buffer->state,
  2896. QETH_QDIO_BUF_PRIMED);
  2897. flush_count++;
  2898. queue->next_buf_to_fill =
  2899. (queue->next_buf_to_fill + 1) %
  2900. QDIO_MAX_BUFFERS_PER_Q;
  2901. buffer = &queue->bufs[queue->next_buf_to_fill];
  2902. /* we did a step forward, so check buffer state
  2903. * again */
  2904. if (atomic_read(&buffer->state) !=
  2905. QETH_QDIO_BUF_EMPTY){
  2906. qeth_flush_buffers(queue, 0,
  2907. start_index, flush_count);
  2908. atomic_set(&queue->state,
  2909. QETH_OUT_Q_UNLOCKED);
  2910. return -EBUSY;
  2911. }
  2912. }
  2913. } else {
  2914. /* check if we have enough elements (including following
  2915. * free buffers) to handle eddp context */
  2916. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2917. < 0) {
  2918. rc = -EBUSY;
  2919. goto out;
  2920. }
  2921. }
  2922. }
  2923. if (ctx == NULL)
  2924. tmp = qeth_fill_buffer(queue, buffer, skb);
  2925. else {
  2926. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2927. queue->next_buf_to_fill);
  2928. if (tmp < 0) {
  2929. rc = -EBUSY;
  2930. goto out;
  2931. }
  2932. }
  2933. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2934. QDIO_MAX_BUFFERS_PER_Q;
  2935. flush_count += tmp;
  2936. out:
  2937. if (flush_count)
  2938. qeth_flush_buffers(queue, 0, start_index, flush_count);
  2939. else if (!atomic_read(&queue->set_pci_flags_count))
  2940. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2941. /*
  2942. * queue->state will go from LOCKED -> UNLOCKED or from
  2943. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2944. * (switch packing state or flush buffer to get another pci flag out).
  2945. * In that case we will enter this loop
  2946. */
  2947. while (atomic_dec_return(&queue->state)) {
  2948. flush_count = 0;
  2949. start_index = queue->next_buf_to_fill;
  2950. /* check if we can go back to non-packing state */
  2951. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2952. /*
  2953. * check if we need to flush a packing buffer to get a pci
  2954. * flag out on the queue
  2955. */
  2956. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2957. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2958. if (flush_count)
  2959. qeth_flush_buffers(queue, 0, start_index, flush_count);
  2960. }
  2961. /* at this point the queue is UNLOCKED again */
  2962. if (queue->card->options.performance_stats && do_pack)
  2963. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2964. return rc;
  2965. }
  2966. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2967. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2968. struct qeth_reply *reply, unsigned long data)
  2969. {
  2970. struct qeth_ipa_cmd *cmd;
  2971. struct qeth_ipacmd_setadpparms *setparms;
  2972. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2973. cmd = (struct qeth_ipa_cmd *) data;
  2974. setparms = &(cmd->data.setadapterparms);
  2975. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2976. if (cmd->hdr.return_code) {
  2977. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2978. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2979. }
  2980. card->info.promisc_mode = setparms->data.mode;
  2981. return 0;
  2982. }
  2983. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2984. {
  2985. enum qeth_ipa_promisc_modes mode;
  2986. struct net_device *dev = card->dev;
  2987. struct qeth_cmd_buffer *iob;
  2988. struct qeth_ipa_cmd *cmd;
  2989. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2990. if (((dev->flags & IFF_PROMISC) &&
  2991. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2992. (!(dev->flags & IFF_PROMISC) &&
  2993. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2994. return;
  2995. mode = SET_PROMISC_MODE_OFF;
  2996. if (dev->flags & IFF_PROMISC)
  2997. mode = SET_PROMISC_MODE_ON;
  2998. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2999. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3000. sizeof(struct qeth_ipacmd_setadpparms));
  3001. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3002. cmd->data.setadapterparms.data.mode = mode;
  3003. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3004. }
  3005. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3006. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3007. {
  3008. struct qeth_card *card;
  3009. char dbf_text[15];
  3010. card = netdev_priv(dev);
  3011. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3012. sprintf(dbf_text, "%8x", new_mtu);
  3013. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3014. if (new_mtu < 64)
  3015. return -EINVAL;
  3016. if (new_mtu > 65535)
  3017. return -EINVAL;
  3018. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3019. (!qeth_mtu_is_valid(card, new_mtu)))
  3020. return -EINVAL;
  3021. dev->mtu = new_mtu;
  3022. return 0;
  3023. }
  3024. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3025. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3026. {
  3027. struct qeth_card *card;
  3028. card = netdev_priv(dev);
  3029. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3030. return &card->stats;
  3031. }
  3032. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3033. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3034. struct qeth_reply *reply, unsigned long data)
  3035. {
  3036. struct qeth_ipa_cmd *cmd;
  3037. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3038. cmd = (struct qeth_ipa_cmd *) data;
  3039. if (!card->options.layer2 ||
  3040. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3041. memcpy(card->dev->dev_addr,
  3042. &cmd->data.setadapterparms.data.change_addr.addr,
  3043. OSA_ADDR_LEN);
  3044. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3045. }
  3046. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3047. return 0;
  3048. }
  3049. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3050. {
  3051. int rc;
  3052. struct qeth_cmd_buffer *iob;
  3053. struct qeth_ipa_cmd *cmd;
  3054. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3055. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3056. sizeof(struct qeth_ipacmd_setadpparms));
  3057. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3058. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3059. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3060. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3061. card->dev->dev_addr, OSA_ADDR_LEN);
  3062. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3063. NULL);
  3064. return rc;
  3065. }
  3066. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3067. void qeth_tx_timeout(struct net_device *dev)
  3068. {
  3069. struct qeth_card *card;
  3070. card = netdev_priv(dev);
  3071. card->stats.tx_errors++;
  3072. qeth_schedule_recovery(card);
  3073. }
  3074. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3075. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3076. {
  3077. struct qeth_card *card = netdev_priv(dev);
  3078. int rc = 0;
  3079. switch (regnum) {
  3080. case MII_BMCR: /* Basic mode control register */
  3081. rc = BMCR_FULLDPLX;
  3082. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3083. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3084. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3085. rc |= BMCR_SPEED100;
  3086. break;
  3087. case MII_BMSR: /* Basic mode status register */
  3088. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3089. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3090. BMSR_100BASE4;
  3091. break;
  3092. case MII_PHYSID1: /* PHYS ID 1 */
  3093. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3094. dev->dev_addr[2];
  3095. rc = (rc >> 5) & 0xFFFF;
  3096. break;
  3097. case MII_PHYSID2: /* PHYS ID 2 */
  3098. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3099. break;
  3100. case MII_ADVERTISE: /* Advertisement control reg */
  3101. rc = ADVERTISE_ALL;
  3102. break;
  3103. case MII_LPA: /* Link partner ability reg */
  3104. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3105. LPA_100BASE4 | LPA_LPACK;
  3106. break;
  3107. case MII_EXPANSION: /* Expansion register */
  3108. break;
  3109. case MII_DCOUNTER: /* disconnect counter */
  3110. break;
  3111. case MII_FCSCOUNTER: /* false carrier counter */
  3112. break;
  3113. case MII_NWAYTEST: /* N-way auto-neg test register */
  3114. break;
  3115. case MII_RERRCOUNTER: /* rx error counter */
  3116. rc = card->stats.rx_errors;
  3117. break;
  3118. case MII_SREVISION: /* silicon revision */
  3119. break;
  3120. case MII_RESV1: /* reserved 1 */
  3121. break;
  3122. case MII_LBRERROR: /* loopback, rx, bypass error */
  3123. break;
  3124. case MII_PHYADDR: /* physical address */
  3125. break;
  3126. case MII_RESV2: /* reserved 2 */
  3127. break;
  3128. case MII_TPISTATUS: /* TPI status for 10mbps */
  3129. break;
  3130. case MII_NCONFIG: /* network interface config */
  3131. break;
  3132. default:
  3133. break;
  3134. }
  3135. return rc;
  3136. }
  3137. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3138. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3139. struct qeth_cmd_buffer *iob, int len,
  3140. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3141. unsigned long),
  3142. void *reply_param)
  3143. {
  3144. u16 s1, s2;
  3145. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3146. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3147. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3148. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3149. /* adjust PDU length fields in IPA_PDU_HEADER */
  3150. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3151. s2 = (u32) len;
  3152. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3153. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3154. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3155. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3156. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3157. reply_cb, reply_param);
  3158. }
  3159. static int qeth_snmp_command_cb(struct qeth_card *card,
  3160. struct qeth_reply *reply, unsigned long sdata)
  3161. {
  3162. struct qeth_ipa_cmd *cmd;
  3163. struct qeth_arp_query_info *qinfo;
  3164. struct qeth_snmp_cmd *snmp;
  3165. unsigned char *data;
  3166. __u16 data_len;
  3167. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3168. cmd = (struct qeth_ipa_cmd *) sdata;
  3169. data = (unsigned char *)((char *)cmd - reply->offset);
  3170. qinfo = (struct qeth_arp_query_info *) reply->param;
  3171. snmp = &cmd->data.setadapterparms.data.snmp;
  3172. if (cmd->hdr.return_code) {
  3173. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3174. return 0;
  3175. }
  3176. if (cmd->data.setadapterparms.hdr.return_code) {
  3177. cmd->hdr.return_code =
  3178. cmd->data.setadapterparms.hdr.return_code;
  3179. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3180. return 0;
  3181. }
  3182. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3183. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3184. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3185. else
  3186. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3187. /* check if there is enough room in userspace */
  3188. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3189. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3190. cmd->hdr.return_code = -ENOMEM;
  3191. return 0;
  3192. }
  3193. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3194. cmd->data.setadapterparms.hdr.used_total);
  3195. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3196. cmd->data.setadapterparms.hdr.seq_no);
  3197. /*copy entries to user buffer*/
  3198. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3199. memcpy(qinfo->udata + qinfo->udata_offset,
  3200. (char *)snmp,
  3201. data_len + offsetof(struct qeth_snmp_cmd, data));
  3202. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3203. } else {
  3204. memcpy(qinfo->udata + qinfo->udata_offset,
  3205. (char *)&snmp->request, data_len);
  3206. }
  3207. qinfo->udata_offset += data_len;
  3208. /* check if all replies received ... */
  3209. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3210. cmd->data.setadapterparms.hdr.used_total);
  3211. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3212. cmd->data.setadapterparms.hdr.seq_no);
  3213. if (cmd->data.setadapterparms.hdr.seq_no <
  3214. cmd->data.setadapterparms.hdr.used_total)
  3215. return 1;
  3216. return 0;
  3217. }
  3218. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3219. {
  3220. struct qeth_cmd_buffer *iob;
  3221. struct qeth_ipa_cmd *cmd;
  3222. struct qeth_snmp_ureq *ureq;
  3223. int req_len;
  3224. struct qeth_arp_query_info qinfo = {0, };
  3225. int rc = 0;
  3226. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3227. if (card->info.guestlan)
  3228. return -EOPNOTSUPP;
  3229. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3230. (!card->options.layer2)) {
  3231. return -EOPNOTSUPP;
  3232. }
  3233. /* skip 4 bytes (data_len struct member) to get req_len */
  3234. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3235. return -EFAULT;
  3236. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3237. if (!ureq) {
  3238. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3239. return -ENOMEM;
  3240. }
  3241. if (copy_from_user(ureq, udata,
  3242. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3243. kfree(ureq);
  3244. return -EFAULT;
  3245. }
  3246. qinfo.udata_len = ureq->hdr.data_len;
  3247. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3248. if (!qinfo.udata) {
  3249. kfree(ureq);
  3250. return -ENOMEM;
  3251. }
  3252. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3253. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3254. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3255. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3256. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3257. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3258. qeth_snmp_command_cb, (void *)&qinfo);
  3259. if (rc)
  3260. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3261. QETH_CARD_IFNAME(card), rc);
  3262. else {
  3263. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3264. rc = -EFAULT;
  3265. }
  3266. kfree(ureq);
  3267. kfree(qinfo.udata);
  3268. return rc;
  3269. }
  3270. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3271. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3272. {
  3273. switch (card->info.type) {
  3274. case QETH_CARD_TYPE_IQD:
  3275. return 2;
  3276. default:
  3277. return 0;
  3278. }
  3279. }
  3280. static int qeth_qdio_establish(struct qeth_card *card)
  3281. {
  3282. struct qdio_initialize init_data;
  3283. char *qib_param_field;
  3284. struct qdio_buffer **in_sbal_ptrs;
  3285. struct qdio_buffer **out_sbal_ptrs;
  3286. int i, j, k;
  3287. int rc = 0;
  3288. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3289. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3290. GFP_KERNEL);
  3291. if (!qib_param_field)
  3292. return -ENOMEM;
  3293. qeth_create_qib_param_field(card, qib_param_field);
  3294. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3295. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3296. GFP_KERNEL);
  3297. if (!in_sbal_ptrs) {
  3298. kfree(qib_param_field);
  3299. return -ENOMEM;
  3300. }
  3301. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3302. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3303. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3304. out_sbal_ptrs =
  3305. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3306. sizeof(void *), GFP_KERNEL);
  3307. if (!out_sbal_ptrs) {
  3308. kfree(in_sbal_ptrs);
  3309. kfree(qib_param_field);
  3310. return -ENOMEM;
  3311. }
  3312. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3313. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3314. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3315. card->qdio.out_qs[i]->bufs[j].buffer);
  3316. }
  3317. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3318. init_data.cdev = CARD_DDEV(card);
  3319. init_data.q_format = qeth_get_qdio_q_format(card);
  3320. init_data.qib_param_field_format = 0;
  3321. init_data.qib_param_field = qib_param_field;
  3322. init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD;
  3323. init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD;
  3324. init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD;
  3325. init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD;
  3326. init_data.no_input_qs = 1;
  3327. init_data.no_output_qs = card->qdio.no_out_queues;
  3328. init_data.input_handler = card->discipline.input_handler;
  3329. init_data.output_handler = card->discipline.output_handler;
  3330. init_data.int_parm = (unsigned long) card;
  3331. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3332. QDIO_OUTBOUND_0COPY_SBALS |
  3333. QDIO_USE_OUTBOUND_PCIS;
  3334. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3335. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3336. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3337. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3338. rc = qdio_initialize(&init_data);
  3339. if (rc)
  3340. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3341. }
  3342. kfree(out_sbal_ptrs);
  3343. kfree(in_sbal_ptrs);
  3344. kfree(qib_param_field);
  3345. return rc;
  3346. }
  3347. static void qeth_core_free_card(struct qeth_card *card)
  3348. {
  3349. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3350. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3351. qeth_clean_channel(&card->read);
  3352. qeth_clean_channel(&card->write);
  3353. if (card->dev)
  3354. free_netdev(card->dev);
  3355. kfree(card->ip_tbd_list);
  3356. qeth_free_qdio_buffers(card);
  3357. kfree(card);
  3358. }
  3359. static struct ccw_device_id qeth_ids[] = {
  3360. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3361. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3362. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3363. {},
  3364. };
  3365. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3366. static struct ccw_driver qeth_ccw_driver = {
  3367. .name = "qeth",
  3368. .ids = qeth_ids,
  3369. .probe = ccwgroup_probe_ccwdev,
  3370. .remove = ccwgroup_remove_ccwdev,
  3371. };
  3372. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3373. unsigned long driver_id)
  3374. {
  3375. return ccwgroup_create_from_string(root_dev, driver_id,
  3376. &qeth_ccw_driver, 3, buf);
  3377. }
  3378. int qeth_core_hardsetup_card(struct qeth_card *card)
  3379. {
  3380. int retries = 3;
  3381. int mpno;
  3382. int rc;
  3383. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3384. atomic_set(&card->force_alloc_skb, 0);
  3385. retry:
  3386. if (retries < 3) {
  3387. PRINT_WARN("Retrying to do IDX activates.\n");
  3388. ccw_device_set_offline(CARD_DDEV(card));
  3389. ccw_device_set_offline(CARD_WDEV(card));
  3390. ccw_device_set_offline(CARD_RDEV(card));
  3391. ccw_device_set_online(CARD_RDEV(card));
  3392. ccw_device_set_online(CARD_WDEV(card));
  3393. ccw_device_set_online(CARD_DDEV(card));
  3394. }
  3395. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3396. if (rc == -ERESTARTSYS) {
  3397. QETH_DBF_TEXT(SETUP, 2, "break1");
  3398. return rc;
  3399. } else if (rc) {
  3400. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3401. if (--retries < 0)
  3402. goto out;
  3403. else
  3404. goto retry;
  3405. }
  3406. rc = qeth_get_unitaddr(card);
  3407. if (rc) {
  3408. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3409. return rc;
  3410. }
  3411. mpno = qdio_get_ssqd_pct(CARD_DDEV(card));
  3412. if (mpno)
  3413. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3414. if (card->info.portno > mpno) {
  3415. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3416. "\n.", CARD_BUS_ID(card), card->info.portno);
  3417. rc = -ENODEV;
  3418. goto out;
  3419. }
  3420. qeth_init_tokens(card);
  3421. qeth_init_func_level(card);
  3422. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3423. if (rc == -ERESTARTSYS) {
  3424. QETH_DBF_TEXT(SETUP, 2, "break2");
  3425. return rc;
  3426. } else if (rc) {
  3427. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3428. if (--retries < 0)
  3429. goto out;
  3430. else
  3431. goto retry;
  3432. }
  3433. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3434. if (rc == -ERESTARTSYS) {
  3435. QETH_DBF_TEXT(SETUP, 2, "break3");
  3436. return rc;
  3437. } else if (rc) {
  3438. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3439. if (--retries < 0)
  3440. goto out;
  3441. else
  3442. goto retry;
  3443. }
  3444. rc = qeth_mpc_initialize(card);
  3445. if (rc) {
  3446. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3447. goto out;
  3448. }
  3449. return 0;
  3450. out:
  3451. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3452. return rc;
  3453. }
  3454. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3455. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3456. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3457. {
  3458. struct page *page = virt_to_page(element->addr);
  3459. if (*pskb == NULL) {
  3460. /* the upper protocol layers assume that there is data in the
  3461. * skb itself. Copy a small amount (64 bytes) to make them
  3462. * happy. */
  3463. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3464. if (!(*pskb))
  3465. return -ENOMEM;
  3466. skb_reserve(*pskb, ETH_HLEN);
  3467. if (data_len <= 64) {
  3468. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3469. data_len);
  3470. } else {
  3471. get_page(page);
  3472. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3473. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3474. data_len - 64);
  3475. (*pskb)->data_len += data_len - 64;
  3476. (*pskb)->len += data_len - 64;
  3477. (*pskb)->truesize += data_len - 64;
  3478. (*pfrag)++;
  3479. }
  3480. } else {
  3481. get_page(page);
  3482. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3483. (*pskb)->data_len += data_len;
  3484. (*pskb)->len += data_len;
  3485. (*pskb)->truesize += data_len;
  3486. (*pfrag)++;
  3487. }
  3488. return 0;
  3489. }
  3490. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3491. struct qdio_buffer *buffer,
  3492. struct qdio_buffer_element **__element, int *__offset,
  3493. struct qeth_hdr **hdr)
  3494. {
  3495. struct qdio_buffer_element *element = *__element;
  3496. int offset = *__offset;
  3497. struct sk_buff *skb = NULL;
  3498. int skb_len;
  3499. void *data_ptr;
  3500. int data_len;
  3501. int headroom = 0;
  3502. int use_rx_sg = 0;
  3503. int frag = 0;
  3504. /* qeth_hdr must not cross element boundaries */
  3505. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3506. if (qeth_is_last_sbale(element))
  3507. return NULL;
  3508. element++;
  3509. offset = 0;
  3510. if (element->length < sizeof(struct qeth_hdr))
  3511. return NULL;
  3512. }
  3513. *hdr = element->addr + offset;
  3514. offset += sizeof(struct qeth_hdr);
  3515. if (card->options.layer2) {
  3516. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3517. skb_len = (*hdr)->hdr.osn.pdu_length;
  3518. headroom = sizeof(struct qeth_hdr);
  3519. } else {
  3520. skb_len = (*hdr)->hdr.l2.pkt_length;
  3521. }
  3522. } else {
  3523. skb_len = (*hdr)->hdr.l3.length;
  3524. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3525. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3526. headroom = TR_HLEN;
  3527. else
  3528. headroom = ETH_HLEN;
  3529. }
  3530. if (!skb_len)
  3531. return NULL;
  3532. if ((skb_len >= card->options.rx_sg_cb) &&
  3533. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3534. (!atomic_read(&card->force_alloc_skb))) {
  3535. use_rx_sg = 1;
  3536. } else {
  3537. skb = dev_alloc_skb(skb_len + headroom);
  3538. if (!skb)
  3539. goto no_mem;
  3540. if (headroom)
  3541. skb_reserve(skb, headroom);
  3542. }
  3543. data_ptr = element->addr + offset;
  3544. while (skb_len) {
  3545. data_len = min(skb_len, (int)(element->length - offset));
  3546. if (data_len) {
  3547. if (use_rx_sg) {
  3548. if (qeth_create_skb_frag(element, &skb, offset,
  3549. &frag, data_len))
  3550. goto no_mem;
  3551. } else {
  3552. memcpy(skb_put(skb, data_len), data_ptr,
  3553. data_len);
  3554. }
  3555. }
  3556. skb_len -= data_len;
  3557. if (skb_len) {
  3558. if (qeth_is_last_sbale(element)) {
  3559. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3560. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3561. CARD_BUS_ID(card));
  3562. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3563. QETH_DBF_TEXT_(QERR, 2, "%s",
  3564. CARD_BUS_ID(card));
  3565. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3566. dev_kfree_skb_any(skb);
  3567. card->stats.rx_errors++;
  3568. return NULL;
  3569. }
  3570. element++;
  3571. offset = 0;
  3572. data_ptr = element->addr;
  3573. } else {
  3574. offset += data_len;
  3575. }
  3576. }
  3577. *__element = element;
  3578. *__offset = offset;
  3579. if (use_rx_sg && card->options.performance_stats) {
  3580. card->perf_stats.sg_skbs_rx++;
  3581. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3582. }
  3583. return skb;
  3584. no_mem:
  3585. if (net_ratelimit()) {
  3586. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3587. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3588. }
  3589. card->stats.rx_dropped++;
  3590. return NULL;
  3591. }
  3592. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3593. static void qeth_unregister_dbf_views(void)
  3594. {
  3595. int x;
  3596. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3597. debug_unregister(qeth_dbf[x].id);
  3598. qeth_dbf[x].id = NULL;
  3599. }
  3600. }
  3601. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3602. {
  3603. char dbf_txt_buf[32];
  3604. va_list args;
  3605. if (level > (qeth_dbf[dbf_nix].id)->level)
  3606. return;
  3607. va_start(args, fmt);
  3608. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3609. va_end(args);
  3610. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3611. }
  3612. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3613. static int qeth_register_dbf_views(void)
  3614. {
  3615. int ret;
  3616. int x;
  3617. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3618. /* register the areas */
  3619. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3620. qeth_dbf[x].pages,
  3621. qeth_dbf[x].areas,
  3622. qeth_dbf[x].len);
  3623. if (qeth_dbf[x].id == NULL) {
  3624. qeth_unregister_dbf_views();
  3625. return -ENOMEM;
  3626. }
  3627. /* register a view */
  3628. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3629. if (ret) {
  3630. qeth_unregister_dbf_views();
  3631. return ret;
  3632. }
  3633. /* set a passing level */
  3634. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3635. }
  3636. return 0;
  3637. }
  3638. int qeth_core_load_discipline(struct qeth_card *card,
  3639. enum qeth_discipline_id discipline)
  3640. {
  3641. int rc = 0;
  3642. switch (discipline) {
  3643. case QETH_DISCIPLINE_LAYER3:
  3644. card->discipline.ccwgdriver = try_then_request_module(
  3645. symbol_get(qeth_l3_ccwgroup_driver),
  3646. "qeth_l3");
  3647. break;
  3648. case QETH_DISCIPLINE_LAYER2:
  3649. card->discipline.ccwgdriver = try_then_request_module(
  3650. symbol_get(qeth_l2_ccwgroup_driver),
  3651. "qeth_l2");
  3652. break;
  3653. }
  3654. if (!card->discipline.ccwgdriver) {
  3655. PRINT_ERR("Support for discipline %d not present\n",
  3656. discipline);
  3657. rc = -EINVAL;
  3658. }
  3659. return rc;
  3660. }
  3661. void qeth_core_free_discipline(struct qeth_card *card)
  3662. {
  3663. if (card->options.layer2)
  3664. symbol_put(qeth_l2_ccwgroup_driver);
  3665. else
  3666. symbol_put(qeth_l3_ccwgroup_driver);
  3667. card->discipline.ccwgdriver = NULL;
  3668. }
  3669. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3670. {
  3671. struct qeth_card *card;
  3672. struct device *dev;
  3673. int rc;
  3674. unsigned long flags;
  3675. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3676. dev = &gdev->dev;
  3677. if (!get_device(dev))
  3678. return -ENODEV;
  3679. QETH_DBF_TEXT_(SETUP, 2, "%s", gdev->dev.bus_id);
  3680. card = qeth_alloc_card();
  3681. if (!card) {
  3682. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3683. rc = -ENOMEM;
  3684. goto err_dev;
  3685. }
  3686. card->read.ccwdev = gdev->cdev[0];
  3687. card->write.ccwdev = gdev->cdev[1];
  3688. card->data.ccwdev = gdev->cdev[2];
  3689. dev_set_drvdata(&gdev->dev, card);
  3690. card->gdev = gdev;
  3691. gdev->cdev[0]->handler = qeth_irq;
  3692. gdev->cdev[1]->handler = qeth_irq;
  3693. gdev->cdev[2]->handler = qeth_irq;
  3694. rc = qeth_determine_card_type(card);
  3695. if (rc) {
  3696. PRINT_WARN("%s: not a valid card type\n", __func__);
  3697. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3698. goto err_card;
  3699. }
  3700. rc = qeth_setup_card(card);
  3701. if (rc) {
  3702. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3703. goto err_card;
  3704. }
  3705. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3706. rc = qeth_core_create_osn_attributes(dev);
  3707. if (rc)
  3708. goto err_card;
  3709. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3710. if (rc) {
  3711. qeth_core_remove_osn_attributes(dev);
  3712. goto err_card;
  3713. }
  3714. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3715. if (rc) {
  3716. qeth_core_free_discipline(card);
  3717. qeth_core_remove_osn_attributes(dev);
  3718. goto err_card;
  3719. }
  3720. } else {
  3721. rc = qeth_core_create_device_attributes(dev);
  3722. if (rc)
  3723. goto err_card;
  3724. }
  3725. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3726. list_add_tail(&card->list, &qeth_core_card_list.list);
  3727. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3728. return 0;
  3729. err_card:
  3730. qeth_core_free_card(card);
  3731. err_dev:
  3732. put_device(dev);
  3733. return rc;
  3734. }
  3735. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3736. {
  3737. unsigned long flags;
  3738. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3739. if (card->discipline.ccwgdriver) {
  3740. card->discipline.ccwgdriver->remove(gdev);
  3741. qeth_core_free_discipline(card);
  3742. }
  3743. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3744. qeth_core_remove_osn_attributes(&gdev->dev);
  3745. } else {
  3746. qeth_core_remove_device_attributes(&gdev->dev);
  3747. }
  3748. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3749. list_del(&card->list);
  3750. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3751. qeth_core_free_card(card);
  3752. dev_set_drvdata(&gdev->dev, NULL);
  3753. put_device(&gdev->dev);
  3754. return;
  3755. }
  3756. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3757. {
  3758. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3759. int rc = 0;
  3760. int def_discipline;
  3761. if (!card->discipline.ccwgdriver) {
  3762. if (card->info.type == QETH_CARD_TYPE_IQD)
  3763. def_discipline = QETH_DISCIPLINE_LAYER3;
  3764. else
  3765. def_discipline = QETH_DISCIPLINE_LAYER2;
  3766. rc = qeth_core_load_discipline(card, def_discipline);
  3767. if (rc)
  3768. goto err;
  3769. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3770. if (rc)
  3771. goto err;
  3772. }
  3773. rc = card->discipline.ccwgdriver->set_online(gdev);
  3774. err:
  3775. return rc;
  3776. }
  3777. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3778. {
  3779. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3780. return card->discipline.ccwgdriver->set_offline(gdev);
  3781. }
  3782. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3783. {
  3784. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3785. if (card->discipline.ccwgdriver &&
  3786. card->discipline.ccwgdriver->shutdown)
  3787. card->discipline.ccwgdriver->shutdown(gdev);
  3788. }
  3789. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3790. .owner = THIS_MODULE,
  3791. .name = "qeth",
  3792. .driver_id = 0xD8C5E3C8,
  3793. .probe = qeth_core_probe_device,
  3794. .remove = qeth_core_remove_device,
  3795. .set_online = qeth_core_set_online,
  3796. .set_offline = qeth_core_set_offline,
  3797. .shutdown = qeth_core_shutdown,
  3798. };
  3799. static ssize_t
  3800. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3801. size_t count)
  3802. {
  3803. int err;
  3804. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3805. qeth_core_ccwgroup_driver.driver_id);
  3806. if (err)
  3807. return err;
  3808. else
  3809. return count;
  3810. }
  3811. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3812. static struct {
  3813. const char str[ETH_GSTRING_LEN];
  3814. } qeth_ethtool_stats_keys[] = {
  3815. /* 0 */{"rx skbs"},
  3816. {"rx buffers"},
  3817. {"tx skbs"},
  3818. {"tx buffers"},
  3819. {"tx skbs no packing"},
  3820. {"tx buffers no packing"},
  3821. {"tx skbs packing"},
  3822. {"tx buffers packing"},
  3823. {"tx sg skbs"},
  3824. {"tx sg frags"},
  3825. /* 10 */{"rx sg skbs"},
  3826. {"rx sg frags"},
  3827. {"rx sg page allocs"},
  3828. {"tx large kbytes"},
  3829. {"tx large count"},
  3830. {"tx pk state ch n->p"},
  3831. {"tx pk state ch p->n"},
  3832. {"tx pk watermark low"},
  3833. {"tx pk watermark high"},
  3834. {"queue 0 buffer usage"},
  3835. /* 20 */{"queue 1 buffer usage"},
  3836. {"queue 2 buffer usage"},
  3837. {"queue 3 buffer usage"},
  3838. {"rx handler time"},
  3839. {"rx handler count"},
  3840. {"rx do_QDIO time"},
  3841. {"rx do_QDIO count"},
  3842. {"tx handler time"},
  3843. {"tx handler count"},
  3844. {"tx time"},
  3845. /* 30 */{"tx count"},
  3846. {"tx do_QDIO time"},
  3847. {"tx do_QDIO count"},
  3848. };
  3849. int qeth_core_get_stats_count(struct net_device *dev)
  3850. {
  3851. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3852. }
  3853. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3854. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3855. struct ethtool_stats *stats, u64 *data)
  3856. {
  3857. struct qeth_card *card = netdev_priv(dev);
  3858. data[0] = card->stats.rx_packets -
  3859. card->perf_stats.initial_rx_packets;
  3860. data[1] = card->perf_stats.bufs_rec;
  3861. data[2] = card->stats.tx_packets -
  3862. card->perf_stats.initial_tx_packets;
  3863. data[3] = card->perf_stats.bufs_sent;
  3864. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3865. - card->perf_stats.skbs_sent_pack;
  3866. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3867. data[6] = card->perf_stats.skbs_sent_pack;
  3868. data[7] = card->perf_stats.bufs_sent_pack;
  3869. data[8] = card->perf_stats.sg_skbs_sent;
  3870. data[9] = card->perf_stats.sg_frags_sent;
  3871. data[10] = card->perf_stats.sg_skbs_rx;
  3872. data[11] = card->perf_stats.sg_frags_rx;
  3873. data[12] = card->perf_stats.sg_alloc_page_rx;
  3874. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3875. data[14] = card->perf_stats.large_send_cnt;
  3876. data[15] = card->perf_stats.sc_dp_p;
  3877. data[16] = card->perf_stats.sc_p_dp;
  3878. data[17] = QETH_LOW_WATERMARK_PACK;
  3879. data[18] = QETH_HIGH_WATERMARK_PACK;
  3880. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3881. data[20] = (card->qdio.no_out_queues > 1) ?
  3882. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3883. data[21] = (card->qdio.no_out_queues > 2) ?
  3884. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3885. data[22] = (card->qdio.no_out_queues > 3) ?
  3886. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3887. data[23] = card->perf_stats.inbound_time;
  3888. data[24] = card->perf_stats.inbound_cnt;
  3889. data[25] = card->perf_stats.inbound_do_qdio_time;
  3890. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3891. data[27] = card->perf_stats.outbound_handler_time;
  3892. data[28] = card->perf_stats.outbound_handler_cnt;
  3893. data[29] = card->perf_stats.outbound_time;
  3894. data[30] = card->perf_stats.outbound_cnt;
  3895. data[31] = card->perf_stats.outbound_do_qdio_time;
  3896. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3897. }
  3898. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3899. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3900. {
  3901. switch (stringset) {
  3902. case ETH_SS_STATS:
  3903. memcpy(data, &qeth_ethtool_stats_keys,
  3904. sizeof(qeth_ethtool_stats_keys));
  3905. break;
  3906. default:
  3907. WARN_ON(1);
  3908. break;
  3909. }
  3910. }
  3911. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3912. void qeth_core_get_drvinfo(struct net_device *dev,
  3913. struct ethtool_drvinfo *info)
  3914. {
  3915. struct qeth_card *card = netdev_priv(dev);
  3916. if (card->options.layer2)
  3917. strcpy(info->driver, "qeth_l2");
  3918. else
  3919. strcpy(info->driver, "qeth_l3");
  3920. strcpy(info->version, "1.0");
  3921. strcpy(info->fw_version, card->info.mcl_level);
  3922. sprintf(info->bus_info, "%s/%s/%s",
  3923. CARD_RDEV_ID(card),
  3924. CARD_WDEV_ID(card),
  3925. CARD_DDEV_ID(card));
  3926. }
  3927. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3928. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3929. struct ethtool_cmd *ecmd)
  3930. {
  3931. struct qeth_card *card = netdev_priv(netdev);
  3932. enum qeth_link_types link_type;
  3933. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3934. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3935. else
  3936. link_type = card->info.link_type;
  3937. ecmd->transceiver = XCVR_INTERNAL;
  3938. ecmd->supported = SUPPORTED_Autoneg;
  3939. ecmd->advertising = ADVERTISED_Autoneg;
  3940. ecmd->duplex = DUPLEX_FULL;
  3941. ecmd->autoneg = AUTONEG_ENABLE;
  3942. switch (link_type) {
  3943. case QETH_LINK_TYPE_FAST_ETH:
  3944. case QETH_LINK_TYPE_LANE_ETH100:
  3945. ecmd->supported |= SUPPORTED_10baseT_Half |
  3946. SUPPORTED_10baseT_Full |
  3947. SUPPORTED_100baseT_Half |
  3948. SUPPORTED_100baseT_Full |
  3949. SUPPORTED_TP;
  3950. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3951. ADVERTISED_10baseT_Full |
  3952. ADVERTISED_100baseT_Half |
  3953. ADVERTISED_100baseT_Full |
  3954. ADVERTISED_TP;
  3955. ecmd->speed = SPEED_100;
  3956. ecmd->port = PORT_TP;
  3957. break;
  3958. case QETH_LINK_TYPE_GBIT_ETH:
  3959. case QETH_LINK_TYPE_LANE_ETH1000:
  3960. ecmd->supported |= SUPPORTED_10baseT_Half |
  3961. SUPPORTED_10baseT_Full |
  3962. SUPPORTED_100baseT_Half |
  3963. SUPPORTED_100baseT_Full |
  3964. SUPPORTED_1000baseT_Half |
  3965. SUPPORTED_1000baseT_Full |
  3966. SUPPORTED_FIBRE;
  3967. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3968. ADVERTISED_10baseT_Full |
  3969. ADVERTISED_100baseT_Half |
  3970. ADVERTISED_100baseT_Full |
  3971. ADVERTISED_1000baseT_Half |
  3972. ADVERTISED_1000baseT_Full |
  3973. ADVERTISED_FIBRE;
  3974. ecmd->speed = SPEED_1000;
  3975. ecmd->port = PORT_FIBRE;
  3976. break;
  3977. case QETH_LINK_TYPE_10GBIT_ETH:
  3978. ecmd->supported |= SUPPORTED_10baseT_Half |
  3979. SUPPORTED_10baseT_Full |
  3980. SUPPORTED_100baseT_Half |
  3981. SUPPORTED_100baseT_Full |
  3982. SUPPORTED_1000baseT_Half |
  3983. SUPPORTED_1000baseT_Full |
  3984. SUPPORTED_10000baseT_Full |
  3985. SUPPORTED_FIBRE;
  3986. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3987. ADVERTISED_10baseT_Full |
  3988. ADVERTISED_100baseT_Half |
  3989. ADVERTISED_100baseT_Full |
  3990. ADVERTISED_1000baseT_Half |
  3991. ADVERTISED_1000baseT_Full |
  3992. ADVERTISED_10000baseT_Full |
  3993. ADVERTISED_FIBRE;
  3994. ecmd->speed = SPEED_10000;
  3995. ecmd->port = PORT_FIBRE;
  3996. break;
  3997. default:
  3998. ecmd->supported |= SUPPORTED_10baseT_Half |
  3999. SUPPORTED_10baseT_Full |
  4000. SUPPORTED_TP;
  4001. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4002. ADVERTISED_10baseT_Full |
  4003. ADVERTISED_TP;
  4004. ecmd->speed = SPEED_10;
  4005. ecmd->port = PORT_TP;
  4006. }
  4007. return 0;
  4008. }
  4009. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4010. static int __init qeth_core_init(void)
  4011. {
  4012. int rc;
  4013. PRINT_INFO("loading core functions\n");
  4014. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4015. rwlock_init(&qeth_core_card_list.rwlock);
  4016. rc = qeth_register_dbf_views();
  4017. if (rc)
  4018. goto out_err;
  4019. rc = ccw_driver_register(&qeth_ccw_driver);
  4020. if (rc)
  4021. goto ccw_err;
  4022. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4023. if (rc)
  4024. goto ccwgroup_err;
  4025. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4026. &driver_attr_group);
  4027. if (rc)
  4028. goto driver_err;
  4029. qeth_core_root_dev = s390_root_dev_register("qeth");
  4030. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4031. if (rc)
  4032. goto register_err;
  4033. return 0;
  4034. register_err:
  4035. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4036. &driver_attr_group);
  4037. driver_err:
  4038. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4039. ccwgroup_err:
  4040. ccw_driver_unregister(&qeth_ccw_driver);
  4041. ccw_err:
  4042. qeth_unregister_dbf_views();
  4043. out_err:
  4044. PRINT_ERR("Initialization failed with code %d\n", rc);
  4045. return rc;
  4046. }
  4047. static void __exit qeth_core_exit(void)
  4048. {
  4049. s390_root_dev_unregister(qeth_core_root_dev);
  4050. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4051. &driver_attr_group);
  4052. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4053. ccw_driver_unregister(&qeth_ccw_driver);
  4054. qeth_unregister_dbf_views();
  4055. PRINT_INFO("core functions removed\n");
  4056. }
  4057. module_init(qeth_core_init);
  4058. module_exit(qeth_core_exit);
  4059. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4060. MODULE_DESCRIPTION("qeth core functions");
  4061. MODULE_LICENSE("GPL");