cs4231_lib.c 57 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846
  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
  4. *
  5. * Bugs:
  6. * - sometimes record brokes playback with WSS portion of
  7. * Yamaha OPL3-SA3 chip
  8. * - CS4231 (GUS MAX) - still trouble with occasional noises
  9. * - broken initialization?
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/slab.h>
  32. #include <linux/ioport.h>
  33. #include <sound/core.h>
  34. #include <sound/cs4231.h>
  35. #include <sound/pcm_params.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h>
  38. #include <asm/irq.h>
  39. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  40. MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
  41. MODULE_LICENSE("GPL");
  42. #if 0
  43. #define SNDRV_DEBUG_MCE
  44. #endif
  45. /*
  46. * Some variables
  47. */
  48. static unsigned char freq_bits[14] = {
  49. /* 5510 */ 0x00 | CS4231_XTAL2,
  50. /* 6620 */ 0x0E | CS4231_XTAL2,
  51. /* 8000 */ 0x00 | CS4231_XTAL1,
  52. /* 9600 */ 0x0E | CS4231_XTAL1,
  53. /* 11025 */ 0x02 | CS4231_XTAL2,
  54. /* 16000 */ 0x02 | CS4231_XTAL1,
  55. /* 18900 */ 0x04 | CS4231_XTAL2,
  56. /* 22050 */ 0x06 | CS4231_XTAL2,
  57. /* 27042 */ 0x04 | CS4231_XTAL1,
  58. /* 32000 */ 0x06 | CS4231_XTAL1,
  59. /* 33075 */ 0x0C | CS4231_XTAL2,
  60. /* 37800 */ 0x08 | CS4231_XTAL2,
  61. /* 44100 */ 0x0A | CS4231_XTAL2,
  62. /* 48000 */ 0x0C | CS4231_XTAL1
  63. };
  64. static unsigned int rates[14] = {
  65. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  66. 27042, 32000, 33075, 37800, 44100, 48000
  67. };
  68. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  69. .count = ARRAY_SIZE(rates),
  70. .list = rates,
  71. .mask = 0,
  72. };
  73. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  74. {
  75. return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  76. }
  77. static unsigned char snd_cs4231_original_image[32] =
  78. {
  79. 0x00, /* 00/00 - lic */
  80. 0x00, /* 01/01 - ric */
  81. 0x9f, /* 02/02 - la1ic */
  82. 0x9f, /* 03/03 - ra1ic */
  83. 0x9f, /* 04/04 - la2ic */
  84. 0x9f, /* 05/05 - ra2ic */
  85. 0xbf, /* 06/06 - loc */
  86. 0xbf, /* 07/07 - roc */
  87. 0x20, /* 08/08 - pdfr */
  88. CS4231_AUTOCALIB, /* 09/09 - ic */
  89. 0x00, /* 0a/10 - pc */
  90. 0x00, /* 0b/11 - ti */
  91. CS4231_MODE2, /* 0c/12 - mi */
  92. 0xfc, /* 0d/13 - lbc */
  93. 0x00, /* 0e/14 - pbru */
  94. 0x00, /* 0f/15 - pbrl */
  95. 0x80, /* 10/16 - afei */
  96. 0x01, /* 11/17 - afeii */
  97. 0x9f, /* 12/18 - llic */
  98. 0x9f, /* 13/19 - rlic */
  99. 0x00, /* 14/20 - tlb */
  100. 0x00, /* 15/21 - thb */
  101. 0x00, /* 16/22 - la3mic/reserved */
  102. 0x00, /* 17/23 - ra3mic/reserved */
  103. 0x00, /* 18/24 - afs */
  104. 0x00, /* 19/25 - lamoc/version */
  105. 0xcf, /* 1a/26 - mioc */
  106. 0x00, /* 1b/27 - ramoc/reserved */
  107. 0x20, /* 1c/28 - cdfr */
  108. 0x00, /* 1d/29 - res4 */
  109. 0x00, /* 1e/30 - cbru */
  110. 0x00, /* 1f/31 - cbrl */
  111. };
  112. /*
  113. * Basic I/O functions
  114. */
  115. static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val)
  116. {
  117. outb(val, chip->port + offset);
  118. }
  119. static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset)
  120. {
  121. return inb(chip->port + offset);
  122. }
  123. static void snd_cs4231_wait(struct snd_cs4231 *chip)
  124. {
  125. int timeout;
  126. for (timeout = 250;
  127. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  128. timeout--)
  129. udelay(100);
  130. }
  131. static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  132. unsigned char mask, unsigned char value)
  133. {
  134. unsigned char tmp = (chip->image[reg] & mask) | value;
  135. snd_cs4231_wait(chip);
  136. #ifdef CONFIG_SND_DEBUG
  137. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  138. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  139. #endif
  140. chip->image[reg] = tmp;
  141. if (!chip->calibrate_mute) {
  142. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  143. wmb();
  144. cs4231_outb(chip, CS4231P(REG), tmp);
  145. mb();
  146. }
  147. }
  148. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  149. {
  150. int timeout;
  151. for (timeout = 250;
  152. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  153. timeout--)
  154. udelay(10);
  155. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  156. cs4231_outb(chip, CS4231P(REG), value);
  157. mb();
  158. }
  159. void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  160. {
  161. snd_cs4231_wait(chip);
  162. #ifdef CONFIG_SND_DEBUG
  163. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  164. snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  165. #endif
  166. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  167. cs4231_outb(chip, CS4231P(REG), value);
  168. chip->image[reg] = value;
  169. mb();
  170. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  171. chip->mce_bit | reg, value);
  172. }
  173. unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  174. {
  175. snd_cs4231_wait(chip);
  176. #ifdef CONFIG_SND_DEBUG
  177. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  178. snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
  179. #endif
  180. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  181. mb();
  182. return cs4231_inb(chip, CS4231P(REG));
  183. }
  184. void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val)
  185. {
  186. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  187. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  188. cs4231_outb(chip, CS4231P(REG), val);
  189. chip->eimage[CS4236_REG(reg)] = val;
  190. #if 0
  191. printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
  192. #endif
  193. }
  194. unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg)
  195. {
  196. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  197. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  198. #if 1
  199. return cs4231_inb(chip, CS4231P(REG));
  200. #else
  201. {
  202. unsigned char res;
  203. res = cs4231_inb(chip, CS4231P(REG));
  204. printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
  205. return res;
  206. }
  207. #endif
  208. }
  209. #if 0
  210. static void snd_cs4231_debug(struct snd_cs4231 *chip)
  211. {
  212. printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
  213. printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
  214. printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
  215. printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
  216. printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
  217. printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
  218. printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
  219. printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
  220. printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
  221. printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
  222. printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
  223. printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
  224. printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
  225. printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
  226. printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
  227. printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
  228. printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
  229. printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
  230. printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
  231. printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
  232. printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
  233. printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
  234. printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
  235. printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
  236. printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
  237. printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
  238. printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
  239. printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
  240. printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
  241. printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
  242. printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
  243. printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
  244. printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
  245. printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
  246. }
  247. #endif
  248. /*
  249. * CS4231 detection / MCE routines
  250. */
  251. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  252. {
  253. int timeout;
  254. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  255. for (timeout = 5; timeout > 0; timeout--)
  256. cs4231_inb(chip, CS4231P(REGSEL));
  257. /* end of cleanup sequence */
  258. for (timeout = 250;
  259. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  260. timeout--)
  261. udelay(10);
  262. }
  263. void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  264. {
  265. unsigned long flags;
  266. int timeout;
  267. snd_cs4231_wait(chip);
  268. #ifdef CONFIG_SND_DEBUG
  269. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  270. snd_printk("mce_up - auto calibration time out (0)\n");
  271. #endif
  272. spin_lock_irqsave(&chip->reg_lock, flags);
  273. chip->mce_bit |= CS4231_MCE;
  274. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  275. if (timeout == 0x80)
  276. snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  277. if (!(timeout & CS4231_MCE))
  278. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  279. spin_unlock_irqrestore(&chip->reg_lock, flags);
  280. }
  281. void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  282. {
  283. unsigned long flags;
  284. int timeout;
  285. snd_cs4231_busy_wait(chip);
  286. #ifdef CONFIG_SND_DEBUG
  287. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  288. snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
  289. #endif
  290. spin_lock_irqsave(&chip->reg_lock, flags);
  291. chip->mce_bit &= ~CS4231_MCE;
  292. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  293. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  294. spin_unlock_irqrestore(&chip->reg_lock, flags);
  295. if (timeout == 0x80)
  296. snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  297. if ((timeout & CS4231_MCE) == 0 ||
  298. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  299. return;
  300. }
  301. snd_cs4231_busy_wait(chip);
  302. /*
  303. * Wait for (possible -- during init auto-calibration may not be set)
  304. * calibration process to start. Needs upto 5 sample periods on AD1848
  305. * which at the slowest possible rate of 5.5125 kHz means 907 us.
  306. */
  307. msleep(1);
  308. snd_printdd("(1) jiffies = %lu\n", jiffies);
  309. /* check condition up to 250 ms */
  310. timeout = msecs_to_jiffies(250);
  311. while (snd_cs4231_in(chip, CS4231_TEST_INIT) &
  312. CS4231_CALIB_IN_PROGRESS) {
  313. if (timeout <= 0) {
  314. snd_printk(KERN_ERR "mce_down - "
  315. "auto calibration time out (2)\n");
  316. return;
  317. }
  318. timeout = schedule_timeout(timeout);
  319. }
  320. snd_printdd("(2) jiffies = %lu\n", jiffies);
  321. /* check condition up to 100 ms */
  322. timeout = msecs_to_jiffies(100);
  323. while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  324. if (timeout <= 0) {
  325. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  326. return;
  327. }
  328. timeout = schedule_timeout(timeout);
  329. }
  330. snd_printdd("(3) jiffies = %lu\n", jiffies);
  331. snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
  332. }
  333. static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
  334. {
  335. switch (format & 0xe0) {
  336. case CS4231_LINEAR_16:
  337. case CS4231_LINEAR_16_BIG:
  338. size >>= 1;
  339. break;
  340. case CS4231_ADPCM_16:
  341. return size >> 2;
  342. }
  343. if (format & CS4231_STEREO)
  344. size >>= 1;
  345. return size;
  346. }
  347. static int snd_cs4231_trigger(struct snd_pcm_substream *substream,
  348. int cmd)
  349. {
  350. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  351. int result = 0;
  352. unsigned int what;
  353. struct snd_pcm_substream *s;
  354. int do_start;
  355. #if 0
  356. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
  357. #endif
  358. switch (cmd) {
  359. case SNDRV_PCM_TRIGGER_START:
  360. case SNDRV_PCM_TRIGGER_RESUME:
  361. do_start = 1; break;
  362. case SNDRV_PCM_TRIGGER_STOP:
  363. case SNDRV_PCM_TRIGGER_SUSPEND:
  364. do_start = 0; break;
  365. default:
  366. return -EINVAL;
  367. }
  368. what = 0;
  369. snd_pcm_group_for_each_entry(s, substream) {
  370. if (s == chip->playback_substream) {
  371. what |= CS4231_PLAYBACK_ENABLE;
  372. snd_pcm_trigger_done(s, substream);
  373. } else if (s == chip->capture_substream) {
  374. what |= CS4231_RECORD_ENABLE;
  375. snd_pcm_trigger_done(s, substream);
  376. }
  377. }
  378. spin_lock(&chip->reg_lock);
  379. if (do_start) {
  380. chip->image[CS4231_IFACE_CTRL] |= what;
  381. if (chip->trigger)
  382. chip->trigger(chip, what, 1);
  383. } else {
  384. chip->image[CS4231_IFACE_CTRL] &= ~what;
  385. if (chip->trigger)
  386. chip->trigger(chip, what, 0);
  387. }
  388. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  389. spin_unlock(&chip->reg_lock);
  390. #if 0
  391. snd_cs4231_debug(chip);
  392. #endif
  393. return result;
  394. }
  395. /*
  396. * CODEC I/O
  397. */
  398. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  399. {
  400. int i;
  401. for (i = 0; i < ARRAY_SIZE(rates); i++)
  402. if (rate == rates[i])
  403. return freq_bits[i];
  404. // snd_BUG();
  405. return freq_bits[ARRAY_SIZE(rates) - 1];
  406. }
  407. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip,
  408. int format,
  409. int channels)
  410. {
  411. unsigned char rformat;
  412. rformat = CS4231_LINEAR_8;
  413. switch (format) {
  414. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  415. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  416. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  417. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  418. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  419. }
  420. if (channels > 1)
  421. rformat |= CS4231_STEREO;
  422. #if 0
  423. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  424. #endif
  425. return rformat;
  426. }
  427. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  428. {
  429. unsigned long flags;
  430. mute = mute ? 1 : 0;
  431. spin_lock_irqsave(&chip->reg_lock, flags);
  432. if (chip->calibrate_mute == mute) {
  433. spin_unlock_irqrestore(&chip->reg_lock, flags);
  434. return;
  435. }
  436. if (!mute) {
  437. snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
  438. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
  439. snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
  440. }
  441. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  442. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  443. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  444. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  445. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  446. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  447. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  448. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  449. snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  450. if (chip->hardware == CS4231_HW_INTERWAVE) {
  451. snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
  452. snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
  453. snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
  454. snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
  455. }
  456. chip->calibrate_mute = mute;
  457. spin_unlock_irqrestore(&chip->reg_lock, flags);
  458. }
  459. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  460. struct snd_pcm_hw_params *params,
  461. unsigned char pdfr)
  462. {
  463. unsigned long flags;
  464. int full_calib = 1;
  465. mutex_lock(&chip->mce_mutex);
  466. snd_cs4231_calibrate_mute(chip, 1);
  467. if (chip->hardware == CS4231_HW_CS4231A ||
  468. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  469. spin_lock_irqsave(&chip->reg_lock, flags);
  470. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
  471. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
  472. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  473. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
  474. udelay(100); /* Fixes audible clicks at least on GUS MAX */
  475. full_calib = 0;
  476. }
  477. spin_unlock_irqrestore(&chip->reg_lock, flags);
  478. }
  479. if (full_calib) {
  480. snd_cs4231_mce_up(chip);
  481. spin_lock_irqsave(&chip->reg_lock, flags);
  482. if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
  483. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  484. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  485. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  486. pdfr);
  487. } else {
  488. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  489. }
  490. spin_unlock_irqrestore(&chip->reg_lock, flags);
  491. if (chip->hardware == CS4231_HW_OPL3SA2)
  492. udelay(100); /* this seems to help */
  493. snd_cs4231_mce_down(chip);
  494. }
  495. snd_cs4231_calibrate_mute(chip, 0);
  496. mutex_unlock(&chip->mce_mutex);
  497. }
  498. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  499. struct snd_pcm_hw_params *params,
  500. unsigned char cdfr)
  501. {
  502. unsigned long flags;
  503. int full_calib = 1;
  504. mutex_lock(&chip->mce_mutex);
  505. snd_cs4231_calibrate_mute(chip, 1);
  506. if (chip->hardware == CS4231_HW_CS4231A ||
  507. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  508. spin_lock_irqsave(&chip->reg_lock, flags);
  509. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
  510. (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  511. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
  512. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
  513. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
  514. full_calib = 0;
  515. }
  516. spin_unlock_irqrestore(&chip->reg_lock, flags);
  517. }
  518. if (full_calib) {
  519. snd_cs4231_mce_up(chip);
  520. spin_lock_irqsave(&chip->reg_lock, flags);
  521. if (chip->hardware != CS4231_HW_INTERWAVE) {
  522. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  523. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  524. ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  525. (cdfr & 0x0f));
  526. spin_unlock_irqrestore(&chip->reg_lock, flags);
  527. snd_cs4231_mce_down(chip);
  528. snd_cs4231_mce_up(chip);
  529. spin_lock_irqsave(&chip->reg_lock, flags);
  530. }
  531. }
  532. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  533. spin_unlock_irqrestore(&chip->reg_lock, flags);
  534. snd_cs4231_mce_down(chip);
  535. }
  536. snd_cs4231_calibrate_mute(chip, 0);
  537. mutex_unlock(&chip->mce_mutex);
  538. }
  539. /*
  540. * Timer interface
  541. */
  542. static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer)
  543. {
  544. struct snd_cs4231 *chip = snd_timer_chip(timer);
  545. if (chip->hardware & CS4231_HW_CS4236B_MASK)
  546. return 14467;
  547. else
  548. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  549. }
  550. static int snd_cs4231_timer_start(struct snd_timer * timer)
  551. {
  552. unsigned long flags;
  553. unsigned int ticks;
  554. struct snd_cs4231 *chip = snd_timer_chip(timer);
  555. spin_lock_irqsave(&chip->reg_lock, flags);
  556. ticks = timer->sticks;
  557. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  558. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  559. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  560. snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
  561. snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
  562. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  563. }
  564. spin_unlock_irqrestore(&chip->reg_lock, flags);
  565. return 0;
  566. }
  567. static int snd_cs4231_timer_stop(struct snd_timer * timer)
  568. {
  569. unsigned long flags;
  570. struct snd_cs4231 *chip = snd_timer_chip(timer);
  571. spin_lock_irqsave(&chip->reg_lock, flags);
  572. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  573. spin_unlock_irqrestore(&chip->reg_lock, flags);
  574. return 0;
  575. }
  576. static void snd_cs4231_init(struct snd_cs4231 *chip)
  577. {
  578. unsigned long flags;
  579. snd_cs4231_mce_down(chip);
  580. #ifdef SNDRV_DEBUG_MCE
  581. snd_printk("init: (1)\n");
  582. #endif
  583. snd_cs4231_mce_up(chip);
  584. spin_lock_irqsave(&chip->reg_lock, flags);
  585. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  586. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  587. CS4231_CALIB_MODE);
  588. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  589. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  590. spin_unlock_irqrestore(&chip->reg_lock, flags);
  591. snd_cs4231_mce_down(chip);
  592. #ifdef SNDRV_DEBUG_MCE
  593. snd_printk("init: (2)\n");
  594. #endif
  595. snd_cs4231_mce_up(chip);
  596. spin_lock_irqsave(&chip->reg_lock, flags);
  597. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  598. spin_unlock_irqrestore(&chip->reg_lock, flags);
  599. snd_cs4231_mce_down(chip);
  600. #ifdef SNDRV_DEBUG_MCE
  601. snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  602. #endif
  603. spin_lock_irqsave(&chip->reg_lock, flags);
  604. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  605. spin_unlock_irqrestore(&chip->reg_lock, flags);
  606. snd_cs4231_mce_up(chip);
  607. spin_lock_irqsave(&chip->reg_lock, flags);
  608. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  609. spin_unlock_irqrestore(&chip->reg_lock, flags);
  610. snd_cs4231_mce_down(chip);
  611. #ifdef SNDRV_DEBUG_MCE
  612. snd_printk("init: (4)\n");
  613. #endif
  614. snd_cs4231_mce_up(chip);
  615. spin_lock_irqsave(&chip->reg_lock, flags);
  616. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  617. spin_unlock_irqrestore(&chip->reg_lock, flags);
  618. snd_cs4231_mce_down(chip);
  619. #ifdef SNDRV_DEBUG_MCE
  620. snd_printk("init: (5)\n");
  621. #endif
  622. }
  623. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  624. {
  625. unsigned long flags;
  626. mutex_lock(&chip->open_mutex);
  627. if ((chip->mode & mode) ||
  628. ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
  629. mutex_unlock(&chip->open_mutex);
  630. return -EAGAIN;
  631. }
  632. if (chip->mode & CS4231_MODE_OPEN) {
  633. chip->mode |= mode;
  634. mutex_unlock(&chip->open_mutex);
  635. return 0;
  636. }
  637. /* ok. now enable and ack CODEC IRQ */
  638. spin_lock_irqsave(&chip->reg_lock, flags);
  639. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  640. CS4231_RECORD_IRQ |
  641. CS4231_TIMER_IRQ);
  642. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  643. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  644. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  645. chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
  646. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  647. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  648. CS4231_RECORD_IRQ |
  649. CS4231_TIMER_IRQ);
  650. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  651. spin_unlock_irqrestore(&chip->reg_lock, flags);
  652. chip->mode = mode;
  653. mutex_unlock(&chip->open_mutex);
  654. return 0;
  655. }
  656. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  657. {
  658. unsigned long flags;
  659. mutex_lock(&chip->open_mutex);
  660. chip->mode &= ~mode;
  661. if (chip->mode & CS4231_MODE_OPEN) {
  662. mutex_unlock(&chip->open_mutex);
  663. return;
  664. }
  665. snd_cs4231_calibrate_mute(chip, 1);
  666. /* disable IRQ */
  667. spin_lock_irqsave(&chip->reg_lock, flags);
  668. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  669. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  670. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  671. chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
  672. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  673. /* now disable record & playback */
  674. if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  675. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  676. spin_unlock_irqrestore(&chip->reg_lock, flags);
  677. snd_cs4231_mce_up(chip);
  678. spin_lock_irqsave(&chip->reg_lock, flags);
  679. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  680. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  681. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  682. spin_unlock_irqrestore(&chip->reg_lock, flags);
  683. snd_cs4231_mce_down(chip);
  684. spin_lock_irqsave(&chip->reg_lock, flags);
  685. }
  686. /* clear IRQ again */
  687. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  688. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  689. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  690. spin_unlock_irqrestore(&chip->reg_lock, flags);
  691. snd_cs4231_calibrate_mute(chip, 0);
  692. chip->mode = 0;
  693. mutex_unlock(&chip->open_mutex);
  694. }
  695. /*
  696. * timer open/close
  697. */
  698. static int snd_cs4231_timer_open(struct snd_timer * timer)
  699. {
  700. struct snd_cs4231 *chip = snd_timer_chip(timer);
  701. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  702. return 0;
  703. }
  704. static int snd_cs4231_timer_close(struct snd_timer * timer)
  705. {
  706. struct snd_cs4231 *chip = snd_timer_chip(timer);
  707. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  708. return 0;
  709. }
  710. static struct snd_timer_hardware snd_cs4231_timer_table =
  711. {
  712. .flags = SNDRV_TIMER_HW_AUTO,
  713. .resolution = 9945,
  714. .ticks = 65535,
  715. .open = snd_cs4231_timer_open,
  716. .close = snd_cs4231_timer_close,
  717. .c_resolution = snd_cs4231_timer_resolution,
  718. .start = snd_cs4231_timer_start,
  719. .stop = snd_cs4231_timer_stop,
  720. };
  721. /*
  722. * ok.. exported functions..
  723. */
  724. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  725. struct snd_pcm_hw_params *hw_params)
  726. {
  727. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  728. unsigned char new_pdfr;
  729. int err;
  730. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  731. return err;
  732. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  733. snd_cs4231_get_rate(params_rate(hw_params));
  734. chip->set_playback_format(chip, hw_params, new_pdfr);
  735. return 0;
  736. }
  737. static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
  738. {
  739. return snd_pcm_lib_free_pages(substream);
  740. }
  741. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  742. {
  743. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  744. struct snd_pcm_runtime *runtime = substream->runtime;
  745. unsigned long flags;
  746. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  747. unsigned int count = snd_pcm_lib_period_bytes(substream);
  748. spin_lock_irqsave(&chip->reg_lock, flags);
  749. chip->p_dma_size = size;
  750. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
  751. snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  752. count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
  753. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  754. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  755. spin_unlock_irqrestore(&chip->reg_lock, flags);
  756. #if 0
  757. snd_cs4231_debug(chip);
  758. #endif
  759. return 0;
  760. }
  761. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  762. struct snd_pcm_hw_params *hw_params)
  763. {
  764. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  765. unsigned char new_cdfr;
  766. int err;
  767. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  768. return err;
  769. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  770. snd_cs4231_get_rate(params_rate(hw_params));
  771. chip->set_capture_format(chip, hw_params, new_cdfr);
  772. return 0;
  773. }
  774. static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
  775. {
  776. return snd_pcm_lib_free_pages(substream);
  777. }
  778. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  779. {
  780. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  781. struct snd_pcm_runtime *runtime = substream->runtime;
  782. unsigned long flags;
  783. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  784. unsigned int count = snd_pcm_lib_period_bytes(substream);
  785. spin_lock_irqsave(&chip->reg_lock, flags);
  786. chip->c_dma_size = size;
  787. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  788. snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  789. count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
  790. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  791. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  792. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  793. } else {
  794. snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
  795. snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
  796. }
  797. spin_unlock_irqrestore(&chip->reg_lock, flags);
  798. return 0;
  799. }
  800. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  801. {
  802. unsigned long flags;
  803. unsigned char res;
  804. spin_lock_irqsave(&chip->reg_lock, flags);
  805. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  806. spin_unlock_irqrestore(&chip->reg_lock, flags);
  807. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  808. chip->capture_substream->runtime->overrange++;
  809. }
  810. irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id)
  811. {
  812. struct snd_cs4231 *chip = dev_id;
  813. unsigned char status;
  814. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  815. if (status & CS4231_TIMER_IRQ) {
  816. if (chip->timer)
  817. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  818. }
  819. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  820. if (status & CS4231_PLAYBACK_IRQ) {
  821. if (chip->mode & CS4231_MODE_PLAY) {
  822. if (chip->playback_substream)
  823. snd_pcm_period_elapsed(chip->playback_substream);
  824. }
  825. if (chip->mode & CS4231_MODE_RECORD) {
  826. if (chip->capture_substream) {
  827. snd_cs4231_overrange(chip);
  828. snd_pcm_period_elapsed(chip->capture_substream);
  829. }
  830. }
  831. }
  832. } else {
  833. if (status & CS4231_PLAYBACK_IRQ) {
  834. if (chip->playback_substream)
  835. snd_pcm_period_elapsed(chip->playback_substream);
  836. }
  837. if (status & CS4231_RECORD_IRQ) {
  838. if (chip->capture_substream) {
  839. snd_cs4231_overrange(chip);
  840. snd_pcm_period_elapsed(chip->capture_substream);
  841. }
  842. }
  843. }
  844. spin_lock(&chip->reg_lock);
  845. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  846. spin_unlock(&chip->reg_lock);
  847. return IRQ_HANDLED;
  848. }
  849. static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
  850. {
  851. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  852. size_t ptr;
  853. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  854. return 0;
  855. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  856. return bytes_to_frames(substream->runtime, ptr);
  857. }
  858. static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
  859. {
  860. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  861. size_t ptr;
  862. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  863. return 0;
  864. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  865. return bytes_to_frames(substream->runtime, ptr);
  866. }
  867. /*
  868. */
  869. static int snd_cs4231_probe(struct snd_cs4231 *chip)
  870. {
  871. unsigned long flags;
  872. int i, id, rev;
  873. unsigned char *ptr;
  874. unsigned int hw;
  875. #if 0
  876. snd_cs4231_debug(chip);
  877. #endif
  878. id = 0;
  879. for (i = 0; i < 50; i++) {
  880. mb();
  881. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  882. udelay(2000);
  883. else {
  884. spin_lock_irqsave(&chip->reg_lock, flags);
  885. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  886. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  887. spin_unlock_irqrestore(&chip->reg_lock, flags);
  888. if (id == 0x0a)
  889. break; /* this is valid value */
  890. }
  891. }
  892. snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
  893. if (id != 0x0a)
  894. return -ENODEV; /* no valid device found */
  895. if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  896. rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
  897. snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
  898. if (rev == 0x80) {
  899. unsigned char tmp = snd_cs4231_in(chip, 23);
  900. snd_cs4231_out(chip, 23, ~tmp);
  901. if (snd_cs4231_in(chip, 23) != tmp)
  902. chip->hardware = CS4231_HW_AD1845;
  903. else
  904. chip->hardware = CS4231_HW_CS4231;
  905. } else if (rev == 0xa0) {
  906. chip->hardware = CS4231_HW_CS4231A;
  907. } else if (rev == 0xa2) {
  908. chip->hardware = CS4231_HW_CS4232;
  909. } else if (rev == 0xb2) {
  910. chip->hardware = CS4231_HW_CS4232A;
  911. } else if (rev == 0x83) {
  912. chip->hardware = CS4231_HW_CS4236;
  913. } else if (rev == 0x03) {
  914. chip->hardware = CS4231_HW_CS4236B;
  915. } else {
  916. snd_printk("unknown CS chip with version 0x%x\n", rev);
  917. return -ENODEV; /* unknown CS4231 chip? */
  918. }
  919. }
  920. spin_lock_irqsave(&chip->reg_lock, flags);
  921. cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
  922. cs4231_outb(chip, CS4231P(STATUS), 0);
  923. mb();
  924. spin_unlock_irqrestore(&chip->reg_lock, flags);
  925. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  926. switch (chip->hardware) {
  927. case CS4231_HW_INTERWAVE:
  928. chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
  929. break;
  930. case CS4231_HW_CS4235:
  931. case CS4231_HW_CS4236B:
  932. case CS4231_HW_CS4237B:
  933. case CS4231_HW_CS4238B:
  934. case CS4231_HW_CS4239:
  935. if (hw == CS4231_HW_DETECT3)
  936. chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
  937. else
  938. chip->hardware = CS4231_HW_CS4236;
  939. break;
  940. }
  941. chip->image[CS4231_IFACE_CTRL] =
  942. (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
  943. (chip->single_dma ? CS4231_SINGLE_DMA : 0);
  944. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  945. chip->image[CS4231_ALT_FEATURE_2] = chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
  946. ptr = (unsigned char *) &chip->image;
  947. snd_cs4231_mce_down(chip);
  948. spin_lock_irqsave(&chip->reg_lock, flags);
  949. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  950. snd_cs4231_out(chip, i, *ptr++);
  951. spin_unlock_irqrestore(&chip->reg_lock, flags);
  952. snd_cs4231_mce_up(chip);
  953. snd_cs4231_mce_down(chip);
  954. mdelay(2);
  955. /* ok.. try check hardware version for CS4236+ chips */
  956. if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  957. if (chip->hardware == CS4231_HW_CS4236B) {
  958. rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
  959. snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
  960. id = snd_cs4236_ext_in(chip, CS4236_VERSION);
  961. snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
  962. snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
  963. if ((id & 0x1f) == 0x1d) { /* CS4235 */
  964. chip->hardware = CS4231_HW_CS4235;
  965. switch (id >> 5) {
  966. case 4:
  967. case 5:
  968. case 6:
  969. break;
  970. default:
  971. snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
  972. }
  973. } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
  974. switch (id >> 5) {
  975. case 4:
  976. case 5:
  977. case 6:
  978. case 7:
  979. chip->hardware = CS4231_HW_CS4236B;
  980. break;
  981. default:
  982. snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
  983. }
  984. } else if ((id & 0x1f) == 0x08) { /* CS4237B */
  985. chip->hardware = CS4231_HW_CS4237B;
  986. switch (id >> 5) {
  987. case 4:
  988. case 5:
  989. case 6:
  990. case 7:
  991. break;
  992. default:
  993. snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
  994. }
  995. } else if ((id & 0x1f) == 0x09) { /* CS4238B */
  996. chip->hardware = CS4231_HW_CS4238B;
  997. switch (id >> 5) {
  998. case 5:
  999. case 6:
  1000. case 7:
  1001. break;
  1002. default:
  1003. snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
  1004. }
  1005. } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
  1006. chip->hardware = CS4231_HW_CS4239;
  1007. switch (id >> 5) {
  1008. case 4:
  1009. case 5:
  1010. case 6:
  1011. break;
  1012. default:
  1013. snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
  1014. }
  1015. } else {
  1016. snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
  1017. }
  1018. }
  1019. }
  1020. return 0; /* all things are ok.. */
  1021. }
  1022. /*
  1023. */
  1024. static struct snd_pcm_hardware snd_cs4231_playback =
  1025. {
  1026. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1027. SNDRV_PCM_INFO_MMAP_VALID |
  1028. SNDRV_PCM_INFO_RESUME |
  1029. SNDRV_PCM_INFO_SYNC_START),
  1030. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1031. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1032. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1033. .rate_min = 5510,
  1034. .rate_max = 48000,
  1035. .channels_min = 1,
  1036. .channels_max = 2,
  1037. .buffer_bytes_max = (128*1024),
  1038. .period_bytes_min = 64,
  1039. .period_bytes_max = (128*1024),
  1040. .periods_min = 1,
  1041. .periods_max = 1024,
  1042. .fifo_size = 0,
  1043. };
  1044. static struct snd_pcm_hardware snd_cs4231_capture =
  1045. {
  1046. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1047. SNDRV_PCM_INFO_MMAP_VALID |
  1048. SNDRV_PCM_INFO_RESUME |
  1049. SNDRV_PCM_INFO_SYNC_START),
  1050. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1051. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1052. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1053. .rate_min = 5510,
  1054. .rate_max = 48000,
  1055. .channels_min = 1,
  1056. .channels_max = 2,
  1057. .buffer_bytes_max = (128*1024),
  1058. .period_bytes_min = 64,
  1059. .period_bytes_max = (128*1024),
  1060. .periods_min = 1,
  1061. .periods_max = 1024,
  1062. .fifo_size = 0,
  1063. };
  1064. /*
  1065. */
  1066. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  1067. {
  1068. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1069. struct snd_pcm_runtime *runtime = substream->runtime;
  1070. int err;
  1071. runtime->hw = snd_cs4231_playback;
  1072. /* hardware bug in InterWave chipset */
  1073. if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
  1074. runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
  1075. /* hardware limitation of cheap chips */
  1076. if (chip->hardware == CS4231_HW_CS4235 ||
  1077. chip->hardware == CS4231_HW_CS4239)
  1078. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1079. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  1080. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  1081. if (chip->claim_dma) {
  1082. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
  1083. return err;
  1084. }
  1085. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1086. if (chip->release_dma)
  1087. chip->release_dma(chip, chip->dma_private_data, chip->dma1);
  1088. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1089. return err;
  1090. }
  1091. chip->playback_substream = substream;
  1092. snd_pcm_set_sync(substream);
  1093. chip->rate_constraint(runtime);
  1094. return 0;
  1095. }
  1096. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  1097. {
  1098. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1099. struct snd_pcm_runtime *runtime = substream->runtime;
  1100. int err;
  1101. runtime->hw = snd_cs4231_capture;
  1102. /* hardware limitation of cheap chips */
  1103. if (chip->hardware == CS4231_HW_CS4235 ||
  1104. chip->hardware == CS4231_HW_CS4239)
  1105. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1106. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  1107. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  1108. if (chip->claim_dma) {
  1109. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
  1110. return err;
  1111. }
  1112. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1113. if (chip->release_dma)
  1114. chip->release_dma(chip, chip->dma_private_data, chip->dma2);
  1115. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1116. return err;
  1117. }
  1118. chip->capture_substream = substream;
  1119. snd_pcm_set_sync(substream);
  1120. chip->rate_constraint(runtime);
  1121. return 0;
  1122. }
  1123. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1124. {
  1125. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1126. chip->playback_substream = NULL;
  1127. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1128. return 0;
  1129. }
  1130. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1131. {
  1132. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1133. chip->capture_substream = NULL;
  1134. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1135. return 0;
  1136. }
  1137. #ifdef CONFIG_PM
  1138. /* lowlevel suspend callback for CS4231 */
  1139. static void snd_cs4231_suspend(struct snd_cs4231 *chip)
  1140. {
  1141. int reg;
  1142. unsigned long flags;
  1143. snd_pcm_suspend_all(chip->pcm);
  1144. spin_lock_irqsave(&chip->reg_lock, flags);
  1145. for (reg = 0; reg < 32; reg++)
  1146. chip->image[reg] = snd_cs4231_in(chip, reg);
  1147. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1148. }
  1149. /* lowlevel resume callback for CS4231 */
  1150. static void snd_cs4231_resume(struct snd_cs4231 *chip)
  1151. {
  1152. int reg;
  1153. unsigned long flags;
  1154. /* int timeout; */
  1155. snd_cs4231_mce_up(chip);
  1156. spin_lock_irqsave(&chip->reg_lock, flags);
  1157. for (reg = 0; reg < 32; reg++) {
  1158. switch (reg) {
  1159. case CS4231_VERSION:
  1160. break;
  1161. default:
  1162. snd_cs4231_out(chip, reg, chip->image[reg]);
  1163. break;
  1164. }
  1165. }
  1166. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1167. #if 1
  1168. snd_cs4231_mce_down(chip);
  1169. #else
  1170. /* The following is a workaround to avoid freeze after resume on TP600E.
  1171. This is the first half of copy of snd_cs4231_mce_down(), but doesn't
  1172. include rescheduling. -- iwai
  1173. */
  1174. snd_cs4231_busy_wait(chip);
  1175. spin_lock_irqsave(&chip->reg_lock, flags);
  1176. chip->mce_bit &= ~CS4231_MCE;
  1177. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  1178. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  1179. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1180. if (timeout == 0x80)
  1181. snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  1182. if ((timeout & CS4231_MCE) == 0 ||
  1183. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  1184. return;
  1185. }
  1186. snd_cs4231_busy_wait(chip);
  1187. #endif
  1188. }
  1189. #endif /* CONFIG_PM */
  1190. static int snd_cs4231_free(struct snd_cs4231 *chip)
  1191. {
  1192. release_and_free_resource(chip->res_port);
  1193. release_and_free_resource(chip->res_cport);
  1194. if (chip->irq >= 0) {
  1195. disable_irq(chip->irq);
  1196. if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
  1197. free_irq(chip->irq, (void *) chip);
  1198. }
  1199. if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
  1200. snd_dma_disable(chip->dma1);
  1201. free_dma(chip->dma1);
  1202. }
  1203. if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
  1204. snd_dma_disable(chip->dma2);
  1205. free_dma(chip->dma2);
  1206. }
  1207. if (chip->timer)
  1208. snd_device_free(chip->card, chip->timer);
  1209. kfree(chip);
  1210. return 0;
  1211. }
  1212. static int snd_cs4231_dev_free(struct snd_device *device)
  1213. {
  1214. struct snd_cs4231 *chip = device->device_data;
  1215. return snd_cs4231_free(chip);
  1216. }
  1217. const char *snd_cs4231_chip_id(struct snd_cs4231 *chip)
  1218. {
  1219. switch (chip->hardware) {
  1220. case CS4231_HW_CS4231: return "CS4231";
  1221. case CS4231_HW_CS4231A: return "CS4231A";
  1222. case CS4231_HW_CS4232: return "CS4232";
  1223. case CS4231_HW_CS4232A: return "CS4232A";
  1224. case CS4231_HW_CS4235: return "CS4235";
  1225. case CS4231_HW_CS4236: return "CS4236";
  1226. case CS4231_HW_CS4236B: return "CS4236B";
  1227. case CS4231_HW_CS4237B: return "CS4237B";
  1228. case CS4231_HW_CS4238B: return "CS4238B";
  1229. case CS4231_HW_CS4239: return "CS4239";
  1230. case CS4231_HW_INTERWAVE: return "AMD InterWave";
  1231. case CS4231_HW_OPL3SA2: return chip->card->shortname;
  1232. case CS4231_HW_AD1845: return "AD1845";
  1233. default: return "???";
  1234. }
  1235. }
  1236. static int snd_cs4231_new(struct snd_card *card,
  1237. unsigned short hardware,
  1238. unsigned short hwshare,
  1239. struct snd_cs4231 ** rchip)
  1240. {
  1241. struct snd_cs4231 *chip;
  1242. *rchip = NULL;
  1243. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1244. if (chip == NULL)
  1245. return -ENOMEM;
  1246. chip->hardware = hardware;
  1247. chip->hwshare = hwshare;
  1248. spin_lock_init(&chip->reg_lock);
  1249. mutex_init(&chip->mce_mutex);
  1250. mutex_init(&chip->open_mutex);
  1251. chip->card = card;
  1252. chip->rate_constraint = snd_cs4231_xrate;
  1253. chip->set_playback_format = snd_cs4231_playback_format;
  1254. chip->set_capture_format = snd_cs4231_capture_format;
  1255. memcpy(&chip->image, &snd_cs4231_original_image, sizeof(snd_cs4231_original_image));
  1256. *rchip = chip;
  1257. return 0;
  1258. }
  1259. int snd_cs4231_create(struct snd_card *card,
  1260. unsigned long port,
  1261. unsigned long cport,
  1262. int irq, int dma1, int dma2,
  1263. unsigned short hardware,
  1264. unsigned short hwshare,
  1265. struct snd_cs4231 ** rchip)
  1266. {
  1267. static struct snd_device_ops ops = {
  1268. .dev_free = snd_cs4231_dev_free,
  1269. };
  1270. struct snd_cs4231 *chip;
  1271. int err;
  1272. err = snd_cs4231_new(card, hardware, hwshare, &chip);
  1273. if (err < 0)
  1274. return err;
  1275. chip->irq = -1;
  1276. chip->dma1 = -1;
  1277. chip->dma2 = -1;
  1278. if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
  1279. snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
  1280. snd_cs4231_free(chip);
  1281. return -EBUSY;
  1282. }
  1283. chip->port = port;
  1284. if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
  1285. snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
  1286. snd_cs4231_free(chip);
  1287. return -ENODEV;
  1288. }
  1289. chip->cport = cport;
  1290. if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) {
  1291. snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
  1292. snd_cs4231_free(chip);
  1293. return -EBUSY;
  1294. }
  1295. chip->irq = irq;
  1296. if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
  1297. snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
  1298. snd_cs4231_free(chip);
  1299. return -EBUSY;
  1300. }
  1301. chip->dma1 = dma1;
  1302. if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
  1303. snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
  1304. snd_cs4231_free(chip);
  1305. return -EBUSY;
  1306. }
  1307. if (dma1 == dma2 || dma2 < 0) {
  1308. chip->single_dma = 1;
  1309. chip->dma2 = chip->dma1;
  1310. } else
  1311. chip->dma2 = dma2;
  1312. /* global setup */
  1313. if (snd_cs4231_probe(chip) < 0) {
  1314. snd_cs4231_free(chip);
  1315. return -ENODEV;
  1316. }
  1317. snd_cs4231_init(chip);
  1318. #if 0
  1319. if (chip->hardware & CS4231_HW_CS4232_MASK) {
  1320. if (chip->res_cport == NULL)
  1321. snd_printk("CS4232 control port features are not accessible\n");
  1322. }
  1323. #endif
  1324. /* Register device */
  1325. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1326. snd_cs4231_free(chip);
  1327. return err;
  1328. }
  1329. #ifdef CONFIG_PM
  1330. /* Power Management */
  1331. chip->suspend = snd_cs4231_suspend;
  1332. chip->resume = snd_cs4231_resume;
  1333. #endif
  1334. *rchip = chip;
  1335. return 0;
  1336. }
  1337. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1338. .open = snd_cs4231_playback_open,
  1339. .close = snd_cs4231_playback_close,
  1340. .ioctl = snd_pcm_lib_ioctl,
  1341. .hw_params = snd_cs4231_playback_hw_params,
  1342. .hw_free = snd_cs4231_playback_hw_free,
  1343. .prepare = snd_cs4231_playback_prepare,
  1344. .trigger = snd_cs4231_trigger,
  1345. .pointer = snd_cs4231_playback_pointer,
  1346. };
  1347. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1348. .open = snd_cs4231_capture_open,
  1349. .close = snd_cs4231_capture_close,
  1350. .ioctl = snd_pcm_lib_ioctl,
  1351. .hw_params = snd_cs4231_capture_hw_params,
  1352. .hw_free = snd_cs4231_capture_hw_free,
  1353. .prepare = snd_cs4231_capture_prepare,
  1354. .trigger = snd_cs4231_trigger,
  1355. .pointer = snd_cs4231_capture_pointer,
  1356. };
  1357. int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm)
  1358. {
  1359. struct snd_pcm *pcm;
  1360. int err;
  1361. if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
  1362. return err;
  1363. spin_lock_init(&chip->reg_lock);
  1364. mutex_init(&chip->mce_mutex);
  1365. mutex_init(&chip->open_mutex);
  1366. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1367. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1368. /* global setup */
  1369. pcm->private_data = chip;
  1370. pcm->info_flags = 0;
  1371. if (chip->single_dma)
  1372. pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
  1373. if (chip->hardware != CS4231_HW_INTERWAVE)
  1374. pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
  1375. strcpy(pcm->name, snd_cs4231_chip_id(chip));
  1376. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1377. snd_dma_isa_data(),
  1378. 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
  1379. chip->pcm = pcm;
  1380. if (rpcm)
  1381. *rpcm = pcm;
  1382. return 0;
  1383. }
  1384. static void snd_cs4231_timer_free(struct snd_timer *timer)
  1385. {
  1386. struct snd_cs4231 *chip = timer->private_data;
  1387. chip->timer = NULL;
  1388. }
  1389. int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer)
  1390. {
  1391. struct snd_timer *timer;
  1392. struct snd_timer_id tid;
  1393. int err;
  1394. /* Timer initialization */
  1395. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1396. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1397. tid.card = chip->card->number;
  1398. tid.device = device;
  1399. tid.subdevice = 0;
  1400. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1401. return err;
  1402. strcpy(timer->name, snd_cs4231_chip_id(chip));
  1403. timer->private_data = chip;
  1404. timer->private_free = snd_cs4231_timer_free;
  1405. timer->hw = snd_cs4231_timer_table;
  1406. chip->timer = timer;
  1407. if (rtimer)
  1408. *rtimer = timer;
  1409. return 0;
  1410. }
  1411. /*
  1412. * MIXER part
  1413. */
  1414. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1415. {
  1416. static char *texts[4] = {
  1417. "Line", "Aux", "Mic", "Mix"
  1418. };
  1419. static char *opl3sa_texts[4] = {
  1420. "Line", "CD", "Mic", "Mix"
  1421. };
  1422. static char *gusmax_texts[4] = {
  1423. "Line", "Synth", "Mic", "Mix"
  1424. };
  1425. char **ptexts = texts;
  1426. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1427. snd_assert(chip->card != NULL, return -EINVAL);
  1428. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1429. uinfo->count = 2;
  1430. uinfo->value.enumerated.items = 4;
  1431. if (uinfo->value.enumerated.item > 3)
  1432. uinfo->value.enumerated.item = 3;
  1433. if (!strcmp(chip->card->driver, "GUS MAX"))
  1434. ptexts = gusmax_texts;
  1435. switch (chip->hardware) {
  1436. case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
  1437. case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
  1438. }
  1439. strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
  1440. return 0;
  1441. }
  1442. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1443. {
  1444. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1445. unsigned long flags;
  1446. spin_lock_irqsave(&chip->reg_lock, flags);
  1447. ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1448. ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1449. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1450. return 0;
  1451. }
  1452. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1453. {
  1454. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1455. unsigned long flags;
  1456. unsigned short left, right;
  1457. int change;
  1458. if (ucontrol->value.enumerated.item[0] > 3 ||
  1459. ucontrol->value.enumerated.item[1] > 3)
  1460. return -EINVAL;
  1461. left = ucontrol->value.enumerated.item[0] << 6;
  1462. right = ucontrol->value.enumerated.item[1] << 6;
  1463. spin_lock_irqsave(&chip->reg_lock, flags);
  1464. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1465. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1466. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1467. right != chip->image[CS4231_RIGHT_INPUT];
  1468. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1469. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1470. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1471. return change;
  1472. }
  1473. int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1474. {
  1475. int mask = (kcontrol->private_value >> 16) & 0xff;
  1476. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1477. uinfo->count = 1;
  1478. uinfo->value.integer.min = 0;
  1479. uinfo->value.integer.max = mask;
  1480. return 0;
  1481. }
  1482. int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1483. {
  1484. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1485. unsigned long flags;
  1486. int reg = kcontrol->private_value & 0xff;
  1487. int shift = (kcontrol->private_value >> 8) & 0xff;
  1488. int mask = (kcontrol->private_value >> 16) & 0xff;
  1489. int invert = (kcontrol->private_value >> 24) & 0xff;
  1490. spin_lock_irqsave(&chip->reg_lock, flags);
  1491. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1492. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1493. if (invert)
  1494. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1495. return 0;
  1496. }
  1497. int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1498. {
  1499. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1500. unsigned long flags;
  1501. int reg = kcontrol->private_value & 0xff;
  1502. int shift = (kcontrol->private_value >> 8) & 0xff;
  1503. int mask = (kcontrol->private_value >> 16) & 0xff;
  1504. int invert = (kcontrol->private_value >> 24) & 0xff;
  1505. int change;
  1506. unsigned short val;
  1507. val = (ucontrol->value.integer.value[0] & mask);
  1508. if (invert)
  1509. val = mask - val;
  1510. val <<= shift;
  1511. spin_lock_irqsave(&chip->reg_lock, flags);
  1512. val = (chip->image[reg] & ~(mask << shift)) | val;
  1513. change = val != chip->image[reg];
  1514. snd_cs4231_out(chip, reg, val);
  1515. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1516. return change;
  1517. }
  1518. int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1519. {
  1520. int mask = (kcontrol->private_value >> 24) & 0xff;
  1521. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1522. uinfo->count = 2;
  1523. uinfo->value.integer.min = 0;
  1524. uinfo->value.integer.max = mask;
  1525. return 0;
  1526. }
  1527. int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1530. unsigned long flags;
  1531. int left_reg = kcontrol->private_value & 0xff;
  1532. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1533. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1534. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1535. int mask = (kcontrol->private_value >> 24) & 0xff;
  1536. int invert = (kcontrol->private_value >> 22) & 1;
  1537. spin_lock_irqsave(&chip->reg_lock, flags);
  1538. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1539. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1540. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1541. if (invert) {
  1542. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1543. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1544. }
  1545. return 0;
  1546. }
  1547. int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1548. {
  1549. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1550. unsigned long flags;
  1551. int left_reg = kcontrol->private_value & 0xff;
  1552. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1553. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1554. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1555. int mask = (kcontrol->private_value >> 24) & 0xff;
  1556. int invert = (kcontrol->private_value >> 22) & 1;
  1557. int change;
  1558. unsigned short val1, val2;
  1559. val1 = ucontrol->value.integer.value[0] & mask;
  1560. val2 = ucontrol->value.integer.value[1] & mask;
  1561. if (invert) {
  1562. val1 = mask - val1;
  1563. val2 = mask - val2;
  1564. }
  1565. val1 <<= shift_left;
  1566. val2 <<= shift_right;
  1567. spin_lock_irqsave(&chip->reg_lock, flags);
  1568. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1569. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1570. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1571. snd_cs4231_out(chip, left_reg, val1);
  1572. snd_cs4231_out(chip, right_reg, val2);
  1573. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1574. return change;
  1575. }
  1576. static struct snd_kcontrol_new snd_cs4231_controls[] = {
  1577. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1578. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1579. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1580. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1581. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1582. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1583. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1584. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1585. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1586. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1587. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1588. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1589. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1590. {
  1591. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1592. .name = "Capture Source",
  1593. .info = snd_cs4231_info_mux,
  1594. .get = snd_cs4231_get_mux,
  1595. .put = snd_cs4231_put_mux,
  1596. },
  1597. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1598. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1599. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
  1600. };
  1601. int snd_cs4231_mixer(struct snd_cs4231 *chip)
  1602. {
  1603. struct snd_card *card;
  1604. unsigned int idx;
  1605. int err;
  1606. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1607. card = chip->card;
  1608. strcpy(card->mixername, chip->pcm->name);
  1609. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1610. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4231_controls[idx], chip))) < 0)
  1611. return err;
  1612. }
  1613. return 0;
  1614. }
  1615. EXPORT_SYMBOL(snd_cs4231_out);
  1616. EXPORT_SYMBOL(snd_cs4231_in);
  1617. EXPORT_SYMBOL(snd_cs4236_ext_out);
  1618. EXPORT_SYMBOL(snd_cs4236_ext_in);
  1619. EXPORT_SYMBOL(snd_cs4231_mce_up);
  1620. EXPORT_SYMBOL(snd_cs4231_mce_down);
  1621. EXPORT_SYMBOL(snd_cs4231_interrupt);
  1622. EXPORT_SYMBOL(snd_cs4231_chip_id);
  1623. EXPORT_SYMBOL(snd_cs4231_create);
  1624. EXPORT_SYMBOL(snd_cs4231_pcm);
  1625. EXPORT_SYMBOL(snd_cs4231_mixer);
  1626. EXPORT_SYMBOL(snd_cs4231_timer);
  1627. EXPORT_SYMBOL(snd_cs4231_info_single);
  1628. EXPORT_SYMBOL(snd_cs4231_get_single);
  1629. EXPORT_SYMBOL(snd_cs4231_put_single);
  1630. EXPORT_SYMBOL(snd_cs4231_info_double);
  1631. EXPORT_SYMBOL(snd_cs4231_get_double);
  1632. EXPORT_SYMBOL(snd_cs4231_put_double);
  1633. /*
  1634. * INIT part
  1635. */
  1636. static int __init alsa_cs4231_init(void)
  1637. {
  1638. return 0;
  1639. }
  1640. static void __exit alsa_cs4231_exit(void)
  1641. {
  1642. }
  1643. module_init(alsa_cs4231_init)
  1644. module_exit(alsa_cs4231_exit)