main.c 31 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/ssb/ssb.h>
  14. #include <linux/ssb/ssb_regs.h>
  15. #include <linux/ssb/ssb_driver_gige.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/pci.h>
  18. #include <linux/mmc/sdio_func.h>
  19. #include <linux/slab.h>
  20. #include <pcmcia/cs_types.h>
  21. #include <pcmcia/cs.h>
  22. #include <pcmcia/cistpl.h>
  23. #include <pcmcia/ds.h>
  24. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  25. MODULE_LICENSE("GPL");
  26. /* Temporary list of yet-to-be-attached buses */
  27. static LIST_HEAD(attach_queue);
  28. /* List if running buses */
  29. static LIST_HEAD(buses);
  30. /* Software ID counter */
  31. static unsigned int next_busnumber;
  32. /* buses_mutes locks the two buslists and the next_busnumber.
  33. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  34. static DEFINE_MUTEX(buses_mutex);
  35. /* There are differences in the codeflow, if the bus is
  36. * initialized from early boot, as various needed services
  37. * are not available early. This is a mechanism to delay
  38. * these initializations to after early boot has finished.
  39. * It's also used to avoid mutex locking, as that's not
  40. * available and needed early. */
  41. static bool ssb_is_early_boot = 1;
  42. static void ssb_buses_lock(void);
  43. static void ssb_buses_unlock(void);
  44. #ifdef CONFIG_SSB_PCIHOST
  45. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  46. {
  47. struct ssb_bus *bus;
  48. ssb_buses_lock();
  49. list_for_each_entry(bus, &buses, list) {
  50. if (bus->bustype == SSB_BUSTYPE_PCI &&
  51. bus->host_pci == pdev)
  52. goto found;
  53. }
  54. bus = NULL;
  55. found:
  56. ssb_buses_unlock();
  57. return bus;
  58. }
  59. #endif /* CONFIG_SSB_PCIHOST */
  60. #ifdef CONFIG_SSB_PCMCIAHOST
  61. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  62. {
  63. struct ssb_bus *bus;
  64. ssb_buses_lock();
  65. list_for_each_entry(bus, &buses, list) {
  66. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  67. bus->host_pcmcia == pdev)
  68. goto found;
  69. }
  70. bus = NULL;
  71. found:
  72. ssb_buses_unlock();
  73. return bus;
  74. }
  75. #endif /* CONFIG_SSB_PCMCIAHOST */
  76. #ifdef CONFIG_SSB_SDIOHOST
  77. struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
  78. {
  79. struct ssb_bus *bus;
  80. ssb_buses_lock();
  81. list_for_each_entry(bus, &buses, list) {
  82. if (bus->bustype == SSB_BUSTYPE_SDIO &&
  83. bus->host_sdio == func)
  84. goto found;
  85. }
  86. bus = NULL;
  87. found:
  88. ssb_buses_unlock();
  89. return bus;
  90. }
  91. #endif /* CONFIG_SSB_SDIOHOST */
  92. int ssb_for_each_bus_call(unsigned long data,
  93. int (*func)(struct ssb_bus *bus, unsigned long data))
  94. {
  95. struct ssb_bus *bus;
  96. int res;
  97. ssb_buses_lock();
  98. list_for_each_entry(bus, &buses, list) {
  99. res = func(bus, data);
  100. if (res >= 0) {
  101. ssb_buses_unlock();
  102. return res;
  103. }
  104. }
  105. ssb_buses_unlock();
  106. return -ENODEV;
  107. }
  108. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  109. {
  110. if (dev)
  111. get_device(dev->dev);
  112. return dev;
  113. }
  114. static void ssb_device_put(struct ssb_device *dev)
  115. {
  116. if (dev)
  117. put_device(dev->dev);
  118. }
  119. static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
  120. {
  121. if (drv)
  122. get_driver(&drv->drv);
  123. return drv;
  124. }
  125. static inline void ssb_driver_put(struct ssb_driver *drv)
  126. {
  127. if (drv)
  128. put_driver(&drv->drv);
  129. }
  130. static int ssb_device_resume(struct device *dev)
  131. {
  132. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  133. struct ssb_driver *ssb_drv;
  134. int err = 0;
  135. if (dev->driver) {
  136. ssb_drv = drv_to_ssb_drv(dev->driver);
  137. if (ssb_drv && ssb_drv->resume)
  138. err = ssb_drv->resume(ssb_dev);
  139. if (err)
  140. goto out;
  141. }
  142. out:
  143. return err;
  144. }
  145. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  146. {
  147. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  148. struct ssb_driver *ssb_drv;
  149. int err = 0;
  150. if (dev->driver) {
  151. ssb_drv = drv_to_ssb_drv(dev->driver);
  152. if (ssb_drv && ssb_drv->suspend)
  153. err = ssb_drv->suspend(ssb_dev, state);
  154. if (err)
  155. goto out;
  156. }
  157. out:
  158. return err;
  159. }
  160. int ssb_bus_resume(struct ssb_bus *bus)
  161. {
  162. int err;
  163. /* Reset HW state information in memory, so that HW is
  164. * completely reinitialized. */
  165. bus->mapped_device = NULL;
  166. #ifdef CONFIG_SSB_DRIVER_PCICORE
  167. bus->pcicore.setup_done = 0;
  168. #endif
  169. err = ssb_bus_powerup(bus, 0);
  170. if (err)
  171. return err;
  172. err = ssb_pcmcia_hardware_setup(bus);
  173. if (err) {
  174. ssb_bus_may_powerdown(bus);
  175. return err;
  176. }
  177. ssb_chipco_resume(&bus->chipco);
  178. ssb_bus_may_powerdown(bus);
  179. return 0;
  180. }
  181. EXPORT_SYMBOL(ssb_bus_resume);
  182. int ssb_bus_suspend(struct ssb_bus *bus)
  183. {
  184. ssb_chipco_suspend(&bus->chipco);
  185. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  186. return 0;
  187. }
  188. EXPORT_SYMBOL(ssb_bus_suspend);
  189. #ifdef CONFIG_SSB_SPROM
  190. /** ssb_devices_freeze - Freeze all devices on the bus.
  191. *
  192. * After freezing no device driver will be handling a device
  193. * on this bus anymore. ssb_devices_thaw() must be called after
  194. * a successful freeze to reactivate the devices.
  195. *
  196. * @bus: The bus.
  197. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  198. */
  199. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  200. {
  201. struct ssb_device *sdev;
  202. struct ssb_driver *sdrv;
  203. unsigned int i;
  204. memset(ctx, 0, sizeof(*ctx));
  205. ctx->bus = bus;
  206. SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  207. for (i = 0; i < bus->nr_devices; i++) {
  208. sdev = ssb_device_get(&bus->devices[i]);
  209. if (!sdev->dev || !sdev->dev->driver ||
  210. !device_is_registered(sdev->dev)) {
  211. ssb_device_put(sdev);
  212. continue;
  213. }
  214. sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
  215. if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
  216. ssb_device_put(sdev);
  217. continue;
  218. }
  219. sdrv->remove(sdev);
  220. ctx->device_frozen[i] = 1;
  221. }
  222. return 0;
  223. }
  224. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  225. *
  226. * This will re-attach the device drivers and re-init the devices.
  227. *
  228. * @ctx: The context structure from ssb_devices_freeze()
  229. */
  230. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  231. {
  232. struct ssb_bus *bus = ctx->bus;
  233. struct ssb_device *sdev;
  234. struct ssb_driver *sdrv;
  235. unsigned int i;
  236. int err, result = 0;
  237. for (i = 0; i < bus->nr_devices; i++) {
  238. if (!ctx->device_frozen[i])
  239. continue;
  240. sdev = &bus->devices[i];
  241. if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
  242. continue;
  243. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  244. if (SSB_WARN_ON(!sdrv || !sdrv->probe))
  245. continue;
  246. err = sdrv->probe(sdev, &sdev->id);
  247. if (err) {
  248. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  249. dev_name(sdev->dev));
  250. result = err;
  251. }
  252. ssb_driver_put(sdrv);
  253. ssb_device_put(sdev);
  254. }
  255. return result;
  256. }
  257. #endif /* CONFIG_SSB_SPROM */
  258. static void ssb_device_shutdown(struct device *dev)
  259. {
  260. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  261. struct ssb_driver *ssb_drv;
  262. if (!dev->driver)
  263. return;
  264. ssb_drv = drv_to_ssb_drv(dev->driver);
  265. if (ssb_drv && ssb_drv->shutdown)
  266. ssb_drv->shutdown(ssb_dev);
  267. }
  268. static int ssb_device_remove(struct device *dev)
  269. {
  270. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  271. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  272. if (ssb_drv && ssb_drv->remove)
  273. ssb_drv->remove(ssb_dev);
  274. ssb_device_put(ssb_dev);
  275. return 0;
  276. }
  277. static int ssb_device_probe(struct device *dev)
  278. {
  279. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  280. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  281. int err = 0;
  282. ssb_device_get(ssb_dev);
  283. if (ssb_drv && ssb_drv->probe)
  284. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  285. if (err)
  286. ssb_device_put(ssb_dev);
  287. return err;
  288. }
  289. static int ssb_match_devid(const struct ssb_device_id *tabid,
  290. const struct ssb_device_id *devid)
  291. {
  292. if ((tabid->vendor != devid->vendor) &&
  293. tabid->vendor != SSB_ANY_VENDOR)
  294. return 0;
  295. if ((tabid->coreid != devid->coreid) &&
  296. tabid->coreid != SSB_ANY_ID)
  297. return 0;
  298. if ((tabid->revision != devid->revision) &&
  299. tabid->revision != SSB_ANY_REV)
  300. return 0;
  301. return 1;
  302. }
  303. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  304. {
  305. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  306. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  307. const struct ssb_device_id *id;
  308. for (id = ssb_drv->id_table;
  309. id->vendor || id->coreid || id->revision;
  310. id++) {
  311. if (ssb_match_devid(id, &ssb_dev->id))
  312. return 1; /* found */
  313. }
  314. return 0;
  315. }
  316. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  317. {
  318. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  319. if (!dev)
  320. return -ENODEV;
  321. return add_uevent_var(env,
  322. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  323. ssb_dev->id.vendor, ssb_dev->id.coreid,
  324. ssb_dev->id.revision);
  325. }
  326. static struct bus_type ssb_bustype = {
  327. .name = "ssb",
  328. .match = ssb_bus_match,
  329. .probe = ssb_device_probe,
  330. .remove = ssb_device_remove,
  331. .shutdown = ssb_device_shutdown,
  332. .suspend = ssb_device_suspend,
  333. .resume = ssb_device_resume,
  334. .uevent = ssb_device_uevent,
  335. };
  336. static void ssb_buses_lock(void)
  337. {
  338. /* See the comment at the ssb_is_early_boot definition */
  339. if (!ssb_is_early_boot)
  340. mutex_lock(&buses_mutex);
  341. }
  342. static void ssb_buses_unlock(void)
  343. {
  344. /* See the comment at the ssb_is_early_boot definition */
  345. if (!ssb_is_early_boot)
  346. mutex_unlock(&buses_mutex);
  347. }
  348. static void ssb_devices_unregister(struct ssb_bus *bus)
  349. {
  350. struct ssb_device *sdev;
  351. int i;
  352. for (i = bus->nr_devices - 1; i >= 0; i--) {
  353. sdev = &(bus->devices[i]);
  354. if (sdev->dev)
  355. device_unregister(sdev->dev);
  356. }
  357. }
  358. void ssb_bus_unregister(struct ssb_bus *bus)
  359. {
  360. ssb_buses_lock();
  361. ssb_devices_unregister(bus);
  362. list_del(&bus->list);
  363. ssb_buses_unlock();
  364. ssb_pcmcia_exit(bus);
  365. ssb_pci_exit(bus);
  366. ssb_iounmap(bus);
  367. }
  368. EXPORT_SYMBOL(ssb_bus_unregister);
  369. static void ssb_release_dev(struct device *dev)
  370. {
  371. struct __ssb_dev_wrapper *devwrap;
  372. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  373. kfree(devwrap);
  374. }
  375. static int ssb_devices_register(struct ssb_bus *bus)
  376. {
  377. struct ssb_device *sdev;
  378. struct device *dev;
  379. struct __ssb_dev_wrapper *devwrap;
  380. int i, err = 0;
  381. int dev_idx = 0;
  382. for (i = 0; i < bus->nr_devices; i++) {
  383. sdev = &(bus->devices[i]);
  384. /* We don't register SSB-system devices to the kernel,
  385. * as the drivers for them are built into SSB. */
  386. switch (sdev->id.coreid) {
  387. case SSB_DEV_CHIPCOMMON:
  388. case SSB_DEV_PCI:
  389. case SSB_DEV_PCIE:
  390. case SSB_DEV_PCMCIA:
  391. case SSB_DEV_MIPS:
  392. case SSB_DEV_MIPS_3302:
  393. case SSB_DEV_EXTIF:
  394. continue;
  395. }
  396. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  397. if (!devwrap) {
  398. ssb_printk(KERN_ERR PFX
  399. "Could not allocate device\n");
  400. err = -ENOMEM;
  401. goto error;
  402. }
  403. dev = &devwrap->dev;
  404. devwrap->sdev = sdev;
  405. dev->release = ssb_release_dev;
  406. dev->bus = &ssb_bustype;
  407. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  408. switch (bus->bustype) {
  409. case SSB_BUSTYPE_PCI:
  410. #ifdef CONFIG_SSB_PCIHOST
  411. sdev->irq = bus->host_pci->irq;
  412. dev->parent = &bus->host_pci->dev;
  413. sdev->dma_dev = dev->parent;
  414. #endif
  415. break;
  416. case SSB_BUSTYPE_PCMCIA:
  417. #ifdef CONFIG_SSB_PCMCIAHOST
  418. sdev->irq = bus->host_pcmcia->irq;
  419. dev->parent = &bus->host_pcmcia->dev;
  420. #endif
  421. break;
  422. case SSB_BUSTYPE_SDIO:
  423. #ifdef CONFIG_SSB_SDIOHOST
  424. dev->parent = &bus->host_sdio->dev;
  425. #endif
  426. break;
  427. case SSB_BUSTYPE_SSB:
  428. dev->dma_mask = &dev->coherent_dma_mask;
  429. sdev->dma_dev = dev;
  430. break;
  431. }
  432. sdev->dev = dev;
  433. err = device_register(dev);
  434. if (err) {
  435. ssb_printk(KERN_ERR PFX
  436. "Could not register %s\n",
  437. dev_name(dev));
  438. /* Set dev to NULL to not unregister
  439. * dev on error unwinding. */
  440. sdev->dev = NULL;
  441. kfree(devwrap);
  442. goto error;
  443. }
  444. dev_idx++;
  445. }
  446. return 0;
  447. error:
  448. /* Unwind the already registered devices. */
  449. ssb_devices_unregister(bus);
  450. return err;
  451. }
  452. /* Needs ssb_buses_lock() */
  453. static int ssb_attach_queued_buses(void)
  454. {
  455. struct ssb_bus *bus, *n;
  456. int err = 0;
  457. int drop_them_all = 0;
  458. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  459. if (drop_them_all) {
  460. list_del(&bus->list);
  461. continue;
  462. }
  463. /* Can't init the PCIcore in ssb_bus_register(), as that
  464. * is too early in boot for embedded systems
  465. * (no udelay() available). So do it here in attach stage.
  466. */
  467. err = ssb_bus_powerup(bus, 0);
  468. if (err)
  469. goto error;
  470. ssb_pcicore_init(&bus->pcicore);
  471. ssb_bus_may_powerdown(bus);
  472. err = ssb_devices_register(bus);
  473. error:
  474. if (err) {
  475. drop_them_all = 1;
  476. list_del(&bus->list);
  477. continue;
  478. }
  479. list_move_tail(&bus->list, &buses);
  480. }
  481. return err;
  482. }
  483. static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
  484. {
  485. struct ssb_bus *bus = dev->bus;
  486. offset += dev->core_index * SSB_CORE_SIZE;
  487. return readb(bus->mmio + offset);
  488. }
  489. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  490. {
  491. struct ssb_bus *bus = dev->bus;
  492. offset += dev->core_index * SSB_CORE_SIZE;
  493. return readw(bus->mmio + offset);
  494. }
  495. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  496. {
  497. struct ssb_bus *bus = dev->bus;
  498. offset += dev->core_index * SSB_CORE_SIZE;
  499. return readl(bus->mmio + offset);
  500. }
  501. #ifdef CONFIG_SSB_BLOCKIO
  502. static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
  503. size_t count, u16 offset, u8 reg_width)
  504. {
  505. struct ssb_bus *bus = dev->bus;
  506. void __iomem *addr;
  507. offset += dev->core_index * SSB_CORE_SIZE;
  508. addr = bus->mmio + offset;
  509. switch (reg_width) {
  510. case sizeof(u8): {
  511. u8 *buf = buffer;
  512. while (count) {
  513. *buf = __raw_readb(addr);
  514. buf++;
  515. count--;
  516. }
  517. break;
  518. }
  519. case sizeof(u16): {
  520. __le16 *buf = buffer;
  521. SSB_WARN_ON(count & 1);
  522. while (count) {
  523. *buf = (__force __le16)__raw_readw(addr);
  524. buf++;
  525. count -= 2;
  526. }
  527. break;
  528. }
  529. case sizeof(u32): {
  530. __le32 *buf = buffer;
  531. SSB_WARN_ON(count & 3);
  532. while (count) {
  533. *buf = (__force __le32)__raw_readl(addr);
  534. buf++;
  535. count -= 4;
  536. }
  537. break;
  538. }
  539. default:
  540. SSB_WARN_ON(1);
  541. }
  542. }
  543. #endif /* CONFIG_SSB_BLOCKIO */
  544. static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
  545. {
  546. struct ssb_bus *bus = dev->bus;
  547. offset += dev->core_index * SSB_CORE_SIZE;
  548. writeb(value, bus->mmio + offset);
  549. }
  550. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  551. {
  552. struct ssb_bus *bus = dev->bus;
  553. offset += dev->core_index * SSB_CORE_SIZE;
  554. writew(value, bus->mmio + offset);
  555. }
  556. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  557. {
  558. struct ssb_bus *bus = dev->bus;
  559. offset += dev->core_index * SSB_CORE_SIZE;
  560. writel(value, bus->mmio + offset);
  561. }
  562. #ifdef CONFIG_SSB_BLOCKIO
  563. static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
  564. size_t count, u16 offset, u8 reg_width)
  565. {
  566. struct ssb_bus *bus = dev->bus;
  567. void __iomem *addr;
  568. offset += dev->core_index * SSB_CORE_SIZE;
  569. addr = bus->mmio + offset;
  570. switch (reg_width) {
  571. case sizeof(u8): {
  572. const u8 *buf = buffer;
  573. while (count) {
  574. __raw_writeb(*buf, addr);
  575. buf++;
  576. count--;
  577. }
  578. break;
  579. }
  580. case sizeof(u16): {
  581. const __le16 *buf = buffer;
  582. SSB_WARN_ON(count & 1);
  583. while (count) {
  584. __raw_writew((__force u16)(*buf), addr);
  585. buf++;
  586. count -= 2;
  587. }
  588. break;
  589. }
  590. case sizeof(u32): {
  591. const __le32 *buf = buffer;
  592. SSB_WARN_ON(count & 3);
  593. while (count) {
  594. __raw_writel((__force u32)(*buf), addr);
  595. buf++;
  596. count -= 4;
  597. }
  598. break;
  599. }
  600. default:
  601. SSB_WARN_ON(1);
  602. }
  603. }
  604. #endif /* CONFIG_SSB_BLOCKIO */
  605. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  606. static const struct ssb_bus_ops ssb_ssb_ops = {
  607. .read8 = ssb_ssb_read8,
  608. .read16 = ssb_ssb_read16,
  609. .read32 = ssb_ssb_read32,
  610. .write8 = ssb_ssb_write8,
  611. .write16 = ssb_ssb_write16,
  612. .write32 = ssb_ssb_write32,
  613. #ifdef CONFIG_SSB_BLOCKIO
  614. .block_read = ssb_ssb_block_read,
  615. .block_write = ssb_ssb_block_write,
  616. #endif
  617. };
  618. static int ssb_fetch_invariants(struct ssb_bus *bus,
  619. ssb_invariants_func_t get_invariants)
  620. {
  621. struct ssb_init_invariants iv;
  622. int err;
  623. memset(&iv, 0, sizeof(iv));
  624. err = get_invariants(bus, &iv);
  625. if (err)
  626. goto out;
  627. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  628. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  629. bus->has_cardbus_slot = iv.has_cardbus_slot;
  630. out:
  631. return err;
  632. }
  633. static int ssb_bus_register(struct ssb_bus *bus,
  634. ssb_invariants_func_t get_invariants,
  635. unsigned long baseaddr)
  636. {
  637. int err;
  638. spin_lock_init(&bus->bar_lock);
  639. INIT_LIST_HEAD(&bus->list);
  640. #ifdef CONFIG_SSB_EMBEDDED
  641. spin_lock_init(&bus->gpio_lock);
  642. #endif
  643. /* Powerup the bus */
  644. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  645. if (err)
  646. goto out;
  647. /* Init SDIO-host device (if any), before the scan */
  648. err = ssb_sdio_init(bus);
  649. if (err)
  650. goto err_disable_xtal;
  651. ssb_buses_lock();
  652. bus->busnumber = next_busnumber;
  653. /* Scan for devices (cores) */
  654. err = ssb_bus_scan(bus, baseaddr);
  655. if (err)
  656. goto err_sdio_exit;
  657. /* Init PCI-host device (if any) */
  658. err = ssb_pci_init(bus);
  659. if (err)
  660. goto err_unmap;
  661. /* Init PCMCIA-host device (if any) */
  662. err = ssb_pcmcia_init(bus);
  663. if (err)
  664. goto err_pci_exit;
  665. /* Initialize basic system devices (if available) */
  666. err = ssb_bus_powerup(bus, 0);
  667. if (err)
  668. goto err_pcmcia_exit;
  669. ssb_chipcommon_init(&bus->chipco);
  670. ssb_mipscore_init(&bus->mipscore);
  671. err = ssb_fetch_invariants(bus, get_invariants);
  672. if (err) {
  673. ssb_bus_may_powerdown(bus);
  674. goto err_pcmcia_exit;
  675. }
  676. ssb_bus_may_powerdown(bus);
  677. /* Queue it for attach.
  678. * See the comment at the ssb_is_early_boot definition. */
  679. list_add_tail(&bus->list, &attach_queue);
  680. if (!ssb_is_early_boot) {
  681. /* This is not early boot, so we must attach the bus now */
  682. err = ssb_attach_queued_buses();
  683. if (err)
  684. goto err_dequeue;
  685. }
  686. next_busnumber++;
  687. ssb_buses_unlock();
  688. out:
  689. return err;
  690. err_dequeue:
  691. list_del(&bus->list);
  692. err_pcmcia_exit:
  693. ssb_pcmcia_exit(bus);
  694. err_pci_exit:
  695. ssb_pci_exit(bus);
  696. err_unmap:
  697. ssb_iounmap(bus);
  698. err_sdio_exit:
  699. ssb_sdio_exit(bus);
  700. err_disable_xtal:
  701. ssb_buses_unlock();
  702. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  703. return err;
  704. }
  705. #ifdef CONFIG_SSB_PCIHOST
  706. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  707. struct pci_dev *host_pci)
  708. {
  709. int err;
  710. bus->bustype = SSB_BUSTYPE_PCI;
  711. bus->host_pci = host_pci;
  712. bus->ops = &ssb_pci_ops;
  713. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  714. if (!err) {
  715. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  716. "PCI device %s\n", dev_name(&host_pci->dev));
  717. } else {
  718. ssb_printk(KERN_ERR PFX "Failed to register PCI version"
  719. " of SSB with error %d\n", err);
  720. }
  721. return err;
  722. }
  723. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  724. #endif /* CONFIG_SSB_PCIHOST */
  725. #ifdef CONFIG_SSB_PCMCIAHOST
  726. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  727. struct pcmcia_device *pcmcia_dev,
  728. unsigned long baseaddr)
  729. {
  730. int err;
  731. bus->bustype = SSB_BUSTYPE_PCMCIA;
  732. bus->host_pcmcia = pcmcia_dev;
  733. bus->ops = &ssb_pcmcia_ops;
  734. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  735. if (!err) {
  736. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  737. "PCMCIA device %s\n", pcmcia_dev->devname);
  738. }
  739. return err;
  740. }
  741. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  742. #endif /* CONFIG_SSB_PCMCIAHOST */
  743. #ifdef CONFIG_SSB_SDIOHOST
  744. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  745. unsigned int quirks)
  746. {
  747. int err;
  748. bus->bustype = SSB_BUSTYPE_SDIO;
  749. bus->host_sdio = func;
  750. bus->ops = &ssb_sdio_ops;
  751. bus->quirks = quirks;
  752. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  753. if (!err) {
  754. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  755. "SDIO device %s\n", sdio_func_id(func));
  756. }
  757. return err;
  758. }
  759. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  760. #endif /* CONFIG_SSB_PCMCIAHOST */
  761. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  762. unsigned long baseaddr,
  763. ssb_invariants_func_t get_invariants)
  764. {
  765. int err;
  766. bus->bustype = SSB_BUSTYPE_SSB;
  767. bus->ops = &ssb_ssb_ops;
  768. err = ssb_bus_register(bus, get_invariants, baseaddr);
  769. if (!err) {
  770. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  771. "address 0x%08lX\n", baseaddr);
  772. }
  773. return err;
  774. }
  775. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  776. {
  777. drv->drv.name = drv->name;
  778. drv->drv.bus = &ssb_bustype;
  779. drv->drv.owner = owner;
  780. return driver_register(&drv->drv);
  781. }
  782. EXPORT_SYMBOL(__ssb_driver_register);
  783. void ssb_driver_unregister(struct ssb_driver *drv)
  784. {
  785. driver_unregister(&drv->drv);
  786. }
  787. EXPORT_SYMBOL(ssb_driver_unregister);
  788. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  789. {
  790. struct ssb_bus *bus = dev->bus;
  791. struct ssb_device *ent;
  792. int i;
  793. for (i = 0; i < bus->nr_devices; i++) {
  794. ent = &(bus->devices[i]);
  795. if (ent->id.vendor != dev->id.vendor)
  796. continue;
  797. if (ent->id.coreid != dev->id.coreid)
  798. continue;
  799. ent->devtypedata = data;
  800. }
  801. }
  802. EXPORT_SYMBOL(ssb_set_devtypedata);
  803. static u32 clkfactor_f6_resolve(u32 v)
  804. {
  805. /* map the magic values */
  806. switch (v) {
  807. case SSB_CHIPCO_CLK_F6_2:
  808. return 2;
  809. case SSB_CHIPCO_CLK_F6_3:
  810. return 3;
  811. case SSB_CHIPCO_CLK_F6_4:
  812. return 4;
  813. case SSB_CHIPCO_CLK_F6_5:
  814. return 5;
  815. case SSB_CHIPCO_CLK_F6_6:
  816. return 6;
  817. case SSB_CHIPCO_CLK_F6_7:
  818. return 7;
  819. }
  820. return 0;
  821. }
  822. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  823. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  824. {
  825. u32 n1, n2, clock, m1, m2, m3, mc;
  826. n1 = (n & SSB_CHIPCO_CLK_N1);
  827. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  828. switch (plltype) {
  829. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  830. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  831. return SSB_CHIPCO_CLK_T6_M0;
  832. return SSB_CHIPCO_CLK_T6_M1;
  833. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  834. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  835. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  836. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  837. n1 = clkfactor_f6_resolve(n1);
  838. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  839. break;
  840. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  841. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  842. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  843. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  844. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  845. break;
  846. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  847. return 100000000;
  848. default:
  849. SSB_WARN_ON(1);
  850. }
  851. switch (plltype) {
  852. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  853. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  854. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  855. break;
  856. default:
  857. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  858. }
  859. if (!clock)
  860. return 0;
  861. m1 = (m & SSB_CHIPCO_CLK_M1);
  862. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  863. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  864. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  865. switch (plltype) {
  866. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  867. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  868. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  869. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  870. m1 = clkfactor_f6_resolve(m1);
  871. if ((plltype == SSB_PLLTYPE_1) ||
  872. (plltype == SSB_PLLTYPE_3))
  873. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  874. else
  875. m2 = clkfactor_f6_resolve(m2);
  876. m3 = clkfactor_f6_resolve(m3);
  877. switch (mc) {
  878. case SSB_CHIPCO_CLK_MC_BYPASS:
  879. return clock;
  880. case SSB_CHIPCO_CLK_MC_M1:
  881. return (clock / m1);
  882. case SSB_CHIPCO_CLK_MC_M1M2:
  883. return (clock / (m1 * m2));
  884. case SSB_CHIPCO_CLK_MC_M1M2M3:
  885. return (clock / (m1 * m2 * m3));
  886. case SSB_CHIPCO_CLK_MC_M1M3:
  887. return (clock / (m1 * m3));
  888. }
  889. return 0;
  890. case SSB_PLLTYPE_2:
  891. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  892. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  893. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  894. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  895. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  896. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  897. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  898. clock /= m1;
  899. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  900. clock /= m2;
  901. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  902. clock /= m3;
  903. return clock;
  904. default:
  905. SSB_WARN_ON(1);
  906. }
  907. return 0;
  908. }
  909. /* Get the current speed the backplane is running at */
  910. u32 ssb_clockspeed(struct ssb_bus *bus)
  911. {
  912. u32 rate;
  913. u32 plltype;
  914. u32 clkctl_n, clkctl_m;
  915. if (ssb_extif_available(&bus->extif))
  916. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  917. &clkctl_n, &clkctl_m);
  918. else if (bus->chipco.dev)
  919. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  920. &clkctl_n, &clkctl_m);
  921. else
  922. return 0;
  923. if (bus->chip_id == 0x5365) {
  924. rate = 100000000;
  925. } else {
  926. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  927. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  928. rate /= 2;
  929. }
  930. return rate;
  931. }
  932. EXPORT_SYMBOL(ssb_clockspeed);
  933. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  934. {
  935. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  936. /* The REJECT bit changed position in TMSLOW between
  937. * Backplane revisions. */
  938. switch (rev) {
  939. case SSB_IDLOW_SSBREV_22:
  940. return SSB_TMSLOW_REJECT_22;
  941. case SSB_IDLOW_SSBREV_23:
  942. return SSB_TMSLOW_REJECT_23;
  943. case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
  944. case SSB_IDLOW_SSBREV_25: /* same here */
  945. case SSB_IDLOW_SSBREV_26: /* same here */
  946. case SSB_IDLOW_SSBREV_27: /* same here */
  947. return SSB_TMSLOW_REJECT_23; /* this is a guess */
  948. default:
  949. printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  950. WARN_ON(1);
  951. }
  952. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  953. }
  954. int ssb_device_is_enabled(struct ssb_device *dev)
  955. {
  956. u32 val;
  957. u32 reject;
  958. reject = ssb_tmslow_reject_bitmask(dev);
  959. val = ssb_read32(dev, SSB_TMSLOW);
  960. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  961. return (val == SSB_TMSLOW_CLOCK);
  962. }
  963. EXPORT_SYMBOL(ssb_device_is_enabled);
  964. static void ssb_flush_tmslow(struct ssb_device *dev)
  965. {
  966. /* Make _really_ sure the device has finished the TMSLOW
  967. * register write transaction, as we risk running into
  968. * a machine check exception otherwise.
  969. * Do this by reading the register back to commit the
  970. * PCI write and delay an additional usec for the device
  971. * to react to the change. */
  972. ssb_read32(dev, SSB_TMSLOW);
  973. udelay(1);
  974. }
  975. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  976. {
  977. u32 val;
  978. ssb_device_disable(dev, core_specific_flags);
  979. ssb_write32(dev, SSB_TMSLOW,
  980. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  981. SSB_TMSLOW_FGC | core_specific_flags);
  982. ssb_flush_tmslow(dev);
  983. /* Clear SERR if set. This is a hw bug workaround. */
  984. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  985. ssb_write32(dev, SSB_TMSHIGH, 0);
  986. val = ssb_read32(dev, SSB_IMSTATE);
  987. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  988. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  989. ssb_write32(dev, SSB_IMSTATE, val);
  990. }
  991. ssb_write32(dev, SSB_TMSLOW,
  992. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  993. core_specific_flags);
  994. ssb_flush_tmslow(dev);
  995. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  996. core_specific_flags);
  997. ssb_flush_tmslow(dev);
  998. }
  999. EXPORT_SYMBOL(ssb_device_enable);
  1000. /* Wait for a bit in a register to get set or unset.
  1001. * timeout is in units of ten-microseconds */
  1002. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  1003. int timeout, int set)
  1004. {
  1005. int i;
  1006. u32 val;
  1007. for (i = 0; i < timeout; i++) {
  1008. val = ssb_read32(dev, reg);
  1009. if (set) {
  1010. if (val & bitmask)
  1011. return 0;
  1012. } else {
  1013. if (!(val & bitmask))
  1014. return 0;
  1015. }
  1016. udelay(10);
  1017. }
  1018. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  1019. "register %04X to %s.\n",
  1020. bitmask, reg, (set ? "set" : "clear"));
  1021. return -ETIMEDOUT;
  1022. }
  1023. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  1024. {
  1025. u32 reject;
  1026. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  1027. return;
  1028. reject = ssb_tmslow_reject_bitmask(dev);
  1029. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  1030. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  1031. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  1032. ssb_write32(dev, SSB_TMSLOW,
  1033. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  1034. reject | SSB_TMSLOW_RESET |
  1035. core_specific_flags);
  1036. ssb_flush_tmslow(dev);
  1037. ssb_write32(dev, SSB_TMSLOW,
  1038. reject | SSB_TMSLOW_RESET |
  1039. core_specific_flags);
  1040. ssb_flush_tmslow(dev);
  1041. }
  1042. EXPORT_SYMBOL(ssb_device_disable);
  1043. u32 ssb_dma_translation(struct ssb_device *dev)
  1044. {
  1045. switch (dev->bus->bustype) {
  1046. case SSB_BUSTYPE_SSB:
  1047. return 0;
  1048. case SSB_BUSTYPE_PCI:
  1049. return SSB_PCI_DMA;
  1050. default:
  1051. __ssb_dma_not_implemented(dev);
  1052. }
  1053. return 0;
  1054. }
  1055. EXPORT_SYMBOL(ssb_dma_translation);
  1056. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  1057. {
  1058. struct ssb_chipcommon *cc;
  1059. int err = 0;
  1060. /* On buses where more than one core may be working
  1061. * at a time, we must not powerdown stuff if there are
  1062. * still cores that may want to run. */
  1063. if (bus->bustype == SSB_BUSTYPE_SSB)
  1064. goto out;
  1065. cc = &bus->chipco;
  1066. if (!cc->dev)
  1067. goto out;
  1068. if (cc->dev->id.revision < 5)
  1069. goto out;
  1070. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1071. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1072. if (err)
  1073. goto error;
  1074. out:
  1075. #ifdef CONFIG_SSB_DEBUG
  1076. bus->powered_up = 0;
  1077. #endif
  1078. return err;
  1079. error:
  1080. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  1081. goto out;
  1082. }
  1083. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1084. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1085. {
  1086. struct ssb_chipcommon *cc;
  1087. int err;
  1088. enum ssb_clkmode mode;
  1089. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1090. if (err)
  1091. goto error;
  1092. cc = &bus->chipco;
  1093. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1094. ssb_chipco_set_clockmode(cc, mode);
  1095. #ifdef CONFIG_SSB_DEBUG
  1096. bus->powered_up = 1;
  1097. #endif
  1098. return 0;
  1099. error:
  1100. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  1101. return err;
  1102. }
  1103. EXPORT_SYMBOL(ssb_bus_powerup);
  1104. u32 ssb_admatch_base(u32 adm)
  1105. {
  1106. u32 base = 0;
  1107. switch (adm & SSB_ADM_TYPE) {
  1108. case SSB_ADM_TYPE0:
  1109. base = (adm & SSB_ADM_BASE0);
  1110. break;
  1111. case SSB_ADM_TYPE1:
  1112. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1113. base = (adm & SSB_ADM_BASE1);
  1114. break;
  1115. case SSB_ADM_TYPE2:
  1116. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1117. base = (adm & SSB_ADM_BASE2);
  1118. break;
  1119. default:
  1120. SSB_WARN_ON(1);
  1121. }
  1122. return base;
  1123. }
  1124. EXPORT_SYMBOL(ssb_admatch_base);
  1125. u32 ssb_admatch_size(u32 adm)
  1126. {
  1127. u32 size = 0;
  1128. switch (adm & SSB_ADM_TYPE) {
  1129. case SSB_ADM_TYPE0:
  1130. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1131. break;
  1132. case SSB_ADM_TYPE1:
  1133. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1134. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1135. break;
  1136. case SSB_ADM_TYPE2:
  1137. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1138. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1139. break;
  1140. default:
  1141. SSB_WARN_ON(1);
  1142. }
  1143. size = (1 << (size + 1));
  1144. return size;
  1145. }
  1146. EXPORT_SYMBOL(ssb_admatch_size);
  1147. static int __init ssb_modinit(void)
  1148. {
  1149. int err;
  1150. /* See the comment at the ssb_is_early_boot definition */
  1151. ssb_is_early_boot = 0;
  1152. err = bus_register(&ssb_bustype);
  1153. if (err)
  1154. return err;
  1155. /* Maybe we already registered some buses at early boot.
  1156. * Check for this and attach them
  1157. */
  1158. ssb_buses_lock();
  1159. err = ssb_attach_queued_buses();
  1160. ssb_buses_unlock();
  1161. if (err) {
  1162. bus_unregister(&ssb_bustype);
  1163. goto out;
  1164. }
  1165. err = b43_pci_ssb_bridge_init();
  1166. if (err) {
  1167. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  1168. "initialization failed\n");
  1169. /* don't fail SSB init because of this */
  1170. err = 0;
  1171. }
  1172. err = ssb_gige_init();
  1173. if (err) {
  1174. ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
  1175. "driver initialization failed\n");
  1176. /* don't fail SSB init because of this */
  1177. err = 0;
  1178. }
  1179. out:
  1180. return err;
  1181. }
  1182. /* ssb must be initialized after PCI but before the ssb drivers.
  1183. * That means we must use some initcall between subsys_initcall
  1184. * and device_initcall. */
  1185. fs_initcall(ssb_modinit);
  1186. static void __exit ssb_modexit(void)
  1187. {
  1188. ssb_gige_exit();
  1189. b43_pci_ssb_bridge_exit();
  1190. bus_unregister(&ssb_bustype);
  1191. }
  1192. module_exit(ssb_modexit)