ql4_mbx.c 34 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine isssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. /* Make sure that pointers are valid */
  33. if (!mbx_cmd || !mbx_sts) {
  34. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  35. "pointer\n", ha->host_no, __func__));
  36. return status;
  37. }
  38. /* Mailbox code active */
  39. wait_count = MBOX_TOV * 100;
  40. while (wait_count--) {
  41. mutex_lock(&ha->mbox_sem);
  42. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  43. set_bit(AF_MBOX_COMMAND, &ha->flags);
  44. mutex_unlock(&ha->mbox_sem);
  45. break;
  46. }
  47. mutex_unlock(&ha->mbox_sem);
  48. if (!wait_count) {
  49. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  50. ha->host_no, __func__));
  51. return status;
  52. }
  53. msleep(10);
  54. }
  55. /* To prevent overwriting mailbox registers for a command that has
  56. * not yet been serviced, check to see if an active command
  57. * (AEN, IOCB, etc.) is interrupting, then service it.
  58. * -----------------------------------------------------------------
  59. */
  60. spin_lock_irqsave(&ha->hardware_lock, flags);
  61. if (is_qla8022(ha)) {
  62. intr_status = readl(&ha->qla4_8xxx_reg->host_int);
  63. if (intr_status & ISRX_82XX_RISC_INT) {
  64. /* Service existing interrupt */
  65. DEBUG2(printk("scsi%ld: %s: "
  66. "servicing existing interrupt\n",
  67. ha->host_no, __func__));
  68. intr_status = readl(&ha->qla4_8xxx_reg->host_status);
  69. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  70. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  71. if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  72. test_bit(AF_INTx_ENABLED, &ha->flags))
  73. qla4_8xxx_wr_32(ha,
  74. ha->nx_legacy_intr.tgt_mask_reg,
  75. 0xfbff);
  76. }
  77. } else {
  78. intr_status = readl(&ha->reg->ctrl_status);
  79. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  80. /* Service existing interrupt */
  81. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  82. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  83. }
  84. }
  85. ha->mbox_status_count = outCount;
  86. for (i = 0; i < outCount; i++)
  87. ha->mbox_status[i] = 0;
  88. if (is_qla8022(ha)) {
  89. /* Load all mailbox registers, except mailbox 0. */
  90. DEBUG5(
  91. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  92. for (i = 0; i < inCount; i++)
  93. printk("mb%d=%04x ", i, mbx_cmd[i]);
  94. printk("\n"));
  95. for (i = 1; i < inCount; i++)
  96. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  97. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  98. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  99. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  100. } else {
  101. /* Load all mailbox registers, except mailbox 0. */
  102. for (i = 1; i < inCount; i++)
  103. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  104. /* Wakeup firmware */
  105. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  106. readl(&ha->reg->mailbox[0]);
  107. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  108. readl(&ha->reg->ctrl_status);
  109. }
  110. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  111. /* Wait for completion */
  112. /*
  113. * If we don't want status, don't wait for the mailbox command to
  114. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  115. * you must poll the inbound Interrupt Mask for completion.
  116. */
  117. if (outCount == 0) {
  118. status = QLA_SUCCESS;
  119. goto mbox_exit;
  120. }
  121. /*
  122. * Wait for completion: Poll or completion queue
  123. */
  124. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  125. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  126. test_bit(AF_ONLINE, &ha->flags) &&
  127. !test_bit(AF_HBA_GOING_AWAY, &ha->flags)) {
  128. /* Do not poll for completion. Use completion queue */
  129. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  130. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  131. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  132. } else {
  133. /* Poll for command to complete */
  134. wait_count = jiffies + MBOX_TOV * HZ;
  135. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  136. if (time_after_eq(jiffies, wait_count))
  137. break;
  138. /*
  139. * Service the interrupt.
  140. * The ISR will save the mailbox status registers
  141. * to a temporary storage location in the adapter
  142. * structure.
  143. */
  144. spin_lock_irqsave(&ha->hardware_lock, flags);
  145. if (is_qla8022(ha)) {
  146. intr_status =
  147. readl(&ha->qla4_8xxx_reg->host_int);
  148. if (intr_status & ISRX_82XX_RISC_INT) {
  149. ha->mbox_status_count = outCount;
  150. intr_status =
  151. readl(&ha->qla4_8xxx_reg->host_status);
  152. ha->isp_ops->interrupt_service_routine(
  153. ha, intr_status);
  154. if (test_bit(AF_INTERRUPTS_ON,
  155. &ha->flags) &&
  156. test_bit(AF_INTx_ENABLED,
  157. &ha->flags))
  158. qla4_8xxx_wr_32(ha,
  159. ha->nx_legacy_intr.tgt_mask_reg,
  160. 0xfbff);
  161. }
  162. } else {
  163. intr_status = readl(&ha->reg->ctrl_status);
  164. if (intr_status & INTR_PENDING) {
  165. /*
  166. * Service the interrupt.
  167. * The ISR will save the mailbox status
  168. * registers to a temporary storage
  169. * location in the adapter structure.
  170. */
  171. ha->mbox_status_count = outCount;
  172. ha->isp_ops->interrupt_service_routine(
  173. ha, intr_status);
  174. }
  175. }
  176. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  177. msleep(10);
  178. }
  179. }
  180. /* Check for mailbox timeout. */
  181. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  182. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  183. " Scheduling Adapter Reset\n", ha->host_no,
  184. mbx_cmd[0]));
  185. ha->mailbox_timeout_count++;
  186. mbx_sts[0] = (-1);
  187. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  188. goto mbox_exit;
  189. }
  190. /*
  191. * Copy the mailbox out registers to the caller's mailbox in/out
  192. * structure.
  193. */
  194. spin_lock_irqsave(&ha->hardware_lock, flags);
  195. for (i = 0; i < outCount; i++)
  196. mbx_sts[i] = ha->mbox_status[i];
  197. /* Set return status and error flags (if applicable). */
  198. switch (ha->mbox_status[0]) {
  199. case MBOX_STS_COMMAND_COMPLETE:
  200. status = QLA_SUCCESS;
  201. break;
  202. case MBOX_STS_INTERMEDIATE_COMPLETION:
  203. status = QLA_SUCCESS;
  204. break;
  205. case MBOX_STS_BUSY:
  206. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  207. ha->host_no, __func__, mbx_cmd[0]));
  208. ha->mailbox_timeout_count++;
  209. break;
  210. default:
  211. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  212. "sts = %08X ****\n", ha->host_no, __func__,
  213. mbx_cmd[0], mbx_sts[0]));
  214. break;
  215. }
  216. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  217. mbox_exit:
  218. mutex_lock(&ha->mbox_sem);
  219. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  220. mutex_unlock(&ha->mbox_sem);
  221. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  222. return status;
  223. }
  224. static uint8_t
  225. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  226. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  227. {
  228. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  229. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  230. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  231. mbox_cmd[1] = 0;
  232. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  233. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  234. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  235. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  236. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  237. QLA_SUCCESS) {
  238. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  239. "MBOX_CMD_INITIALIZE_FIRMWARE"
  240. " failed w/ status %04X\n",
  241. ha->host_no, __func__, mbox_sts[0]));
  242. return QLA_ERROR;
  243. }
  244. return QLA_SUCCESS;
  245. }
  246. static uint8_t
  247. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  248. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  249. {
  250. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  251. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  252. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  253. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  254. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  255. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  256. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  257. QLA_SUCCESS) {
  258. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  259. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  260. " failed w/ status %04X\n",
  261. ha->host_no, __func__, mbox_sts[0]));
  262. return QLA_ERROR;
  263. }
  264. return QLA_SUCCESS;
  265. }
  266. static void
  267. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  268. struct addr_ctrl_blk *init_fw_cb)
  269. {
  270. /* Save IPv4 Address Info */
  271. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  272. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  273. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  274. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  275. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  276. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  277. if (is_ipv6_enabled(ha)) {
  278. /* Save IPv6 Address */
  279. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  280. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  281. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  282. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  283. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  284. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  285. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  286. init_fw_cb->ipv6_if_id,
  287. min(sizeof(ha->ipv6_link_local_addr)/2,
  288. sizeof(init_fw_cb->ipv6_if_id)));
  289. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  290. min(sizeof(ha->ipv6_addr0),
  291. sizeof(init_fw_cb->ipv6_addr0)));
  292. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  293. min(sizeof(ha->ipv6_addr1),
  294. sizeof(init_fw_cb->ipv6_addr1)));
  295. memcpy(&ha->ipv6_default_router_addr,
  296. init_fw_cb->ipv6_dflt_rtr_addr,
  297. min(sizeof(ha->ipv6_default_router_addr),
  298. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  299. }
  300. }
  301. static uint8_t
  302. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  303. uint32_t *mbox_cmd,
  304. uint32_t *mbox_sts,
  305. struct addr_ctrl_blk *init_fw_cb,
  306. dma_addr_t init_fw_cb_dma)
  307. {
  308. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  309. != QLA_SUCCESS) {
  310. DEBUG2(printk(KERN_WARNING
  311. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  312. ha->host_no, __func__));
  313. return QLA_ERROR;
  314. }
  315. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  316. /* Save some info in adapter structure. */
  317. ha->acb_version = init_fw_cb->acb_version;
  318. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  319. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  320. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  321. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  322. ha->heartbeat_interval = init_fw_cb->hb_interval;
  323. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  324. min(sizeof(ha->name_string),
  325. sizeof(init_fw_cb->iscsi_name)));
  326. /*memcpy(ha->alias, init_fw_cb->Alias,
  327. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  328. /* Save Command Line Paramater info */
  329. ha->port_down_retry_count = le16_to_cpu(init_fw_cb->conn_ka_timeout);
  330. ha->discovery_wait = ql4xdiscoverywait;
  331. if (ha->acb_version == ACB_SUPPORTED) {
  332. ha->ipv6_options = init_fw_cb->ipv6_opts;
  333. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  334. }
  335. qla4xxx_update_local_ip(ha, init_fw_cb);
  336. return QLA_SUCCESS;
  337. }
  338. /**
  339. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  340. * @ha: Pointer to host adapter structure.
  341. **/
  342. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  343. {
  344. struct addr_ctrl_blk *init_fw_cb;
  345. dma_addr_t init_fw_cb_dma;
  346. uint32_t mbox_cmd[MBOX_REG_COUNT];
  347. uint32_t mbox_sts[MBOX_REG_COUNT];
  348. int status = QLA_ERROR;
  349. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  350. sizeof(struct addr_ctrl_blk),
  351. &init_fw_cb_dma, GFP_KERNEL);
  352. if (init_fw_cb == NULL) {
  353. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  354. ha->host_no, __func__));
  355. goto exit_init_fw_cb_no_free;
  356. }
  357. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  358. /* Get Initialize Firmware Control Block. */
  359. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  360. memset(&mbox_sts, 0, sizeof(mbox_sts));
  361. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  362. QLA_SUCCESS) {
  363. dma_free_coherent(&ha->pdev->dev,
  364. sizeof(struct addr_ctrl_blk),
  365. init_fw_cb, init_fw_cb_dma);
  366. goto exit_init_fw_cb;
  367. }
  368. /* Initialize request and response queues. */
  369. qla4xxx_init_rings(ha);
  370. /* Fill in the request and response queue information. */
  371. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  372. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  373. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  374. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  375. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  376. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  377. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  378. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  379. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  380. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  381. /* Set up required options. */
  382. init_fw_cb->fw_options |=
  383. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  384. FWOPT_INITIATOR_MODE);
  385. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  386. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  387. != QLA_SUCCESS) {
  388. DEBUG2(printk(KERN_WARNING
  389. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  390. ha->host_no, __func__));
  391. goto exit_init_fw_cb;
  392. }
  393. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  394. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  395. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  396. ha->host_no, __func__));
  397. goto exit_init_fw_cb;
  398. }
  399. status = QLA_SUCCESS;
  400. exit_init_fw_cb:
  401. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  402. init_fw_cb, init_fw_cb_dma);
  403. exit_init_fw_cb_no_free:
  404. return status;
  405. }
  406. /**
  407. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  408. * @ha: Pointer to host adapter structure.
  409. **/
  410. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  411. {
  412. struct addr_ctrl_blk *init_fw_cb;
  413. dma_addr_t init_fw_cb_dma;
  414. uint32_t mbox_cmd[MBOX_REG_COUNT];
  415. uint32_t mbox_sts[MBOX_REG_COUNT];
  416. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  417. sizeof(struct addr_ctrl_blk),
  418. &init_fw_cb_dma, GFP_KERNEL);
  419. if (init_fw_cb == NULL) {
  420. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  421. __func__);
  422. return QLA_ERROR;
  423. }
  424. /* Get Initialize Firmware Control Block. */
  425. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  426. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  427. QLA_SUCCESS) {
  428. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  429. ha->host_no, __func__));
  430. dma_free_coherent(&ha->pdev->dev,
  431. sizeof(struct addr_ctrl_blk),
  432. init_fw_cb, init_fw_cb_dma);
  433. return QLA_ERROR;
  434. }
  435. /* Save IP Address. */
  436. qla4xxx_update_local_ip(ha, init_fw_cb);
  437. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  438. init_fw_cb, init_fw_cb_dma);
  439. return QLA_SUCCESS;
  440. }
  441. /**
  442. * qla4xxx_get_firmware_state - gets firmware state of HBA
  443. * @ha: Pointer to host adapter structure.
  444. **/
  445. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  446. {
  447. uint32_t mbox_cmd[MBOX_REG_COUNT];
  448. uint32_t mbox_sts[MBOX_REG_COUNT];
  449. /* Get firmware version */
  450. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  451. memset(&mbox_sts, 0, sizeof(mbox_sts));
  452. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  453. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  454. QLA_SUCCESS) {
  455. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  456. "status %04X\n", ha->host_no, __func__,
  457. mbox_sts[0]));
  458. return QLA_ERROR;
  459. }
  460. ha->firmware_state = mbox_sts[1];
  461. ha->board_id = mbox_sts[2];
  462. ha->addl_fw_state = mbox_sts[3];
  463. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  464. ha->host_no, __func__, ha->firmware_state);)
  465. return QLA_SUCCESS;
  466. }
  467. /**
  468. * qla4xxx_get_firmware_status - retrieves firmware status
  469. * @ha: Pointer to host adapter structure.
  470. **/
  471. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  472. {
  473. uint32_t mbox_cmd[MBOX_REG_COUNT];
  474. uint32_t mbox_sts[MBOX_REG_COUNT];
  475. /* Get firmware version */
  476. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  477. memset(&mbox_sts, 0, sizeof(mbox_sts));
  478. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  479. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  480. QLA_SUCCESS) {
  481. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  482. "status %04X\n", ha->host_no, __func__,
  483. mbox_sts[0]));
  484. return QLA_ERROR;
  485. }
  486. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  487. ha->host_no, mbox_cmd[2]);
  488. return QLA_SUCCESS;
  489. }
  490. /**
  491. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  492. * @ha: Pointer to host adapter structure.
  493. * @fw_ddb_index: Firmware's device database index
  494. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  495. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  496. * @next_ddb_index: Pointer to next valid device database index
  497. * @fw_ddb_device_state: Pointer to device state
  498. **/
  499. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  500. uint16_t fw_ddb_index,
  501. struct dev_db_entry *fw_ddb_entry,
  502. dma_addr_t fw_ddb_entry_dma,
  503. uint32_t *num_valid_ddb_entries,
  504. uint32_t *next_ddb_index,
  505. uint32_t *fw_ddb_device_state,
  506. uint32_t *conn_err_detail,
  507. uint16_t *tcp_source_port_num,
  508. uint16_t *connection_id)
  509. {
  510. int status = QLA_ERROR;
  511. uint16_t options;
  512. uint32_t mbox_cmd[MBOX_REG_COUNT];
  513. uint32_t mbox_sts[MBOX_REG_COUNT];
  514. /* Make sure the device index is valid */
  515. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  516. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  517. ha->host_no, __func__, fw_ddb_index));
  518. goto exit_get_fwddb;
  519. }
  520. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  521. memset(&mbox_sts, 0, sizeof(mbox_sts));
  522. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  523. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  524. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  525. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  526. mbox_cmd[4] = sizeof(struct dev_db_entry);
  527. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  528. QLA_ERROR) {
  529. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  530. " with status 0x%04X\n", ha->host_no, __func__,
  531. mbox_sts[0]));
  532. goto exit_get_fwddb;
  533. }
  534. if (fw_ddb_index != mbox_sts[1]) {
  535. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  536. ha->host_no, __func__, fw_ddb_index,
  537. mbox_sts[1]));
  538. goto exit_get_fwddb;
  539. }
  540. if (fw_ddb_entry) {
  541. options = le16_to_cpu(fw_ddb_entry->options);
  542. if (options & DDB_OPT_IPV6_DEVICE) {
  543. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  544. "Next %d State %04x ConnErr %08x %pI6 "
  545. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  546. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  547. mbox_sts[4], mbox_sts[5],
  548. fw_ddb_entry->ip_addr,
  549. le16_to_cpu(fw_ddb_entry->port),
  550. fw_ddb_entry->iscsi_name);
  551. } else {
  552. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  553. "Next %d State %04x ConnErr %08x %pI4 "
  554. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  555. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  556. mbox_sts[4], mbox_sts[5],
  557. fw_ddb_entry->ip_addr,
  558. le16_to_cpu(fw_ddb_entry->port),
  559. fw_ddb_entry->iscsi_name);
  560. }
  561. }
  562. if (num_valid_ddb_entries)
  563. *num_valid_ddb_entries = mbox_sts[2];
  564. if (next_ddb_index)
  565. *next_ddb_index = mbox_sts[3];
  566. if (fw_ddb_device_state)
  567. *fw_ddb_device_state = mbox_sts[4];
  568. /*
  569. * RA: This mailbox has been changed to pass connection error and
  570. * details. Its true for ISP4010 as per Version E - Not sure when it
  571. * was changed. Get the time2wait from the fw_dd_entry field :
  572. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  573. * struct.
  574. */
  575. if (conn_err_detail)
  576. *conn_err_detail = mbox_sts[5];
  577. if (tcp_source_port_num)
  578. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  579. if (connection_id)
  580. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  581. status = QLA_SUCCESS;
  582. exit_get_fwddb:
  583. return status;
  584. }
  585. /**
  586. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  587. * @ha: Pointer to host adapter structure.
  588. * @fw_ddb_index: Firmware's device database index
  589. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  590. *
  591. * This routine initializes or updates the adapter's device database
  592. * entry for the specified device. It also triggers a login for the
  593. * specified device. Therefore, it may also be used as a secondary
  594. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  595. **/
  596. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  597. dma_addr_t fw_ddb_entry_dma)
  598. {
  599. uint32_t mbox_cmd[MBOX_REG_COUNT];
  600. uint32_t mbox_sts[MBOX_REG_COUNT];
  601. int status;
  602. /* Do not wait for completion. The firmware will send us an
  603. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  604. */
  605. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  606. memset(&mbox_sts, 0, sizeof(mbox_sts));
  607. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  608. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  609. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  610. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  611. mbox_cmd[4] = sizeof(struct dev_db_entry);
  612. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  613. &mbox_sts[0]);
  614. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  615. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  616. return status;
  617. }
  618. /**
  619. * qla4xxx_get_crash_record - retrieves crash record.
  620. * @ha: Pointer to host adapter structure.
  621. *
  622. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  623. **/
  624. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  625. {
  626. uint32_t mbox_cmd[MBOX_REG_COUNT];
  627. uint32_t mbox_sts[MBOX_REG_COUNT];
  628. struct crash_record *crash_record = NULL;
  629. dma_addr_t crash_record_dma = 0;
  630. uint32_t crash_record_size = 0;
  631. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  632. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  633. /* Get size of crash record. */
  634. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  635. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  636. QLA_SUCCESS) {
  637. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  638. ha->host_no, __func__));
  639. goto exit_get_crash_record;
  640. }
  641. crash_record_size = mbox_sts[4];
  642. if (crash_record_size == 0) {
  643. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  644. ha->host_no, __func__));
  645. goto exit_get_crash_record;
  646. }
  647. /* Alloc Memory for Crash Record. */
  648. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  649. &crash_record_dma, GFP_KERNEL);
  650. if (crash_record == NULL)
  651. goto exit_get_crash_record;
  652. /* Get Crash Record. */
  653. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  654. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  655. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  656. mbox_cmd[2] = LSDW(crash_record_dma);
  657. mbox_cmd[3] = MSDW(crash_record_dma);
  658. mbox_cmd[4] = crash_record_size;
  659. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  660. QLA_SUCCESS)
  661. goto exit_get_crash_record;
  662. /* Dump Crash Record. */
  663. exit_get_crash_record:
  664. if (crash_record)
  665. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  666. crash_record, crash_record_dma);
  667. }
  668. /**
  669. * qla4xxx_get_conn_event_log - retrieves connection event log
  670. * @ha: Pointer to host adapter structure.
  671. **/
  672. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  673. {
  674. uint32_t mbox_cmd[MBOX_REG_COUNT];
  675. uint32_t mbox_sts[MBOX_REG_COUNT];
  676. struct conn_event_log_entry *event_log = NULL;
  677. dma_addr_t event_log_dma = 0;
  678. uint32_t event_log_size = 0;
  679. uint32_t num_valid_entries;
  680. uint32_t oldest_entry = 0;
  681. uint32_t max_event_log_entries;
  682. uint8_t i;
  683. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  684. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  685. /* Get size of crash record. */
  686. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  687. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  688. QLA_SUCCESS)
  689. goto exit_get_event_log;
  690. event_log_size = mbox_sts[4];
  691. if (event_log_size == 0)
  692. goto exit_get_event_log;
  693. /* Alloc Memory for Crash Record. */
  694. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  695. &event_log_dma, GFP_KERNEL);
  696. if (event_log == NULL)
  697. goto exit_get_event_log;
  698. /* Get Crash Record. */
  699. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  700. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  701. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  702. mbox_cmd[2] = LSDW(event_log_dma);
  703. mbox_cmd[3] = MSDW(event_log_dma);
  704. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  705. QLA_SUCCESS) {
  706. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  707. "log!\n", ha->host_no, __func__));
  708. goto exit_get_event_log;
  709. }
  710. /* Dump Event Log. */
  711. num_valid_entries = mbox_sts[1];
  712. max_event_log_entries = event_log_size /
  713. sizeof(struct conn_event_log_entry);
  714. if (num_valid_entries > max_event_log_entries)
  715. oldest_entry = num_valid_entries % max_event_log_entries;
  716. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  717. ha->host_no, num_valid_entries));
  718. if (ql4xextended_error_logging == 3) {
  719. if (oldest_entry == 0) {
  720. /* Circular Buffer has not wrapped around */
  721. for (i=0; i < num_valid_entries; i++) {
  722. qla4xxx_dump_buffer((uint8_t *)event_log+
  723. (i*sizeof(*event_log)),
  724. sizeof(*event_log));
  725. }
  726. }
  727. else {
  728. /* Circular Buffer has wrapped around -
  729. * display accordingly*/
  730. for (i=oldest_entry; i < max_event_log_entries; i++) {
  731. qla4xxx_dump_buffer((uint8_t *)event_log+
  732. (i*sizeof(*event_log)),
  733. sizeof(*event_log));
  734. }
  735. for (i=0; i < oldest_entry; i++) {
  736. qla4xxx_dump_buffer((uint8_t *)event_log+
  737. (i*sizeof(*event_log)),
  738. sizeof(*event_log));
  739. }
  740. }
  741. }
  742. exit_get_event_log:
  743. if (event_log)
  744. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  745. event_log_dma);
  746. }
  747. /**
  748. * qla4xxx_abort_task - issues Abort Task
  749. * @ha: Pointer to host adapter structure.
  750. * @srb: Pointer to srb entry
  751. *
  752. * This routine performs a LUN RESET on the specified target/lun.
  753. * The caller must ensure that the ddb_entry and lun_entry pointers
  754. * are valid before calling this routine.
  755. **/
  756. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  757. {
  758. uint32_t mbox_cmd[MBOX_REG_COUNT];
  759. uint32_t mbox_sts[MBOX_REG_COUNT];
  760. struct scsi_cmnd *cmd = srb->cmd;
  761. int status = QLA_SUCCESS;
  762. unsigned long flags = 0;
  763. uint32_t index;
  764. /*
  765. * Send abort task command to ISP, so that the ISP will return
  766. * request with ABORT status
  767. */
  768. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  769. memset(&mbox_sts, 0, sizeof(mbox_sts));
  770. spin_lock_irqsave(&ha->hardware_lock, flags);
  771. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  772. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  773. /* Firmware already posted completion on response queue */
  774. if (index == MAX_SRBS)
  775. return status;
  776. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  777. mbox_cmd[1] = srb->fw_ddb_index;
  778. mbox_cmd[2] = index;
  779. /* Immediate Command Enable */
  780. mbox_cmd[5] = 0x01;
  781. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  782. &mbox_sts[0]);
  783. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  784. status = QLA_ERROR;
  785. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  786. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  787. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  788. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  789. }
  790. return status;
  791. }
  792. /**
  793. * qla4xxx_reset_lun - issues LUN Reset
  794. * @ha: Pointer to host adapter structure.
  795. * @ddb_entry: Pointer to device database entry
  796. * @lun: lun number
  797. *
  798. * This routine performs a LUN RESET on the specified target/lun.
  799. * The caller must ensure that the ddb_entry and lun_entry pointers
  800. * are valid before calling this routine.
  801. **/
  802. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  803. int lun)
  804. {
  805. uint32_t mbox_cmd[MBOX_REG_COUNT];
  806. uint32_t mbox_sts[MBOX_REG_COUNT];
  807. int status = QLA_SUCCESS;
  808. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  809. ddb_entry->fw_ddb_index, lun));
  810. /*
  811. * Send lun reset command to ISP, so that the ISP will return all
  812. * outstanding requests with RESET status
  813. */
  814. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  815. memset(&mbox_sts, 0, sizeof(mbox_sts));
  816. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  817. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  818. mbox_cmd[2] = lun << 8;
  819. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  820. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  821. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  822. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  823. status = QLA_ERROR;
  824. return status;
  825. }
  826. /**
  827. * qla4xxx_reset_target - issues target Reset
  828. * @ha: Pointer to host adapter structure.
  829. * @db_entry: Pointer to device database entry
  830. * @un_entry: Pointer to lun entry structure
  831. *
  832. * This routine performs a TARGET RESET on the specified target.
  833. * The caller must ensure that the ddb_entry pointers
  834. * are valid before calling this routine.
  835. **/
  836. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  837. struct ddb_entry *ddb_entry)
  838. {
  839. uint32_t mbox_cmd[MBOX_REG_COUNT];
  840. uint32_t mbox_sts[MBOX_REG_COUNT];
  841. int status = QLA_SUCCESS;
  842. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  843. ddb_entry->fw_ddb_index));
  844. /*
  845. * Send target reset command to ISP, so that the ISP will return all
  846. * outstanding requests with RESET status
  847. */
  848. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  849. memset(&mbox_sts, 0, sizeof(mbox_sts));
  850. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  851. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  852. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  853. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  854. &mbox_sts[0]);
  855. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  856. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  857. status = QLA_ERROR;
  858. return status;
  859. }
  860. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  861. uint32_t offset, uint32_t len)
  862. {
  863. uint32_t mbox_cmd[MBOX_REG_COUNT];
  864. uint32_t mbox_sts[MBOX_REG_COUNT];
  865. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  866. memset(&mbox_sts, 0, sizeof(mbox_sts));
  867. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  868. mbox_cmd[1] = LSDW(dma_addr);
  869. mbox_cmd[2] = MSDW(dma_addr);
  870. mbox_cmd[3] = offset;
  871. mbox_cmd[4] = len;
  872. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  873. QLA_SUCCESS) {
  874. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  875. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  876. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  877. return QLA_ERROR;
  878. }
  879. return QLA_SUCCESS;
  880. }
  881. /**
  882. * qla4xxx_get_fw_version - gets firmware version
  883. * @ha: Pointer to host adapter structure.
  884. *
  885. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  886. * hold an address for data. Make sure that we write 0 to those mailboxes,
  887. * if unused.
  888. **/
  889. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  890. {
  891. uint32_t mbox_cmd[MBOX_REG_COUNT];
  892. uint32_t mbox_sts[MBOX_REG_COUNT];
  893. /* Get firmware version. */
  894. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  895. memset(&mbox_sts, 0, sizeof(mbox_sts));
  896. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  897. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  898. QLA_SUCCESS) {
  899. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  900. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  901. return QLA_ERROR;
  902. }
  903. /* Save firmware version information. */
  904. ha->firmware_version[0] = mbox_sts[1];
  905. ha->firmware_version[1] = mbox_sts[2];
  906. ha->patch_number = mbox_sts[3];
  907. ha->build_number = mbox_sts[4];
  908. return QLA_SUCCESS;
  909. }
  910. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  911. dma_addr_t dma_addr)
  912. {
  913. uint32_t mbox_cmd[MBOX_REG_COUNT];
  914. uint32_t mbox_sts[MBOX_REG_COUNT];
  915. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  916. memset(&mbox_sts, 0, sizeof(mbox_sts));
  917. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  918. mbox_cmd[2] = LSDW(dma_addr);
  919. mbox_cmd[3] = MSDW(dma_addr);
  920. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  921. QLA_SUCCESS) {
  922. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  923. ha->host_no, __func__, mbox_sts[0]));
  924. return QLA_ERROR;
  925. }
  926. return QLA_SUCCESS;
  927. }
  928. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  929. {
  930. uint32_t mbox_cmd[MBOX_REG_COUNT];
  931. uint32_t mbox_sts[MBOX_REG_COUNT];
  932. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  933. memset(&mbox_sts, 0, sizeof(mbox_sts));
  934. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  935. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  936. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  937. QLA_SUCCESS) {
  938. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  939. *ddb_index = mbox_sts[2];
  940. } else {
  941. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  942. ha->host_no, __func__, mbox_sts[0]));
  943. return QLA_ERROR;
  944. }
  945. } else {
  946. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  947. }
  948. return QLA_SUCCESS;
  949. }
  950. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  951. {
  952. struct dev_db_entry *fw_ddb_entry;
  953. dma_addr_t fw_ddb_entry_dma;
  954. uint32_t ddb_index;
  955. int ret_val = QLA_SUCCESS;
  956. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  957. sizeof(*fw_ddb_entry),
  958. &fw_ddb_entry_dma, GFP_KERNEL);
  959. if (!fw_ddb_entry) {
  960. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  961. ha->host_no, __func__));
  962. ret_val = QLA_ERROR;
  963. goto exit_send_tgts_no_free;
  964. }
  965. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  966. if (ret_val != QLA_SUCCESS)
  967. goto exit_send_tgts;
  968. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  969. if (ret_val != QLA_SUCCESS)
  970. goto exit_send_tgts;
  971. memset(fw_ddb_entry->iscsi_alias, 0,
  972. sizeof(fw_ddb_entry->iscsi_alias));
  973. memset(fw_ddb_entry->iscsi_name, 0,
  974. sizeof(fw_ddb_entry->iscsi_name));
  975. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  976. memset(fw_ddb_entry->tgt_addr, 0,
  977. sizeof(fw_ddb_entry->tgt_addr));
  978. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  979. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  980. fw_ddb_entry->ip_addr[0] = *ip;
  981. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  982. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  983. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  984. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  985. exit_send_tgts:
  986. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  987. fw_ddb_entry, fw_ddb_entry_dma);
  988. exit_send_tgts_no_free:
  989. return ret_val;
  990. }