mx2_camera.c 38 KB

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  1. /*
  2. * V4L2 Driver for i.MX27/i.MX25 camera host
  3. *
  4. * Copyright (C) 2008, Sascha Hauer, Pengutronix
  5. * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/io.h>
  15. #include <linux/delay.h>
  16. #include <linux/slab.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/errno.h>
  19. #include <linux/fs.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/kernel.h>
  22. #include <linux/mm.h>
  23. #include <linux/moduleparam.h>
  24. #include <linux/time.h>
  25. #include <linux/version.h>
  26. #include <linux/device.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/mutex.h>
  29. #include <linux/clk.h>
  30. #include <media/v4l2-common.h>
  31. #include <media/v4l2-dev.h>
  32. #include <media/videobuf-dma-contig.h>
  33. #include <media/soc_camera.h>
  34. #include <media/soc_mediabus.h>
  35. #include <linux/videodev2.h>
  36. #include <mach/mx2_cam.h>
  37. #ifdef CONFIG_MACH_MX27
  38. #include <mach/dma-mx1-mx2.h>
  39. #endif
  40. #include <mach/hardware.h>
  41. #include <asm/dma.h>
  42. #define MX2_CAM_DRV_NAME "mx2-camera"
  43. #define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
  44. #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
  45. /* reset values */
  46. #define CSICR1_RESET_VAL 0x40000800
  47. #define CSICR2_RESET_VAL 0x0
  48. #define CSICR3_RESET_VAL 0x0
  49. /* csi control reg 1 */
  50. #define CSICR1_SWAP16_EN (1 << 31)
  51. #define CSICR1_EXT_VSYNC (1 << 30)
  52. #define CSICR1_EOF_INTEN (1 << 29)
  53. #define CSICR1_PRP_IF_EN (1 << 28)
  54. #define CSICR1_CCIR_MODE (1 << 27)
  55. #define CSICR1_COF_INTEN (1 << 26)
  56. #define CSICR1_SF_OR_INTEN (1 << 25)
  57. #define CSICR1_RF_OR_INTEN (1 << 24)
  58. #define CSICR1_STATFF_LEVEL (3 << 22)
  59. #define CSICR1_STATFF_INTEN (1 << 21)
  60. #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
  61. #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
  62. #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
  63. #define CSICR1_RXFF_INTEN (1 << 18)
  64. #define CSICR1_SOF_POL (1 << 17)
  65. #define CSICR1_SOF_INTEN (1 << 16)
  66. #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
  67. #define CSICR1_HSYNC_POL (1 << 11)
  68. #define CSICR1_CCIR_EN (1 << 10)
  69. #define CSICR1_MCLKEN (1 << 9)
  70. #define CSICR1_FCC (1 << 8)
  71. #define CSICR1_PACK_DIR (1 << 7)
  72. #define CSICR1_CLR_STATFIFO (1 << 6)
  73. #define CSICR1_CLR_RXFIFO (1 << 5)
  74. #define CSICR1_GCLK_MODE (1 << 4)
  75. #define CSICR1_INV_DATA (1 << 3)
  76. #define CSICR1_INV_PCLK (1 << 2)
  77. #define CSICR1_REDGE (1 << 1)
  78. #define SHIFT_STATFF_LEVEL 22
  79. #define SHIFT_RXFF_LEVEL 19
  80. #define SHIFT_MCLKDIV 12
  81. /* control reg 3 */
  82. #define CSICR3_FRMCNT (0xFFFF << 16)
  83. #define CSICR3_FRMCNT_RST (1 << 15)
  84. #define CSICR3_DMA_REFLASH_RFF (1 << 14)
  85. #define CSICR3_DMA_REFLASH_SFF (1 << 13)
  86. #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
  87. #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
  88. #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
  89. #define CSICR3_CSI_SUP (1 << 3)
  90. #define CSICR3_ZERO_PACK_EN (1 << 2)
  91. #define CSICR3_ECC_INT_EN (1 << 1)
  92. #define CSICR3_ECC_AUTO_EN (1 << 0)
  93. #define SHIFT_FRMCNT 16
  94. /* csi status reg */
  95. #define CSISR_SFF_OR_INT (1 << 25)
  96. #define CSISR_RFF_OR_INT (1 << 24)
  97. #define CSISR_STATFF_INT (1 << 21)
  98. #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
  99. #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
  100. #define CSISR_RXFF_INT (1 << 18)
  101. #define CSISR_EOF_INT (1 << 17)
  102. #define CSISR_SOF_INT (1 << 16)
  103. #define CSISR_F2_INT (1 << 15)
  104. #define CSISR_F1_INT (1 << 14)
  105. #define CSISR_COF_INT (1 << 13)
  106. #define CSISR_ECC_INT (1 << 1)
  107. #define CSISR_DRDY (1 << 0)
  108. #define CSICR1 0x00
  109. #define CSICR2 0x04
  110. #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
  111. #define CSISTATFIFO 0x0c
  112. #define CSIRFIFO 0x10
  113. #define CSIRXCNT 0x14
  114. #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
  115. #define CSIDMASA_STATFIFO 0x20
  116. #define CSIDMATA_STATFIFO 0x24
  117. #define CSIDMASA_FB1 0x28
  118. #define CSIDMASA_FB2 0x2c
  119. #define CSIFBUF_PARA 0x30
  120. #define CSIIMAG_PARA 0x34
  121. /* EMMA PrP */
  122. #define PRP_CNTL 0x00
  123. #define PRP_INTR_CNTL 0x04
  124. #define PRP_INTRSTATUS 0x08
  125. #define PRP_SOURCE_Y_PTR 0x0c
  126. #define PRP_SOURCE_CB_PTR 0x10
  127. #define PRP_SOURCE_CR_PTR 0x14
  128. #define PRP_DEST_RGB1_PTR 0x18
  129. #define PRP_DEST_RGB2_PTR 0x1c
  130. #define PRP_DEST_Y_PTR 0x20
  131. #define PRP_DEST_CB_PTR 0x24
  132. #define PRP_DEST_CR_PTR 0x28
  133. #define PRP_SRC_FRAME_SIZE 0x2c
  134. #define PRP_DEST_CH1_LINE_STRIDE 0x30
  135. #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
  136. #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
  137. #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
  138. #define PRP_CH2_OUT_IMAGE_SIZE 0x40
  139. #define PRP_SRC_LINE_STRIDE 0x44
  140. #define PRP_CSC_COEF_012 0x48
  141. #define PRP_CSC_COEF_345 0x4c
  142. #define PRP_CSC_COEF_678 0x50
  143. #define PRP_CH1_RZ_HORI_COEF1 0x54
  144. #define PRP_CH1_RZ_HORI_COEF2 0x58
  145. #define PRP_CH1_RZ_HORI_VALID 0x5c
  146. #define PRP_CH1_RZ_VERT_COEF1 0x60
  147. #define PRP_CH1_RZ_VERT_COEF2 0x64
  148. #define PRP_CH1_RZ_VERT_VALID 0x68
  149. #define PRP_CH2_RZ_HORI_COEF1 0x6c
  150. #define PRP_CH2_RZ_HORI_COEF2 0x70
  151. #define PRP_CH2_RZ_HORI_VALID 0x74
  152. #define PRP_CH2_RZ_VERT_COEF1 0x78
  153. #define PRP_CH2_RZ_VERT_COEF2 0x7c
  154. #define PRP_CH2_RZ_VERT_VALID 0x80
  155. #define PRP_CNTL_CH1EN (1 << 0)
  156. #define PRP_CNTL_CH2EN (1 << 1)
  157. #define PRP_CNTL_CSIEN (1 << 2)
  158. #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
  159. #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
  160. #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
  161. #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
  162. #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
  163. #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
  164. #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
  165. #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
  166. #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
  167. #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
  168. #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
  169. #define PRP_CNTL_CH1_LEN (1 << 9)
  170. #define PRP_CNTL_CH2_LEN (1 << 10)
  171. #define PRP_CNTL_SKIP_FRAME (1 << 11)
  172. #define PRP_CNTL_SWRST (1 << 12)
  173. #define PRP_CNTL_CLKEN (1 << 13)
  174. #define PRP_CNTL_WEN (1 << 14)
  175. #define PRP_CNTL_CH1BYP (1 << 15)
  176. #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
  177. #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
  178. #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
  179. #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
  180. #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
  181. #define PRP_CNTL_CH2B1EN (1 << 29)
  182. #define PRP_CNTL_CH2B2EN (1 << 30)
  183. #define PRP_CNTL_CH2FEN (1 << 31)
  184. /* IRQ Enable and status register */
  185. #define PRP_INTR_RDERR (1 << 0)
  186. #define PRP_INTR_CH1WERR (1 << 1)
  187. #define PRP_INTR_CH2WERR (1 << 2)
  188. #define PRP_INTR_CH1FC (1 << 3)
  189. #define PRP_INTR_CH2FC (1 << 5)
  190. #define PRP_INTR_LBOVF (1 << 7)
  191. #define PRP_INTR_CH2OVF (1 << 8)
  192. #define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma)
  193. #define MAX_VIDEO_MEM 16
  194. struct mx2_camera_dev {
  195. struct device *dev;
  196. struct soc_camera_host soc_host;
  197. struct soc_camera_device *icd;
  198. struct clk *clk_csi, *clk_emma;
  199. unsigned int irq_csi, irq_emma;
  200. void __iomem *base_csi, *base_emma;
  201. unsigned long base_dma;
  202. struct mx2_camera_platform_data *pdata;
  203. struct resource *res_csi, *res_emma;
  204. unsigned long platform_flags;
  205. struct list_head capture;
  206. struct list_head active_bufs;
  207. spinlock_t lock;
  208. int dma;
  209. struct mx2_buffer *active;
  210. struct mx2_buffer *fb1_active;
  211. struct mx2_buffer *fb2_active;
  212. int use_emma;
  213. u32 csicr1;
  214. void *discard_buffer;
  215. dma_addr_t discard_buffer_dma;
  216. size_t discard_size;
  217. };
  218. /* buffer for one video frame */
  219. struct mx2_buffer {
  220. /* common v4l buffer stuff -- must be first */
  221. struct videobuf_buffer vb;
  222. enum v4l2_mbus_pixelcode code;
  223. int bufnum;
  224. };
  225. static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
  226. {
  227. unsigned long flags;
  228. clk_disable(pcdev->clk_csi);
  229. writel(0, pcdev->base_csi + CSICR1);
  230. if (mx27_camera_emma(pcdev)) {
  231. writel(0, pcdev->base_emma + PRP_CNTL);
  232. } else if (cpu_is_mx25()) {
  233. spin_lock_irqsave(&pcdev->lock, flags);
  234. pcdev->fb1_active = NULL;
  235. pcdev->fb2_active = NULL;
  236. writel(0, pcdev->base_csi + CSIDMASA_FB1);
  237. writel(0, pcdev->base_csi + CSIDMASA_FB2);
  238. spin_unlock_irqrestore(&pcdev->lock, flags);
  239. }
  240. }
  241. /*
  242. * The following two functions absolutely depend on the fact, that
  243. * there can be only one camera on mx2 camera sensor interface
  244. */
  245. static int mx2_camera_add_device(struct soc_camera_device *icd)
  246. {
  247. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  248. struct mx2_camera_dev *pcdev = ici->priv;
  249. int ret;
  250. u32 csicr1;
  251. if (pcdev->icd)
  252. return -EBUSY;
  253. ret = clk_enable(pcdev->clk_csi);
  254. if (ret < 0)
  255. return ret;
  256. csicr1 = CSICR1_MCLKEN;
  257. if (mx27_camera_emma(pcdev)) {
  258. csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
  259. CSICR1_RXFF_LEVEL(0);
  260. } else if (cpu_is_mx27())
  261. csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
  262. pcdev->csicr1 = csicr1;
  263. writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
  264. pcdev->icd = icd;
  265. dev_info(icd->dev.parent, "Camera driver attached to camera %d\n",
  266. icd->devnum);
  267. return 0;
  268. }
  269. static void mx2_camera_remove_device(struct soc_camera_device *icd)
  270. {
  271. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  272. struct mx2_camera_dev *pcdev = ici->priv;
  273. BUG_ON(icd != pcdev->icd);
  274. dev_info(icd->dev.parent, "Camera driver detached from camera %d\n",
  275. icd->devnum);
  276. mx2_camera_deactivate(pcdev);
  277. if (pcdev->discard_buffer) {
  278. dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
  279. pcdev->discard_buffer,
  280. pcdev->discard_buffer_dma);
  281. pcdev->discard_buffer = NULL;
  282. }
  283. pcdev->icd = NULL;
  284. }
  285. #ifdef CONFIG_MACH_MX27
  286. static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
  287. {
  288. u32 tmp;
  289. imx_dma_enable(pcdev->dma);
  290. tmp = readl(pcdev->base_csi + CSICR1);
  291. tmp |= CSICR1_RF_OR_INTEN;
  292. writel(tmp, pcdev->base_csi + CSICR1);
  293. }
  294. static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
  295. {
  296. struct mx2_camera_dev *pcdev = data;
  297. u32 status = readl(pcdev->base_csi + CSISR);
  298. if (status & CSISR_SOF_INT && pcdev->active) {
  299. u32 tmp;
  300. tmp = readl(pcdev->base_csi + CSICR1);
  301. writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
  302. mx27_camera_dma_enable(pcdev);
  303. }
  304. writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
  305. return IRQ_HANDLED;
  306. }
  307. #else
  308. static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
  309. {
  310. return IRQ_NONE;
  311. }
  312. #endif /* CONFIG_MACH_MX27 */
  313. static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
  314. int state)
  315. {
  316. struct videobuf_buffer *vb;
  317. struct mx2_buffer *buf;
  318. struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
  319. &pcdev->fb2_active;
  320. u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
  321. unsigned long flags;
  322. spin_lock_irqsave(&pcdev->lock, flags);
  323. vb = &(*fb_active)->vb;
  324. dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  325. vb, vb->baddr, vb->bsize);
  326. vb->state = state;
  327. do_gettimeofday(&vb->ts);
  328. vb->field_count++;
  329. wake_up(&vb->done);
  330. if (list_empty(&pcdev->capture)) {
  331. buf = NULL;
  332. writel(0, pcdev->base_csi + fb_reg);
  333. } else {
  334. buf = list_entry(pcdev->capture.next, struct mx2_buffer,
  335. vb.queue);
  336. vb = &buf->vb;
  337. list_del(&vb->queue);
  338. vb->state = VIDEOBUF_ACTIVE;
  339. writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
  340. }
  341. *fb_active = buf;
  342. spin_unlock_irqrestore(&pcdev->lock, flags);
  343. }
  344. static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
  345. {
  346. struct mx2_camera_dev *pcdev = data;
  347. u32 status = readl(pcdev->base_csi + CSISR);
  348. if (status & CSISR_DMA_TSF_FB1_INT)
  349. mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
  350. else if (status & CSISR_DMA_TSF_FB2_INT)
  351. mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
  352. /* FIXME: handle CSISR_RFF_OR_INT */
  353. writel(status, pcdev->base_csi + CSISR);
  354. return IRQ_HANDLED;
  355. }
  356. /*
  357. * Videobuf operations
  358. */
  359. static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
  360. unsigned int *size)
  361. {
  362. struct soc_camera_device *icd = vq->priv_data;
  363. int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
  364. icd->current_fmt->host_fmt);
  365. dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
  366. if (bytes_per_line < 0)
  367. return bytes_per_line;
  368. *size = bytes_per_line * icd->user_height;
  369. if (0 == *count)
  370. *count = 32;
  371. if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
  372. *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
  373. return 0;
  374. }
  375. static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
  376. {
  377. struct soc_camera_device *icd = vq->priv_data;
  378. struct videobuf_buffer *vb = &buf->vb;
  379. dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  380. vb, vb->baddr, vb->bsize);
  381. /*
  382. * This waits until this buffer is out of danger, i.e., until it is no
  383. * longer in STATE_QUEUED or STATE_ACTIVE
  384. */
  385. videobuf_waiton(vb, 0, 0);
  386. videobuf_dma_contig_free(vq, vb);
  387. dev_dbg(&icd->dev, "%s freed\n", __func__);
  388. vb->state = VIDEOBUF_NEEDS_INIT;
  389. }
  390. static int mx2_videobuf_prepare(struct videobuf_queue *vq,
  391. struct videobuf_buffer *vb, enum v4l2_field field)
  392. {
  393. struct soc_camera_device *icd = vq->priv_data;
  394. struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
  395. int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
  396. icd->current_fmt->host_fmt);
  397. int ret = 0;
  398. dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  399. vb, vb->baddr, vb->bsize);
  400. if (bytes_per_line < 0)
  401. return bytes_per_line;
  402. #ifdef DEBUG
  403. /*
  404. * This can be useful if you want to see if we actually fill
  405. * the buffer with something
  406. */
  407. memset((void *)vb->baddr, 0xaa, vb->bsize);
  408. #endif
  409. if (buf->code != icd->current_fmt->code ||
  410. vb->width != icd->user_width ||
  411. vb->height != icd->user_height ||
  412. vb->field != field) {
  413. buf->code = icd->current_fmt->code;
  414. vb->width = icd->user_width;
  415. vb->height = icd->user_height;
  416. vb->field = field;
  417. vb->state = VIDEOBUF_NEEDS_INIT;
  418. }
  419. vb->size = bytes_per_line * vb->height;
  420. if (vb->baddr && vb->bsize < vb->size) {
  421. ret = -EINVAL;
  422. goto out;
  423. }
  424. if (vb->state == VIDEOBUF_NEEDS_INIT) {
  425. ret = videobuf_iolock(vq, vb, NULL);
  426. if (ret)
  427. goto fail;
  428. vb->state = VIDEOBUF_PREPARED;
  429. }
  430. return 0;
  431. fail:
  432. free_buffer(vq, buf);
  433. out:
  434. return ret;
  435. }
  436. static void mx2_videobuf_queue(struct videobuf_queue *vq,
  437. struct videobuf_buffer *vb)
  438. {
  439. struct soc_camera_device *icd = vq->priv_data;
  440. struct soc_camera_host *ici =
  441. to_soc_camera_host(icd->dev.parent);
  442. struct mx2_camera_dev *pcdev = ici->priv;
  443. struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
  444. unsigned long flags;
  445. dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  446. vb, vb->baddr, vb->bsize);
  447. spin_lock_irqsave(&pcdev->lock, flags);
  448. vb->state = VIDEOBUF_QUEUED;
  449. list_add_tail(&vb->queue, &pcdev->capture);
  450. if (mx27_camera_emma(pcdev)) {
  451. goto out;
  452. #ifdef CONFIG_MACH_MX27
  453. } else if (cpu_is_mx27()) {
  454. int ret;
  455. if (pcdev->active == NULL) {
  456. ret = imx_dma_setup_single(pcdev->dma,
  457. videobuf_to_dma_contig(vb), vb->size,
  458. (u32)pcdev->base_dma + 0x10,
  459. DMA_MODE_READ);
  460. if (ret) {
  461. vb->state = VIDEOBUF_ERROR;
  462. wake_up(&vb->done);
  463. goto out;
  464. }
  465. vb->state = VIDEOBUF_ACTIVE;
  466. pcdev->active = buf;
  467. }
  468. #endif
  469. } else { /* cpu_is_mx25() */
  470. u32 csicr3, dma_inten = 0;
  471. if (pcdev->fb1_active == NULL) {
  472. writel(videobuf_to_dma_contig(vb),
  473. pcdev->base_csi + CSIDMASA_FB1);
  474. pcdev->fb1_active = buf;
  475. dma_inten = CSICR1_FB1_DMA_INTEN;
  476. } else if (pcdev->fb2_active == NULL) {
  477. writel(videobuf_to_dma_contig(vb),
  478. pcdev->base_csi + CSIDMASA_FB2);
  479. pcdev->fb2_active = buf;
  480. dma_inten = CSICR1_FB2_DMA_INTEN;
  481. }
  482. if (dma_inten) {
  483. list_del(&vb->queue);
  484. vb->state = VIDEOBUF_ACTIVE;
  485. csicr3 = readl(pcdev->base_csi + CSICR3);
  486. /* Reflash DMA */
  487. writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
  488. pcdev->base_csi + CSICR3);
  489. /* clear & enable interrupts */
  490. writel(dma_inten, pcdev->base_csi + CSISR);
  491. pcdev->csicr1 |= dma_inten;
  492. writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
  493. /* enable DMA */
  494. csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
  495. writel(csicr3, pcdev->base_csi + CSICR3);
  496. }
  497. }
  498. out:
  499. spin_unlock_irqrestore(&pcdev->lock, flags);
  500. }
  501. static void mx2_videobuf_release(struct videobuf_queue *vq,
  502. struct videobuf_buffer *vb)
  503. {
  504. struct soc_camera_device *icd = vq->priv_data;
  505. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  506. struct mx2_camera_dev *pcdev = ici->priv;
  507. struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
  508. unsigned long flags;
  509. #ifdef DEBUG
  510. dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  511. vb, vb->baddr, vb->bsize);
  512. switch (vb->state) {
  513. case VIDEOBUF_ACTIVE:
  514. dev_info(&icd->dev, "%s (active)\n", __func__);
  515. break;
  516. case VIDEOBUF_QUEUED:
  517. dev_info(&icd->dev, "%s (queued)\n", __func__);
  518. break;
  519. case VIDEOBUF_PREPARED:
  520. dev_info(&icd->dev, "%s (prepared)\n", __func__);
  521. break;
  522. default:
  523. dev_info(&icd->dev, "%s (unknown) %d\n", __func__,
  524. vb->state);
  525. break;
  526. }
  527. #endif
  528. /*
  529. * Terminate only queued but inactive buffers. Active buffers are
  530. * released when they become inactive after videobuf_waiton().
  531. *
  532. * FIXME: implement forced termination of active buffers, so that the
  533. * user won't get stuck in an uninterruptible state. This requires a
  534. * specific handling for each of the three DMA types that this driver
  535. * supports.
  536. */
  537. spin_lock_irqsave(&pcdev->lock, flags);
  538. if (vb->state == VIDEOBUF_QUEUED) {
  539. list_del(&vb->queue);
  540. vb->state = VIDEOBUF_ERROR;
  541. }
  542. spin_unlock_irqrestore(&pcdev->lock, flags);
  543. free_buffer(vq, buf);
  544. }
  545. static struct videobuf_queue_ops mx2_videobuf_ops = {
  546. .buf_setup = mx2_videobuf_setup,
  547. .buf_prepare = mx2_videobuf_prepare,
  548. .buf_queue = mx2_videobuf_queue,
  549. .buf_release = mx2_videobuf_release,
  550. };
  551. static void mx2_camera_init_videobuf(struct videobuf_queue *q,
  552. struct soc_camera_device *icd)
  553. {
  554. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  555. struct mx2_camera_dev *pcdev = ici->priv;
  556. videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
  557. &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
  558. V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd);
  559. }
  560. #define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \
  561. SOCAM_MASTER | \
  562. SOCAM_VSYNC_ACTIVE_HIGH | \
  563. SOCAM_VSYNC_ACTIVE_LOW | \
  564. SOCAM_HSYNC_ACTIVE_HIGH | \
  565. SOCAM_HSYNC_ACTIVE_LOW | \
  566. SOCAM_PCLK_SAMPLE_RISING | \
  567. SOCAM_PCLK_SAMPLE_FALLING | \
  568. SOCAM_DATA_ACTIVE_HIGH | \
  569. SOCAM_DATA_ACTIVE_LOW)
  570. static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
  571. {
  572. u32 cntl;
  573. int count = 0;
  574. cntl = readl(pcdev->base_emma + PRP_CNTL);
  575. writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
  576. while (count++ < 100) {
  577. if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
  578. return 0;
  579. barrier();
  580. udelay(1);
  581. }
  582. return -ETIMEDOUT;
  583. }
  584. static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
  585. int bytesperline)
  586. {
  587. struct soc_camera_host *ici =
  588. to_soc_camera_host(icd->dev.parent);
  589. struct mx2_camera_dev *pcdev = ici->priv;
  590. writel(pcdev->discard_buffer_dma,
  591. pcdev->base_emma + PRP_DEST_RGB1_PTR);
  592. writel(pcdev->discard_buffer_dma,
  593. pcdev->base_emma + PRP_DEST_RGB2_PTR);
  594. /*
  595. * We only use the EMMA engine to get rid of the broken
  596. * DMA Engine. No color space consversion at the moment.
  597. * We adjust incoming and outgoing pixelformat to rgb16
  598. * and adjust the bytesperline accordingly.
  599. */
  600. writel(PRP_CNTL_CH1EN |
  601. PRP_CNTL_CSIEN |
  602. PRP_CNTL_DATA_IN_RGB16 |
  603. PRP_CNTL_CH1_OUT_RGB16 |
  604. PRP_CNTL_CH1_LEN |
  605. PRP_CNTL_CH1BYP |
  606. PRP_CNTL_CH1_TSKIP(0) |
  607. PRP_CNTL_IN_TSKIP(0),
  608. pcdev->base_emma + PRP_CNTL);
  609. writel(((bytesperline >> 1) << 16) | icd->user_height,
  610. pcdev->base_emma + PRP_SRC_FRAME_SIZE);
  611. writel(((bytesperline >> 1) << 16) | icd->user_height,
  612. pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
  613. writel(bytesperline,
  614. pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
  615. writel(0x2ca00565, /* RGB565 */
  616. pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
  617. writel(0x2ca00565, /* RGB565 */
  618. pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
  619. /* Enable interrupts */
  620. writel(PRP_INTR_RDERR |
  621. PRP_INTR_CH1WERR |
  622. PRP_INTR_CH2WERR |
  623. PRP_INTR_CH1FC |
  624. PRP_INTR_CH2FC |
  625. PRP_INTR_LBOVF |
  626. PRP_INTR_CH2OVF,
  627. pcdev->base_emma + PRP_INTR_CNTL);
  628. }
  629. static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
  630. __u32 pixfmt)
  631. {
  632. struct soc_camera_host *ici =
  633. to_soc_camera_host(icd->dev.parent);
  634. struct mx2_camera_dev *pcdev = ici->priv;
  635. unsigned long camera_flags, common_flags;
  636. int ret = 0;
  637. int bytesperline;
  638. u32 csicr1 = pcdev->csicr1;
  639. camera_flags = icd->ops->query_bus_param(icd);
  640. common_flags = soc_camera_bus_param_compatible(camera_flags,
  641. MX2_BUS_FLAGS);
  642. if (!common_flags)
  643. return -EINVAL;
  644. if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
  645. (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
  646. if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
  647. common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
  648. else
  649. common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
  650. }
  651. if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
  652. (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
  653. if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
  654. common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
  655. else
  656. common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
  657. }
  658. ret = icd->ops->set_bus_param(icd, common_flags);
  659. if (ret < 0)
  660. return ret;
  661. if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
  662. csicr1 |= CSICR1_INV_PCLK;
  663. if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
  664. csicr1 |= CSICR1_SOF_POL;
  665. if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
  666. csicr1 |= CSICR1_HSYNC_POL;
  667. if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
  668. csicr1 |= CSICR1_SWAP16_EN;
  669. if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
  670. csicr1 |= CSICR1_EXT_VSYNC;
  671. if (pcdev->platform_flags & MX2_CAMERA_CCIR)
  672. csicr1 |= CSICR1_CCIR_EN;
  673. if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
  674. csicr1 |= CSICR1_CCIR_MODE;
  675. if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
  676. csicr1 |= CSICR1_GCLK_MODE;
  677. if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
  678. csicr1 |= CSICR1_INV_DATA;
  679. if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
  680. csicr1 |= CSICR1_PACK_DIR;
  681. pcdev->csicr1 = csicr1;
  682. bytesperline = soc_mbus_bytes_per_line(icd->user_width,
  683. icd->current_fmt->host_fmt);
  684. if (bytesperline < 0)
  685. return bytesperline;
  686. if (mx27_camera_emma(pcdev)) {
  687. ret = mx27_camera_emma_prp_reset(pcdev);
  688. if (ret)
  689. return ret;
  690. if (pcdev->discard_buffer)
  691. dma_free_coherent(ici->v4l2_dev.dev,
  692. pcdev->discard_size, pcdev->discard_buffer,
  693. pcdev->discard_buffer_dma);
  694. /*
  695. * I didn't manage to properly enable/disable the prp
  696. * on a per frame basis during running transfers,
  697. * thus we allocate a buffer here and use it to
  698. * discard frames when no buffer is available.
  699. * Feel free to work on this ;)
  700. */
  701. pcdev->discard_size = icd->user_height * bytesperline;
  702. pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
  703. pcdev->discard_size, &pcdev->discard_buffer_dma,
  704. GFP_KERNEL);
  705. if (!pcdev->discard_buffer)
  706. return -ENOMEM;
  707. mx27_camera_emma_buf_init(icd, bytesperline);
  708. } else if (cpu_is_mx25()) {
  709. writel((bytesperline * icd->user_height) >> 2,
  710. pcdev->base_csi + CSIRXCNT);
  711. writel((bytesperline << 16) | icd->user_height,
  712. pcdev->base_csi + CSIIMAG_PARA);
  713. }
  714. writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
  715. return 0;
  716. }
  717. static int mx2_camera_set_crop(struct soc_camera_device *icd,
  718. struct v4l2_crop *a)
  719. {
  720. struct v4l2_rect *rect = &a->c;
  721. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  722. struct v4l2_mbus_framefmt mf;
  723. int ret;
  724. soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
  725. soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
  726. ret = v4l2_subdev_call(sd, video, s_crop, a);
  727. if (ret < 0)
  728. return ret;
  729. /* The capture device might have changed its output */
  730. ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
  731. if (ret < 0)
  732. return ret;
  733. dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
  734. mf.width, mf.height);
  735. icd->user_width = mf.width;
  736. icd->user_height = mf.height;
  737. return ret;
  738. }
  739. static int mx2_camera_set_fmt(struct soc_camera_device *icd,
  740. struct v4l2_format *f)
  741. {
  742. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  743. struct mx2_camera_dev *pcdev = ici->priv;
  744. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  745. const struct soc_camera_format_xlate *xlate;
  746. struct v4l2_pix_format *pix = &f->fmt.pix;
  747. struct v4l2_mbus_framefmt mf;
  748. int ret;
  749. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  750. if (!xlate) {
  751. dev_warn(icd->dev.parent, "Format %x not found\n",
  752. pix->pixelformat);
  753. return -EINVAL;
  754. }
  755. /* eMMA can only do RGB565 */
  756. if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565)
  757. return -EINVAL;
  758. mf.width = pix->width;
  759. mf.height = pix->height;
  760. mf.field = pix->field;
  761. mf.colorspace = pix->colorspace;
  762. mf.code = xlate->code;
  763. ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
  764. if (ret < 0 && ret != -ENOIOCTLCMD)
  765. return ret;
  766. if (mf.code != xlate->code)
  767. return -EINVAL;
  768. pix->width = mf.width;
  769. pix->height = mf.height;
  770. pix->field = mf.field;
  771. pix->colorspace = mf.colorspace;
  772. icd->current_fmt = xlate;
  773. return 0;
  774. }
  775. static int mx2_camera_try_fmt(struct soc_camera_device *icd,
  776. struct v4l2_format *f)
  777. {
  778. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  779. struct mx2_camera_dev *pcdev = ici->priv;
  780. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  781. const struct soc_camera_format_xlate *xlate;
  782. struct v4l2_pix_format *pix = &f->fmt.pix;
  783. struct v4l2_mbus_framefmt mf;
  784. __u32 pixfmt = pix->pixelformat;
  785. unsigned int width_limit;
  786. int ret;
  787. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  788. if (pixfmt && !xlate) {
  789. dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
  790. return -EINVAL;
  791. }
  792. /* FIXME: implement MX27 limits */
  793. /* eMMA can only do RGB565 */
  794. if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565)
  795. return -EINVAL;
  796. /* limit to MX25 hardware capabilities */
  797. if (cpu_is_mx25()) {
  798. if (xlate->host_fmt->bits_per_sample <= 8)
  799. width_limit = 0xffff * 4;
  800. else
  801. width_limit = 0xffff * 2;
  802. /* CSIIMAG_PARA limit */
  803. if (pix->width > width_limit)
  804. pix->width = width_limit;
  805. if (pix->height > 0xffff)
  806. pix->height = 0xffff;
  807. pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
  808. xlate->host_fmt);
  809. if (pix->bytesperline < 0)
  810. return pix->bytesperline;
  811. pix->sizeimage = pix->height * pix->bytesperline;
  812. if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */
  813. dev_warn(icd->dev.parent,
  814. "Image size (%u) above limit\n",
  815. pix->sizeimage);
  816. return -EINVAL;
  817. }
  818. }
  819. /* limit to sensor capabilities */
  820. mf.width = pix->width;
  821. mf.height = pix->height;
  822. mf.field = pix->field;
  823. mf.colorspace = pix->colorspace;
  824. mf.code = xlate->code;
  825. ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
  826. if (ret < 0)
  827. return ret;
  828. if (mf.field == V4L2_FIELD_ANY)
  829. mf.field = V4L2_FIELD_NONE;
  830. if (mf.field != V4L2_FIELD_NONE) {
  831. dev_err(icd->dev.parent, "Field type %d unsupported.\n",
  832. mf.field);
  833. return -EINVAL;
  834. }
  835. pix->width = mf.width;
  836. pix->height = mf.height;
  837. pix->field = mf.field;
  838. pix->colorspace = mf.colorspace;
  839. return 0;
  840. }
  841. static int mx2_camera_querycap(struct soc_camera_host *ici,
  842. struct v4l2_capability *cap)
  843. {
  844. /* cap->name is set by the friendly caller:-> */
  845. strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
  846. cap->version = MX2_CAM_VERSION_CODE;
  847. cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
  848. return 0;
  849. }
  850. static int mx2_camera_reqbufs(struct soc_camera_file *icf,
  851. struct v4l2_requestbuffers *p)
  852. {
  853. int i;
  854. for (i = 0; i < p->count; i++) {
  855. struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i],
  856. struct mx2_buffer, vb);
  857. INIT_LIST_HEAD(&buf->vb.queue);
  858. }
  859. return 0;
  860. }
  861. #ifdef CONFIG_MACH_MX27
  862. static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
  863. {
  864. struct videobuf_buffer *vb;
  865. struct mx2_buffer *buf;
  866. unsigned long flags;
  867. int ret;
  868. spin_lock_irqsave(&pcdev->lock, flags);
  869. if (!pcdev->active) {
  870. dev_err(pcdev->dev, "%s called with no active buffer!\n",
  871. __func__);
  872. goto out;
  873. }
  874. vb = &pcdev->active->vb;
  875. buf = container_of(vb, struct mx2_buffer, vb);
  876. WARN_ON(list_empty(&vb->queue));
  877. dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  878. vb, vb->baddr, vb->bsize);
  879. /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
  880. list_del_init(&vb->queue);
  881. vb->state = state;
  882. do_gettimeofday(&vb->ts);
  883. vb->field_count++;
  884. wake_up(&vb->done);
  885. if (list_empty(&pcdev->capture)) {
  886. pcdev->active = NULL;
  887. goto out;
  888. }
  889. pcdev->active = list_entry(pcdev->capture.next,
  890. struct mx2_buffer, vb.queue);
  891. vb = &pcdev->active->vb;
  892. vb->state = VIDEOBUF_ACTIVE;
  893. ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
  894. vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
  895. if (ret) {
  896. vb->state = VIDEOBUF_ERROR;
  897. pcdev->active = NULL;
  898. wake_up(&vb->done);
  899. }
  900. out:
  901. spin_unlock_irqrestore(&pcdev->lock, flags);
  902. }
  903. static void mx27_camera_dma_err_callback(int channel, void *data, int err)
  904. {
  905. struct mx2_camera_dev *pcdev = data;
  906. mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
  907. }
  908. static void mx27_camera_dma_callback(int channel, void *data)
  909. {
  910. struct mx2_camera_dev *pcdev = data;
  911. mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
  912. }
  913. #define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
  914. static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
  915. struct mx2_camera_dev *pcdev)
  916. {
  917. int err;
  918. pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
  919. if (pcdev->dma < 0) {
  920. dev_err(&pdev->dev, "%s failed to request DMA channel\n",
  921. __func__);
  922. return pcdev->dma;
  923. }
  924. err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
  925. mx27_camera_dma_err_callback, pcdev);
  926. if (err) {
  927. dev_err(&pdev->dev, "%s failed to set DMA callback\n",
  928. __func__);
  929. goto err_out;
  930. }
  931. err = imx_dma_config_channel(pcdev->dma,
  932. IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
  933. IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
  934. DMA_REQ_CSI_RX, 1);
  935. if (err) {
  936. dev_err(&pdev->dev, "%s failed to config DMA channel\n",
  937. __func__);
  938. goto err_out;
  939. }
  940. imx_dma_config_burstlen(pcdev->dma, 64);
  941. return 0;
  942. err_out:
  943. imx_dma_free(pcdev->dma);
  944. return err;
  945. }
  946. #endif /* CONFIG_MACH_MX27 */
  947. static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
  948. {
  949. struct soc_camera_file *icf = file->private_data;
  950. return videobuf_poll_stream(file, &icf->vb_vidq, pt);
  951. }
  952. static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
  953. .owner = THIS_MODULE,
  954. .add = mx2_camera_add_device,
  955. .remove = mx2_camera_remove_device,
  956. .set_fmt = mx2_camera_set_fmt,
  957. .set_crop = mx2_camera_set_crop,
  958. .try_fmt = mx2_camera_try_fmt,
  959. .init_videobuf = mx2_camera_init_videobuf,
  960. .reqbufs = mx2_camera_reqbufs,
  961. .poll = mx2_camera_poll,
  962. .querycap = mx2_camera_querycap,
  963. .set_bus_param = mx2_camera_set_bus_param,
  964. };
  965. static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
  966. int bufnum, int state)
  967. {
  968. struct mx2_buffer *buf;
  969. struct videobuf_buffer *vb;
  970. unsigned long phys;
  971. if (!list_empty(&pcdev->active_bufs)) {
  972. buf = list_entry(pcdev->active_bufs.next,
  973. struct mx2_buffer, vb.queue);
  974. BUG_ON(buf->bufnum != bufnum);
  975. vb = &buf->vb;
  976. #ifdef DEBUG
  977. phys = videobuf_to_dma_contig(vb);
  978. if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
  979. != phys) {
  980. dev_err(pcdev->dev, "%p != %p\n", phys,
  981. readl(pcdev->base_emma +
  982. PRP_DEST_RGB1_PTR +
  983. 4 * bufnum));
  984. }
  985. #endif
  986. dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
  987. vb->baddr, vb->bsize);
  988. list_del(&vb->queue);
  989. vb->state = state;
  990. do_gettimeofday(&vb->ts);
  991. vb->field_count++;
  992. wake_up(&vb->done);
  993. }
  994. if (list_empty(&pcdev->capture)) {
  995. writel(pcdev->discard_buffer_dma, pcdev->base_emma +
  996. PRP_DEST_RGB1_PTR + 4 * bufnum);
  997. return;
  998. }
  999. buf = list_entry(pcdev->capture.next,
  1000. struct mx2_buffer, vb.queue);
  1001. buf->bufnum = bufnum;
  1002. list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
  1003. vb = &buf->vb;
  1004. vb->state = VIDEOBUF_ACTIVE;
  1005. phys = videobuf_to_dma_contig(vb);
  1006. writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
  1007. }
  1008. static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
  1009. {
  1010. struct mx2_camera_dev *pcdev = data;
  1011. unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
  1012. struct mx2_buffer *buf;
  1013. if (status & (1 << 7)) { /* overflow */
  1014. u32 cntl;
  1015. /*
  1016. * We only disable channel 1 here since this is the only
  1017. * enabled channel
  1018. *
  1019. * FIXME: the correct DMA overflow handling should be resetting
  1020. * the buffer, returning an error frame, and continuing with
  1021. * the next one.
  1022. */
  1023. cntl = readl(pcdev->base_emma + PRP_CNTL);
  1024. writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
  1025. writel(cntl, pcdev->base_emma + PRP_CNTL);
  1026. }
  1027. if ((status & (3 << 5)) == (3 << 5)
  1028. && !list_empty(&pcdev->active_bufs)) {
  1029. /*
  1030. * Both buffers have triggered, process the one we're expecting
  1031. * to first
  1032. */
  1033. buf = list_entry(pcdev->active_bufs.next,
  1034. struct mx2_buffer, vb.queue);
  1035. mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
  1036. status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
  1037. }
  1038. if (status & (1 << 6))
  1039. mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
  1040. if (status & (1 << 5))
  1041. mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
  1042. writel(status, pcdev->base_emma + PRP_INTRSTATUS);
  1043. return IRQ_HANDLED;
  1044. }
  1045. static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
  1046. {
  1047. struct resource *res_emma = pcdev->res_emma;
  1048. int err = 0;
  1049. if (!request_mem_region(res_emma->start, resource_size(res_emma),
  1050. MX2_CAM_DRV_NAME)) {
  1051. err = -EBUSY;
  1052. goto out;
  1053. }
  1054. pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
  1055. if (!pcdev->base_emma) {
  1056. err = -ENOMEM;
  1057. goto exit_release;
  1058. }
  1059. err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
  1060. MX2_CAM_DRV_NAME, pcdev);
  1061. if (err) {
  1062. dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
  1063. goto exit_iounmap;
  1064. }
  1065. pcdev->clk_emma = clk_get(NULL, "emma");
  1066. if (IS_ERR(pcdev->clk_emma)) {
  1067. err = PTR_ERR(pcdev->clk_emma);
  1068. goto exit_free_irq;
  1069. }
  1070. clk_enable(pcdev->clk_emma);
  1071. err = mx27_camera_emma_prp_reset(pcdev);
  1072. if (err)
  1073. goto exit_clk_emma_put;
  1074. return err;
  1075. exit_clk_emma_put:
  1076. clk_disable(pcdev->clk_emma);
  1077. clk_put(pcdev->clk_emma);
  1078. exit_free_irq:
  1079. free_irq(pcdev->irq_emma, pcdev);
  1080. exit_iounmap:
  1081. iounmap(pcdev->base_emma);
  1082. exit_release:
  1083. release_mem_region(res_emma->start, resource_size(res_emma));
  1084. out:
  1085. return err;
  1086. }
  1087. static int __devinit mx2_camera_probe(struct platform_device *pdev)
  1088. {
  1089. struct mx2_camera_dev *pcdev;
  1090. struct resource *res_csi, *res_emma;
  1091. void __iomem *base_csi;
  1092. int irq_csi, irq_emma;
  1093. irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
  1094. : mx27_camera_irq;
  1095. int err = 0;
  1096. dev_dbg(&pdev->dev, "initialising\n");
  1097. res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1098. irq_csi = platform_get_irq(pdev, 0);
  1099. if (res_csi == NULL || irq_csi < 0) {
  1100. dev_err(&pdev->dev, "Missing platform resources data\n");
  1101. err = -ENODEV;
  1102. goto exit;
  1103. }
  1104. pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
  1105. if (!pcdev) {
  1106. dev_err(&pdev->dev, "Could not allocate pcdev\n");
  1107. err = -ENOMEM;
  1108. goto exit;
  1109. }
  1110. pcdev->clk_csi = clk_get(&pdev->dev, NULL);
  1111. if (IS_ERR(pcdev->clk_csi)) {
  1112. err = PTR_ERR(pcdev->clk_csi);
  1113. goto exit_kfree;
  1114. }
  1115. dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
  1116. clk_get_rate(pcdev->clk_csi));
  1117. /* Initialize DMA */
  1118. #ifdef CONFIG_MACH_MX27
  1119. if (cpu_is_mx27()) {
  1120. err = mx27_camera_dma_init(pdev, pcdev);
  1121. if (err)
  1122. goto exit_clk_put;
  1123. }
  1124. #endif /* CONFIG_MACH_MX27 */
  1125. pcdev->res_csi = res_csi;
  1126. pcdev->pdata = pdev->dev.platform_data;
  1127. if (pcdev->pdata) {
  1128. long rate;
  1129. pcdev->platform_flags = pcdev->pdata->flags;
  1130. rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
  1131. if (rate <= 0) {
  1132. err = -ENODEV;
  1133. goto exit_dma_free;
  1134. }
  1135. err = clk_set_rate(pcdev->clk_csi, rate);
  1136. if (err < 0)
  1137. goto exit_dma_free;
  1138. }
  1139. INIT_LIST_HEAD(&pcdev->capture);
  1140. INIT_LIST_HEAD(&pcdev->active_bufs);
  1141. spin_lock_init(&pcdev->lock);
  1142. /*
  1143. * Request the regions.
  1144. */
  1145. if (!request_mem_region(res_csi->start, resource_size(res_csi),
  1146. MX2_CAM_DRV_NAME)) {
  1147. err = -EBUSY;
  1148. goto exit_dma_free;
  1149. }
  1150. base_csi = ioremap(res_csi->start, resource_size(res_csi));
  1151. if (!base_csi) {
  1152. err = -ENOMEM;
  1153. goto exit_release;
  1154. }
  1155. pcdev->irq_csi = irq_csi;
  1156. pcdev->base_csi = base_csi;
  1157. pcdev->base_dma = res_csi->start;
  1158. pcdev->dev = &pdev->dev;
  1159. err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
  1160. MX2_CAM_DRV_NAME, pcdev);
  1161. if (err) {
  1162. dev_err(pcdev->dev, "Camera interrupt register failed \n");
  1163. goto exit_iounmap;
  1164. }
  1165. if (cpu_is_mx27()) {
  1166. /* EMMA support */
  1167. res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1168. irq_emma = platform_get_irq(pdev, 1);
  1169. if (res_emma && irq_emma >= 0) {
  1170. dev_info(&pdev->dev, "Using EMMA\n");
  1171. pcdev->use_emma = 1;
  1172. pcdev->res_emma = res_emma;
  1173. pcdev->irq_emma = irq_emma;
  1174. if (mx27_camera_emma_init(pcdev))
  1175. goto exit_free_irq;
  1176. }
  1177. }
  1178. pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
  1179. pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
  1180. pcdev->soc_host.priv = pcdev;
  1181. pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
  1182. pcdev->soc_host.nr = pdev->id;
  1183. err = soc_camera_host_register(&pcdev->soc_host);
  1184. if (err)
  1185. goto exit_free_emma;
  1186. return 0;
  1187. exit_free_emma:
  1188. if (mx27_camera_emma(pcdev)) {
  1189. free_irq(pcdev->irq_emma, pcdev);
  1190. clk_disable(pcdev->clk_emma);
  1191. clk_put(pcdev->clk_emma);
  1192. iounmap(pcdev->base_emma);
  1193. release_mem_region(res_emma->start, resource_size(res_emma));
  1194. }
  1195. exit_free_irq:
  1196. free_irq(pcdev->irq_csi, pcdev);
  1197. exit_iounmap:
  1198. iounmap(base_csi);
  1199. exit_release:
  1200. release_mem_region(res_csi->start, resource_size(res_csi));
  1201. exit_dma_free:
  1202. #ifdef CONFIG_MACH_MX27
  1203. if (cpu_is_mx27())
  1204. imx_dma_free(pcdev->dma);
  1205. exit_clk_put:
  1206. clk_put(pcdev->clk_csi);
  1207. #endif /* CONFIG_MACH_MX27 */
  1208. exit_kfree:
  1209. kfree(pcdev);
  1210. exit:
  1211. return err;
  1212. }
  1213. static int __devexit mx2_camera_remove(struct platform_device *pdev)
  1214. {
  1215. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  1216. struct mx2_camera_dev *pcdev = container_of(soc_host,
  1217. struct mx2_camera_dev, soc_host);
  1218. struct resource *res;
  1219. clk_put(pcdev->clk_csi);
  1220. #ifdef CONFIG_MACH_MX27
  1221. if (cpu_is_mx27())
  1222. imx_dma_free(pcdev->dma);
  1223. #endif /* CONFIG_MACH_MX27 */
  1224. free_irq(pcdev->irq_csi, pcdev);
  1225. if (mx27_camera_emma(pcdev))
  1226. free_irq(pcdev->irq_emma, pcdev);
  1227. soc_camera_host_unregister(&pcdev->soc_host);
  1228. iounmap(pcdev->base_csi);
  1229. if (mx27_camera_emma(pcdev)) {
  1230. clk_disable(pcdev->clk_emma);
  1231. clk_put(pcdev->clk_emma);
  1232. iounmap(pcdev->base_emma);
  1233. res = pcdev->res_emma;
  1234. release_mem_region(res->start, resource_size(res));
  1235. }
  1236. res = pcdev->res_csi;
  1237. release_mem_region(res->start, resource_size(res));
  1238. kfree(pcdev);
  1239. dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
  1240. return 0;
  1241. }
  1242. static struct platform_driver mx2_camera_driver = {
  1243. .driver = {
  1244. .name = MX2_CAM_DRV_NAME,
  1245. },
  1246. .remove = __devexit_p(mx2_camera_remove),
  1247. };
  1248. static int __init mx2_camera_init(void)
  1249. {
  1250. return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
  1251. }
  1252. static void __exit mx2_camera_exit(void)
  1253. {
  1254. return platform_driver_unregister(&mx2_camera_driver);
  1255. }
  1256. module_init(mx2_camera_init);
  1257. module_exit(mx2_camera_exit);
  1258. MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
  1259. MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
  1260. MODULE_LICENSE("GPL");