cm4040_cs.c 16 KB

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  1. /*
  2. * A driver for the Omnikey PCMCIA smartcard reader CardMan 4040
  3. *
  4. * (c) 2000-2004 Omnikey AG (http://www.omnikey.com/)
  5. *
  6. * (C) 2005-2006 Harald Welte <laforge@gnumonks.org>
  7. * - add support for poll()
  8. * - driver cleanup
  9. * - add waitqueues
  10. * - adhere to linux kernel coding style and policies
  11. * - support 2.6.13 "new style" pcmcia interface
  12. * - add class interface for udev device creation
  13. *
  14. * The device basically is a USB CCID compliant device that has been
  15. * attached to an I/O-Mapped FIFO.
  16. *
  17. * All rights reserved, Dual BSD/GPL Licensed.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/slab.h>
  22. #include <linux/init.h>
  23. #include <linux/fs.h>
  24. #include <linux/delay.h>
  25. #include <linux/poll.h>
  26. #include <linux/smp_lock.h>
  27. #include <linux/wait.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/io.h>
  30. #include <pcmcia/cs_types.h>
  31. #include <pcmcia/cs.h>
  32. #include <pcmcia/cistpl.h>
  33. #include <pcmcia/cisreg.h>
  34. #include <pcmcia/ciscode.h>
  35. #include <pcmcia/ds.h>
  36. #include "cm4040_cs.h"
  37. #define reader_to_dev(x) (&x->p_dev->dev)
  38. /* n (debug level) is ignored */
  39. /* additional debug output may be enabled by re-compiling with
  40. * CM4040_DEBUG set */
  41. /* #define CM4040_DEBUG */
  42. #define DEBUGP(n, rdr, x, args...) do { \
  43. dev_dbg(reader_to_dev(rdr), "%s:" x, \
  44. __func__ , ## args); \
  45. } while (0)
  46. static char *version =
  47. "OMNIKEY CardMan 4040 v1.1.0gm5 - All bugs added by Harald Welte";
  48. #define CCID_DRIVER_BULK_DEFAULT_TIMEOUT (150*HZ)
  49. #define CCID_DRIVER_ASYNC_POWERUP_TIMEOUT (35*HZ)
  50. #define CCID_DRIVER_MINIMUM_TIMEOUT (3*HZ)
  51. #define READ_WRITE_BUFFER_SIZE 512
  52. #define POLL_LOOP_COUNT 1000
  53. /* how often to poll for fifo status change */
  54. #define POLL_PERIOD msecs_to_jiffies(10)
  55. static void reader_release(struct pcmcia_device *link);
  56. static int major;
  57. static struct class *cmx_class;
  58. #define BS_READABLE 0x01
  59. #define BS_WRITABLE 0x02
  60. struct reader_dev {
  61. struct pcmcia_device *p_dev;
  62. wait_queue_head_t devq;
  63. wait_queue_head_t poll_wait;
  64. wait_queue_head_t read_wait;
  65. wait_queue_head_t write_wait;
  66. unsigned long buffer_status;
  67. unsigned long timeout;
  68. unsigned char s_buf[READ_WRITE_BUFFER_SIZE];
  69. unsigned char r_buf[READ_WRITE_BUFFER_SIZE];
  70. struct timer_list poll_timer;
  71. };
  72. static struct pcmcia_device *dev_table[CM_MAX_DEV];
  73. #ifndef CM4040_DEBUG
  74. #define xoutb outb
  75. #define xinb inb
  76. #else
  77. static inline void xoutb(unsigned char val, unsigned short port)
  78. {
  79. pr_debug("outb(val=%.2x,port=%.4x)\n", val, port);
  80. outb(val, port);
  81. }
  82. static inline unsigned char xinb(unsigned short port)
  83. {
  84. unsigned char val;
  85. val = inb(port);
  86. pr_debug("%.2x=inb(%.4x)\n", val, port);
  87. return val;
  88. }
  89. #endif
  90. /* poll the device fifo status register. not to be confused with
  91. * the poll syscall. */
  92. static void cm4040_do_poll(unsigned long dummy)
  93. {
  94. struct reader_dev *dev = (struct reader_dev *) dummy;
  95. unsigned int obs = xinb(dev->p_dev->io.BasePort1
  96. + REG_OFFSET_BUFFER_STATUS);
  97. if ((obs & BSR_BULK_IN_FULL)) {
  98. set_bit(BS_READABLE, &dev->buffer_status);
  99. DEBUGP(4, dev, "waking up read_wait\n");
  100. wake_up_interruptible(&dev->read_wait);
  101. } else
  102. clear_bit(BS_READABLE, &dev->buffer_status);
  103. if (!(obs & BSR_BULK_OUT_FULL)) {
  104. set_bit(BS_WRITABLE, &dev->buffer_status);
  105. DEBUGP(4, dev, "waking up write_wait\n");
  106. wake_up_interruptible(&dev->write_wait);
  107. } else
  108. clear_bit(BS_WRITABLE, &dev->buffer_status);
  109. if (dev->buffer_status)
  110. wake_up_interruptible(&dev->poll_wait);
  111. mod_timer(&dev->poll_timer, jiffies + POLL_PERIOD);
  112. }
  113. static void cm4040_stop_poll(struct reader_dev *dev)
  114. {
  115. del_timer_sync(&dev->poll_timer);
  116. }
  117. static int wait_for_bulk_out_ready(struct reader_dev *dev)
  118. {
  119. int i, rc;
  120. int iobase = dev->p_dev->io.BasePort1;
  121. for (i = 0; i < POLL_LOOP_COUNT; i++) {
  122. if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS)
  123. & BSR_BULK_OUT_FULL) == 0) {
  124. DEBUGP(4, dev, "BulkOut empty (i=%d)\n", i);
  125. return 1;
  126. }
  127. }
  128. DEBUGP(4, dev, "wait_event_interruptible_timeout(timeout=%ld\n",
  129. dev->timeout);
  130. rc = wait_event_interruptible_timeout(dev->write_wait,
  131. test_and_clear_bit(BS_WRITABLE,
  132. &dev->buffer_status),
  133. dev->timeout);
  134. if (rc > 0)
  135. DEBUGP(4, dev, "woke up: BulkOut empty\n");
  136. else if (rc == 0)
  137. DEBUGP(4, dev, "woke up: BulkOut full, returning 0 :(\n");
  138. else if (rc < 0)
  139. DEBUGP(4, dev, "woke up: signal arrived\n");
  140. return rc;
  141. }
  142. /* Write to Sync Control Register */
  143. static int write_sync_reg(unsigned char val, struct reader_dev *dev)
  144. {
  145. int iobase = dev->p_dev->io.BasePort1;
  146. int rc;
  147. rc = wait_for_bulk_out_ready(dev);
  148. if (rc <= 0)
  149. return rc;
  150. xoutb(val, iobase + REG_OFFSET_SYNC_CONTROL);
  151. rc = wait_for_bulk_out_ready(dev);
  152. if (rc <= 0)
  153. return rc;
  154. return 1;
  155. }
  156. static int wait_for_bulk_in_ready(struct reader_dev *dev)
  157. {
  158. int i, rc;
  159. int iobase = dev->p_dev->io.BasePort1;
  160. for (i = 0; i < POLL_LOOP_COUNT; i++) {
  161. if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS)
  162. & BSR_BULK_IN_FULL) == BSR_BULK_IN_FULL) {
  163. DEBUGP(3, dev, "BulkIn full (i=%d)\n", i);
  164. return 1;
  165. }
  166. }
  167. DEBUGP(4, dev, "wait_event_interruptible_timeout(timeout=%ld\n",
  168. dev->timeout);
  169. rc = wait_event_interruptible_timeout(dev->read_wait,
  170. test_and_clear_bit(BS_READABLE,
  171. &dev->buffer_status),
  172. dev->timeout);
  173. if (rc > 0)
  174. DEBUGP(4, dev, "woke up: BulkIn full\n");
  175. else if (rc == 0)
  176. DEBUGP(4, dev, "woke up: BulkIn not full, returning 0 :(\n");
  177. else if (rc < 0)
  178. DEBUGP(4, dev, "woke up: signal arrived\n");
  179. return rc;
  180. }
  181. static ssize_t cm4040_read(struct file *filp, char __user *buf,
  182. size_t count, loff_t *ppos)
  183. {
  184. struct reader_dev *dev = filp->private_data;
  185. int iobase = dev->p_dev->io.BasePort1;
  186. size_t bytes_to_read;
  187. unsigned long i;
  188. size_t min_bytes_to_read;
  189. int rc;
  190. unsigned char uc;
  191. DEBUGP(2, dev, "-> cm4040_read(%s,%d)\n", current->comm, current->pid);
  192. if (count == 0)
  193. return 0;
  194. if (count < 10)
  195. return -EFAULT;
  196. if (filp->f_flags & O_NONBLOCK) {
  197. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  198. DEBUGP(2, dev, "<- cm4040_read (failure)\n");
  199. return -EAGAIN;
  200. }
  201. if (!pcmcia_dev_present(dev->p_dev))
  202. return -ENODEV;
  203. for (i = 0; i < 5; i++) {
  204. rc = wait_for_bulk_in_ready(dev);
  205. if (rc <= 0) {
  206. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  207. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  208. if (rc == -ERESTARTSYS)
  209. return rc;
  210. return -EIO;
  211. }
  212. dev->r_buf[i] = xinb(iobase + REG_OFFSET_BULK_IN);
  213. #ifdef CM4040_DEBUG
  214. pr_debug("%lu:%2x ", i, dev->r_buf[i]);
  215. }
  216. pr_debug("\n");
  217. #else
  218. }
  219. #endif
  220. bytes_to_read = 5 + le32_to_cpu(*(__le32 *)&dev->r_buf[1]);
  221. DEBUGP(6, dev, "BytesToRead=%zu\n", bytes_to_read);
  222. min_bytes_to_read = min(count, bytes_to_read + 5);
  223. min_bytes_to_read = min_t(size_t, min_bytes_to_read, READ_WRITE_BUFFER_SIZE);
  224. DEBUGP(6, dev, "Min=%zu\n", min_bytes_to_read);
  225. for (i = 0; i < (min_bytes_to_read-5); i++) {
  226. rc = wait_for_bulk_in_ready(dev);
  227. if (rc <= 0) {
  228. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  229. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  230. if (rc == -ERESTARTSYS)
  231. return rc;
  232. return -EIO;
  233. }
  234. dev->r_buf[i+5] = xinb(iobase + REG_OFFSET_BULK_IN);
  235. #ifdef CM4040_DEBUG
  236. pr_debug("%lu:%2x ", i, dev->r_buf[i]);
  237. }
  238. pr_debug("\n");
  239. #else
  240. }
  241. #endif
  242. *ppos = min_bytes_to_read;
  243. if (copy_to_user(buf, dev->r_buf, min_bytes_to_read))
  244. return -EFAULT;
  245. rc = wait_for_bulk_in_ready(dev);
  246. if (rc <= 0) {
  247. DEBUGP(5, dev, "wait_for_bulk_in_ready rc=%.2x\n", rc);
  248. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  249. if (rc == -ERESTARTSYS)
  250. return rc;
  251. return -EIO;
  252. }
  253. rc = write_sync_reg(SCR_READER_TO_HOST_DONE, dev);
  254. if (rc <= 0) {
  255. DEBUGP(5, dev, "write_sync_reg c=%.2x\n", rc);
  256. DEBUGP(2, dev, "<- cm4040_read (failed)\n");
  257. if (rc == -ERESTARTSYS)
  258. return rc;
  259. else
  260. return -EIO;
  261. }
  262. uc = xinb(iobase + REG_OFFSET_BULK_IN);
  263. DEBUGP(2, dev, "<- cm4040_read (successfully)\n");
  264. return min_bytes_to_read;
  265. }
  266. static ssize_t cm4040_write(struct file *filp, const char __user *buf,
  267. size_t count, loff_t *ppos)
  268. {
  269. struct reader_dev *dev = filp->private_data;
  270. int iobase = dev->p_dev->io.BasePort1;
  271. ssize_t rc;
  272. int i;
  273. unsigned int bytes_to_write;
  274. DEBUGP(2, dev, "-> cm4040_write(%s,%d)\n", current->comm, current->pid);
  275. if (count == 0) {
  276. DEBUGP(2, dev, "<- cm4040_write empty read (successfully)\n");
  277. return 0;
  278. }
  279. if ((count < 5) || (count > READ_WRITE_BUFFER_SIZE)) {
  280. DEBUGP(2, dev, "<- cm4040_write buffersize=%Zd < 5\n", count);
  281. return -EIO;
  282. }
  283. if (filp->f_flags & O_NONBLOCK) {
  284. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  285. DEBUGP(4, dev, "<- cm4040_write (failure)\n");
  286. return -EAGAIN;
  287. }
  288. if (!pcmcia_dev_present(dev->p_dev))
  289. return -ENODEV;
  290. bytes_to_write = count;
  291. if (copy_from_user(dev->s_buf, buf, bytes_to_write))
  292. return -EFAULT;
  293. switch (dev->s_buf[0]) {
  294. case CMD_PC_TO_RDR_XFRBLOCK:
  295. case CMD_PC_TO_RDR_SECURE:
  296. case CMD_PC_TO_RDR_TEST_SECURE:
  297. case CMD_PC_TO_RDR_OK_SECURE:
  298. dev->timeout = CCID_DRIVER_BULK_DEFAULT_TIMEOUT;
  299. break;
  300. case CMD_PC_TO_RDR_ICCPOWERON:
  301. dev->timeout = CCID_DRIVER_ASYNC_POWERUP_TIMEOUT;
  302. break;
  303. case CMD_PC_TO_RDR_GETSLOTSTATUS:
  304. case CMD_PC_TO_RDR_ICCPOWEROFF:
  305. case CMD_PC_TO_RDR_GETPARAMETERS:
  306. case CMD_PC_TO_RDR_RESETPARAMETERS:
  307. case CMD_PC_TO_RDR_SETPARAMETERS:
  308. case CMD_PC_TO_RDR_ESCAPE:
  309. case CMD_PC_TO_RDR_ICCCLOCK:
  310. default:
  311. dev->timeout = CCID_DRIVER_MINIMUM_TIMEOUT;
  312. break;
  313. }
  314. rc = write_sync_reg(SCR_HOST_TO_READER_START, dev);
  315. if (rc <= 0) {
  316. DEBUGP(5, dev, "write_sync_reg c=%.2Zx\n", rc);
  317. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  318. if (rc == -ERESTARTSYS)
  319. return rc;
  320. else
  321. return -EIO;
  322. }
  323. DEBUGP(4, dev, "start \n");
  324. for (i = 0; i < bytes_to_write; i++) {
  325. rc = wait_for_bulk_out_ready(dev);
  326. if (rc <= 0) {
  327. DEBUGP(5, dev, "wait_for_bulk_out_ready rc=%.2Zx\n",
  328. rc);
  329. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  330. if (rc == -ERESTARTSYS)
  331. return rc;
  332. else
  333. return -EIO;
  334. }
  335. xoutb(dev->s_buf[i],iobase + REG_OFFSET_BULK_OUT);
  336. }
  337. DEBUGP(4, dev, "end\n");
  338. rc = write_sync_reg(SCR_HOST_TO_READER_DONE, dev);
  339. if (rc <= 0) {
  340. DEBUGP(5, dev, "write_sync_reg c=%.2Zx\n", rc);
  341. DEBUGP(2, dev, "<- cm4040_write (failed)\n");
  342. if (rc == -ERESTARTSYS)
  343. return rc;
  344. else
  345. return -EIO;
  346. }
  347. DEBUGP(2, dev, "<- cm4040_write (successfully)\n");
  348. return count;
  349. }
  350. static unsigned int cm4040_poll(struct file *filp, poll_table *wait)
  351. {
  352. struct reader_dev *dev = filp->private_data;
  353. unsigned int mask = 0;
  354. poll_wait(filp, &dev->poll_wait, wait);
  355. if (test_and_clear_bit(BS_READABLE, &dev->buffer_status))
  356. mask |= POLLIN | POLLRDNORM;
  357. if (test_and_clear_bit(BS_WRITABLE, &dev->buffer_status))
  358. mask |= POLLOUT | POLLWRNORM;
  359. DEBUGP(2, dev, "<- cm4040_poll(%u)\n", mask);
  360. return mask;
  361. }
  362. static int cm4040_open(struct inode *inode, struct file *filp)
  363. {
  364. struct reader_dev *dev;
  365. struct pcmcia_device *link;
  366. int minor = iminor(inode);
  367. int ret;
  368. if (minor >= CM_MAX_DEV)
  369. return -ENODEV;
  370. lock_kernel();
  371. link = dev_table[minor];
  372. if (link == NULL || !pcmcia_dev_present(link)) {
  373. ret = -ENODEV;
  374. goto out;
  375. }
  376. if (link->open) {
  377. ret = -EBUSY;
  378. goto out;
  379. }
  380. dev = link->priv;
  381. filp->private_data = dev;
  382. if (filp->f_flags & O_NONBLOCK) {
  383. DEBUGP(4, dev, "filep->f_flags O_NONBLOCK set\n");
  384. ret = -EAGAIN;
  385. goto out;
  386. }
  387. link->open = 1;
  388. dev->poll_timer.data = (unsigned long) dev;
  389. mod_timer(&dev->poll_timer, jiffies + POLL_PERIOD);
  390. DEBUGP(2, dev, "<- cm4040_open (successfully)\n");
  391. ret = nonseekable_open(inode, filp);
  392. out:
  393. unlock_kernel();
  394. return ret;
  395. }
  396. static int cm4040_close(struct inode *inode, struct file *filp)
  397. {
  398. struct reader_dev *dev = filp->private_data;
  399. struct pcmcia_device *link;
  400. int minor = iminor(inode);
  401. DEBUGP(2, dev, "-> cm4040_close(maj/min=%d.%d)\n", imajor(inode),
  402. iminor(inode));
  403. if (minor >= CM_MAX_DEV)
  404. return -ENODEV;
  405. link = dev_table[minor];
  406. if (link == NULL)
  407. return -ENODEV;
  408. cm4040_stop_poll(dev);
  409. link->open = 0;
  410. wake_up(&dev->devq);
  411. DEBUGP(2, dev, "<- cm4040_close\n");
  412. return 0;
  413. }
  414. static void cm4040_reader_release(struct pcmcia_device *link)
  415. {
  416. struct reader_dev *dev = link->priv;
  417. DEBUGP(3, dev, "-> cm4040_reader_release\n");
  418. while (link->open) {
  419. DEBUGP(3, dev, KERN_INFO MODULE_NAME ": delaying release "
  420. "until process has terminated\n");
  421. wait_event(dev->devq, (link->open == 0));
  422. }
  423. DEBUGP(3, dev, "<- cm4040_reader_release\n");
  424. return;
  425. }
  426. static int cm4040_config_check(struct pcmcia_device *p_dev,
  427. cistpl_cftable_entry_t *cfg,
  428. cistpl_cftable_entry_t *dflt,
  429. unsigned int vcc,
  430. void *priv_data)
  431. {
  432. int rc;
  433. if (!cfg->io.nwin)
  434. return -ENODEV;
  435. /* Get the IOaddr */
  436. p_dev->io.BasePort1 = cfg->io.win[0].base;
  437. p_dev->io.NumPorts1 = cfg->io.win[0].len;
  438. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  439. if (!(cfg->io.flags & CISTPL_IO_8BIT))
  440. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  441. if (!(cfg->io.flags & CISTPL_IO_16BIT))
  442. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  443. p_dev->io.IOAddrLines = cfg->io.flags & CISTPL_IO_LINES_MASK;
  444. rc = pcmcia_request_io(p_dev, &p_dev->io);
  445. dev_printk(KERN_INFO, &p_dev->dev,
  446. "pcmcia_request_io returned 0x%x\n", rc);
  447. return rc;
  448. }
  449. static int reader_config(struct pcmcia_device *link, int devno)
  450. {
  451. struct reader_dev *dev;
  452. int fail_rc;
  453. link->io.BasePort2 = 0;
  454. link->io.NumPorts2 = 0;
  455. link->io.Attributes2 = 0;
  456. if (pcmcia_loop_config(link, cm4040_config_check, NULL))
  457. goto cs_release;
  458. link->conf.IntType = 00000002;
  459. fail_rc = pcmcia_request_configuration(link, &link->conf);
  460. if (fail_rc != 0) {
  461. dev_printk(KERN_INFO, &link->dev,
  462. "pcmcia_request_configuration failed 0x%x\n",
  463. fail_rc);
  464. goto cs_release;
  465. }
  466. dev = link->priv;
  467. DEBUGP(2, dev, "device " DEVICE_NAME "%d at 0x%.4x-0x%.4x\n", devno,
  468. link->io.BasePort1, link->io.BasePort1+link->io.NumPorts1);
  469. DEBUGP(2, dev, "<- reader_config (succ)\n");
  470. return 0;
  471. cs_release:
  472. reader_release(link);
  473. return -ENODEV;
  474. }
  475. static void reader_release(struct pcmcia_device *link)
  476. {
  477. cm4040_reader_release(link);
  478. pcmcia_disable_device(link);
  479. }
  480. static int reader_probe(struct pcmcia_device *link)
  481. {
  482. struct reader_dev *dev;
  483. int i, ret;
  484. for (i = 0; i < CM_MAX_DEV; i++) {
  485. if (dev_table[i] == NULL)
  486. break;
  487. }
  488. if (i == CM_MAX_DEV)
  489. return -ENODEV;
  490. dev = kzalloc(sizeof(struct reader_dev), GFP_KERNEL);
  491. if (dev == NULL)
  492. return -ENOMEM;
  493. dev->timeout = CCID_DRIVER_MINIMUM_TIMEOUT;
  494. dev->buffer_status = 0;
  495. link->priv = dev;
  496. dev->p_dev = link;
  497. link->conf.IntType = INT_MEMORY_AND_IO;
  498. dev_table[i] = link;
  499. init_waitqueue_head(&dev->devq);
  500. init_waitqueue_head(&dev->poll_wait);
  501. init_waitqueue_head(&dev->read_wait);
  502. init_waitqueue_head(&dev->write_wait);
  503. setup_timer(&dev->poll_timer, cm4040_do_poll, 0);
  504. ret = reader_config(link, i);
  505. if (ret) {
  506. dev_table[i] = NULL;
  507. kfree(dev);
  508. return ret;
  509. }
  510. device_create(cmx_class, NULL, MKDEV(major, i), NULL, "cmx%d", i);
  511. return 0;
  512. }
  513. static void reader_detach(struct pcmcia_device *link)
  514. {
  515. struct reader_dev *dev = link->priv;
  516. int devno;
  517. /* find device */
  518. for (devno = 0; devno < CM_MAX_DEV; devno++) {
  519. if (dev_table[devno] == link)
  520. break;
  521. }
  522. if (devno == CM_MAX_DEV)
  523. return;
  524. reader_release(link);
  525. dev_table[devno] = NULL;
  526. kfree(dev);
  527. device_destroy(cmx_class, MKDEV(major, devno));
  528. return;
  529. }
  530. static const struct file_operations reader_fops = {
  531. .owner = THIS_MODULE,
  532. .read = cm4040_read,
  533. .write = cm4040_write,
  534. .open = cm4040_open,
  535. .release = cm4040_close,
  536. .poll = cm4040_poll,
  537. };
  538. static struct pcmcia_device_id cm4040_ids[] = {
  539. PCMCIA_DEVICE_MANF_CARD(0x0223, 0x0200),
  540. PCMCIA_DEVICE_PROD_ID12("OMNIKEY", "CardMan 4040",
  541. 0xE32CDD8C, 0x8F23318B),
  542. PCMCIA_DEVICE_NULL,
  543. };
  544. MODULE_DEVICE_TABLE(pcmcia, cm4040_ids);
  545. static struct pcmcia_driver reader_driver = {
  546. .owner = THIS_MODULE,
  547. .drv = {
  548. .name = "cm4040_cs",
  549. },
  550. .probe = reader_probe,
  551. .remove = reader_detach,
  552. .id_table = cm4040_ids,
  553. };
  554. static int __init cm4040_init(void)
  555. {
  556. int rc;
  557. printk(KERN_INFO "%s\n", version);
  558. cmx_class = class_create(THIS_MODULE, "cardman_4040");
  559. if (IS_ERR(cmx_class))
  560. return PTR_ERR(cmx_class);
  561. major = register_chrdev(0, DEVICE_NAME, &reader_fops);
  562. if (major < 0) {
  563. printk(KERN_WARNING MODULE_NAME
  564. ": could not get major number\n");
  565. class_destroy(cmx_class);
  566. return major;
  567. }
  568. rc = pcmcia_register_driver(&reader_driver);
  569. if (rc < 0) {
  570. unregister_chrdev(major, DEVICE_NAME);
  571. class_destroy(cmx_class);
  572. return rc;
  573. }
  574. return 0;
  575. }
  576. static void __exit cm4040_exit(void)
  577. {
  578. printk(KERN_INFO MODULE_NAME ": unloading\n");
  579. pcmcia_unregister_driver(&reader_driver);
  580. unregister_chrdev(major, DEVICE_NAME);
  581. class_destroy(cmx_class);
  582. }
  583. module_init(cm4040_init);
  584. module_exit(cm4040_exit);
  585. MODULE_LICENSE("Dual BSD/GPL");