iwl3945-base.c 123 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/ieee80211_radiotap.h>
  46. #include <net/mac80211.h>
  47. #include <asm/div64.h>
  48. #define DRV_NAME "iwl3945"
  49. #include "iwl-fh.h"
  50. #include "iwl-3945-fh.h"
  51. #include "iwl-commands.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-3945.h"
  54. #include "iwl-core.h"
  55. #include "iwl-helpers.h"
  56. #include "iwl-dev.h"
  57. #include "iwl-spectrum.h"
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION \
  62. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  63. #ifdef CONFIG_IWLWIFI_DEBUG
  64. #define VD "d"
  65. #else
  66. #define VD
  67. #endif
  68. /*
  69. * add "s" to indicate spectrum measurement included.
  70. * we add it here to be consistent with previous releases in which
  71. * this was configurable.
  72. */
  73. #define DRV_VERSION IWLWIFI_VERSION VD "s"
  74. #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
  75. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  76. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  77. MODULE_VERSION(DRV_VERSION);
  78. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  79. MODULE_LICENSE("GPL");
  80. /* module parameters */
  81. struct iwl_mod_params iwl3945_mod_params = {
  82. .sw_crypto = 1,
  83. .restart_fw = 1,
  84. /* the rest are 0 by default */
  85. };
  86. /**
  87. * iwl3945_get_antenna_flags - Get antenna flags for RXON command
  88. * @priv: eeprom and antenna fields are used to determine antenna flags
  89. *
  90. * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
  91. * iwl3945_mod_params.antenna specifies the antenna diversity mode:
  92. *
  93. * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  94. * IWL_ANTENNA_MAIN - Force MAIN antenna
  95. * IWL_ANTENNA_AUX - Force AUX antenna
  96. */
  97. __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
  98. {
  99. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  100. switch (iwl3945_mod_params.antenna) {
  101. case IWL_ANTENNA_DIVERSITY:
  102. return 0;
  103. case IWL_ANTENNA_MAIN:
  104. if (eeprom->antenna_switch_type)
  105. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  106. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  107. case IWL_ANTENNA_AUX:
  108. if (eeprom->antenna_switch_type)
  109. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  110. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  111. }
  112. /* bad antenna selector value */
  113. IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
  114. iwl3945_mod_params.antenna);
  115. return 0; /* "diversity" is default if error */
  116. }
  117. static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
  118. struct ieee80211_key_conf *keyconf,
  119. u8 sta_id)
  120. {
  121. unsigned long flags;
  122. __le16 key_flags = 0;
  123. int ret;
  124. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  125. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  126. if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id)
  127. key_flags |= STA_KEY_MULTICAST_MSK;
  128. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  129. keyconf->hw_key_idx = keyconf->keyidx;
  130. key_flags &= ~STA_KEY_FLG_INVALID;
  131. spin_lock_irqsave(&priv->sta_lock, flags);
  132. priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  133. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  134. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  135. keyconf->keylen);
  136. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  137. keyconf->keylen);
  138. if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  139. == STA_KEY_FLG_NO_ENC)
  140. priv->stations[sta_id].sta.key.key_offset =
  141. iwl_get_free_ucode_key_index(priv);
  142. /* else, we are overriding an existing key => no need to allocated room
  143. * in uCode. */
  144. WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  145. "no space for a new key");
  146. priv->stations[sta_id].sta.key.key_flags = key_flags;
  147. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  148. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  149. IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
  150. ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  151. spin_unlock_irqrestore(&priv->sta_lock, flags);
  152. return ret;
  153. }
  154. static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
  155. struct ieee80211_key_conf *keyconf,
  156. u8 sta_id)
  157. {
  158. return -EOPNOTSUPP;
  159. }
  160. static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
  161. struct ieee80211_key_conf *keyconf,
  162. u8 sta_id)
  163. {
  164. return -EOPNOTSUPP;
  165. }
  166. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  167. {
  168. unsigned long flags;
  169. struct iwl_addsta_cmd sta_cmd;
  170. spin_lock_irqsave(&priv->sta_lock, flags);
  171. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
  172. memset(&priv->stations[sta_id].sta.key, 0,
  173. sizeof(struct iwl4965_keyinfo));
  174. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  175. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  176. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  177. memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
  178. spin_unlock_irqrestore(&priv->sta_lock, flags);
  179. IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
  180. return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
  181. }
  182. static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
  183. struct ieee80211_key_conf *keyconf, u8 sta_id)
  184. {
  185. int ret = 0;
  186. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  187. switch (keyconf->cipher) {
  188. case WLAN_CIPHER_SUITE_CCMP:
  189. ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
  190. break;
  191. case WLAN_CIPHER_SUITE_TKIP:
  192. ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
  193. break;
  194. case WLAN_CIPHER_SUITE_WEP40:
  195. case WLAN_CIPHER_SUITE_WEP104:
  196. ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
  197. break;
  198. default:
  199. IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__,
  200. keyconf->cipher);
  201. ret = -EINVAL;
  202. }
  203. IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
  204. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  205. sta_id, ret);
  206. return ret;
  207. }
  208. static int iwl3945_remove_static_key(struct iwl_priv *priv)
  209. {
  210. int ret = -EOPNOTSUPP;
  211. return ret;
  212. }
  213. static int iwl3945_set_static_key(struct iwl_priv *priv,
  214. struct ieee80211_key_conf *key)
  215. {
  216. if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  217. key->cipher == WLAN_CIPHER_SUITE_WEP104)
  218. return -EOPNOTSUPP;
  219. IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher);
  220. return -EINVAL;
  221. }
  222. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  223. {
  224. struct list_head *element;
  225. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  226. priv->frames_count);
  227. while (!list_empty(&priv->free_frames)) {
  228. element = priv->free_frames.next;
  229. list_del(element);
  230. kfree(list_entry(element, struct iwl3945_frame, list));
  231. priv->frames_count--;
  232. }
  233. if (priv->frames_count) {
  234. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  235. priv->frames_count);
  236. priv->frames_count = 0;
  237. }
  238. }
  239. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  240. {
  241. struct iwl3945_frame *frame;
  242. struct list_head *element;
  243. if (list_empty(&priv->free_frames)) {
  244. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  245. if (!frame) {
  246. IWL_ERR(priv, "Could not allocate frame!\n");
  247. return NULL;
  248. }
  249. priv->frames_count++;
  250. return frame;
  251. }
  252. element = priv->free_frames.next;
  253. list_del(element);
  254. return list_entry(element, struct iwl3945_frame, list);
  255. }
  256. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  257. {
  258. memset(frame, 0, sizeof(*frame));
  259. list_add(&frame->list, &priv->free_frames);
  260. }
  261. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  262. struct ieee80211_hdr *hdr,
  263. int left)
  264. {
  265. if (!iwl_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->ibss_beacon)
  266. return 0;
  267. if (priv->ibss_beacon->len > left)
  268. return 0;
  269. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  270. return priv->ibss_beacon->len;
  271. }
  272. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  273. {
  274. struct iwl3945_frame *frame;
  275. unsigned int frame_size;
  276. int rc;
  277. u8 rate;
  278. frame = iwl3945_get_free_frame(priv);
  279. if (!frame) {
  280. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  281. "command.\n");
  282. return -ENOMEM;
  283. }
  284. rate = iwl_rate_get_lowest_plcp(priv);
  285. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  286. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  287. &frame->u.cmd[0]);
  288. iwl3945_free_frame(priv, frame);
  289. return rc;
  290. }
  291. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  292. {
  293. if (priv->_3945.shared_virt)
  294. dma_free_coherent(&priv->pci_dev->dev,
  295. sizeof(struct iwl3945_shared),
  296. priv->_3945.shared_virt,
  297. priv->_3945.shared_phys);
  298. }
  299. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  300. struct ieee80211_tx_info *info,
  301. struct iwl_device_cmd *cmd,
  302. struct sk_buff *skb_frag,
  303. int sta_id)
  304. {
  305. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  306. struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
  307. tx_cmd->sec_ctl = 0;
  308. switch (keyinfo->cipher) {
  309. case WLAN_CIPHER_SUITE_CCMP:
  310. tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
  311. memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
  312. IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
  313. break;
  314. case WLAN_CIPHER_SUITE_TKIP:
  315. break;
  316. case WLAN_CIPHER_SUITE_WEP104:
  317. tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
  318. /* fall through */
  319. case WLAN_CIPHER_SUITE_WEP40:
  320. tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
  321. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  322. memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
  323. IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
  324. "with key %d\n", info->control.hw_key->hw_key_idx);
  325. break;
  326. default:
  327. IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher);
  328. break;
  329. }
  330. }
  331. /*
  332. * handle build REPLY_TX command notification.
  333. */
  334. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  335. struct iwl_device_cmd *cmd,
  336. struct ieee80211_tx_info *info,
  337. struct ieee80211_hdr *hdr, u8 std_id)
  338. {
  339. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  340. __le32 tx_flags = tx_cmd->tx_flags;
  341. __le16 fc = hdr->frame_control;
  342. tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  343. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  344. tx_flags |= TX_CMD_FLG_ACK_MSK;
  345. if (ieee80211_is_mgmt(fc))
  346. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  347. if (ieee80211_is_probe_resp(fc) &&
  348. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  349. tx_flags |= TX_CMD_FLG_TSF_MSK;
  350. } else {
  351. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  352. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  353. }
  354. tx_cmd->sta_id = std_id;
  355. if (ieee80211_has_morefrags(fc))
  356. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  357. if (ieee80211_is_data_qos(fc)) {
  358. u8 *qc = ieee80211_get_qos_ctl(hdr);
  359. tx_cmd->tid_tspec = qc[0] & 0xf;
  360. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  361. } else {
  362. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  363. }
  364. priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
  365. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  366. if (ieee80211_is_mgmt(fc)) {
  367. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  368. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
  369. else
  370. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
  371. } else {
  372. tx_cmd->timeout.pm_frame_timeout = 0;
  373. }
  374. tx_cmd->driver_txop = 0;
  375. tx_cmd->tx_flags = tx_flags;
  376. tx_cmd->next_frame_len = 0;
  377. }
  378. /*
  379. * start REPLY_TX command process
  380. */
  381. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  382. {
  383. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  384. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  385. struct iwl3945_tx_cmd *tx_cmd;
  386. struct iwl_tx_queue *txq = NULL;
  387. struct iwl_queue *q = NULL;
  388. struct iwl_device_cmd *out_cmd;
  389. struct iwl_cmd_meta *out_meta;
  390. dma_addr_t phys_addr;
  391. dma_addr_t txcmd_phys;
  392. int txq_id = skb_get_queue_mapping(skb);
  393. u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
  394. u8 id;
  395. u8 unicast;
  396. u8 sta_id;
  397. u8 tid = 0;
  398. __le16 fc;
  399. u8 wait_write_ptr = 0;
  400. unsigned long flags;
  401. spin_lock_irqsave(&priv->lock, flags);
  402. if (iwl_is_rfkill(priv)) {
  403. IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
  404. goto drop_unlock;
  405. }
  406. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  407. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  408. goto drop_unlock;
  409. }
  410. unicast = !is_multicast_ether_addr(hdr->addr1);
  411. id = 0;
  412. fc = hdr->frame_control;
  413. #ifdef CONFIG_IWLWIFI_DEBUG
  414. if (ieee80211_is_auth(fc))
  415. IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
  416. else if (ieee80211_is_assoc_req(fc))
  417. IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
  418. else if (ieee80211_is_reassoc_req(fc))
  419. IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
  420. #endif
  421. spin_unlock_irqrestore(&priv->lock, flags);
  422. hdr_len = ieee80211_hdrlen(fc);
  423. /* Find index into station table for destination station */
  424. sta_id = iwl_sta_id_or_broadcast(
  425. priv, &priv->contexts[IWL_RXON_CTX_BSS],
  426. info->control.sta);
  427. if (sta_id == IWL_INVALID_STATION) {
  428. IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
  429. hdr->addr1);
  430. goto drop;
  431. }
  432. IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
  433. if (ieee80211_is_data_qos(fc)) {
  434. u8 *qc = ieee80211_get_qos_ctl(hdr);
  435. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  436. if (unlikely(tid >= MAX_TID_COUNT))
  437. goto drop;
  438. }
  439. /* Descriptor for chosen Tx queue */
  440. txq = &priv->txq[txq_id];
  441. q = &txq->q;
  442. if ((iwl_queue_space(q) < q->high_mark))
  443. goto drop;
  444. spin_lock_irqsave(&priv->lock, flags);
  445. idx = get_cmd_index(q, q->write_ptr, 0);
  446. /* Set up driver data for this TFD */
  447. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  448. txq->txb[q->write_ptr].skb = skb;
  449. txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  450. /* Init first empty entry in queue's array of Tx/cmd buffers */
  451. out_cmd = txq->cmd[idx];
  452. out_meta = &txq->meta[idx];
  453. tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  454. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  455. memset(tx_cmd, 0, sizeof(*tx_cmd));
  456. /*
  457. * Set up the Tx-command (not MAC!) header.
  458. * Store the chosen Tx queue and TFD index within the sequence field;
  459. * after Tx, uCode's Tx response will return this value so driver can
  460. * locate the frame within the tx queue and do post-tx processing.
  461. */
  462. out_cmd->hdr.cmd = REPLY_TX;
  463. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  464. INDEX_TO_SEQ(q->write_ptr)));
  465. /* Copy MAC header from skb into command buffer */
  466. memcpy(tx_cmd->hdr, hdr, hdr_len);
  467. if (info->control.hw_key)
  468. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
  469. /* TODO need this for burst mode later on */
  470. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  471. /* set is_hcca to 0; it probably will never be implemented */
  472. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  473. /* Total # bytes to be transmitted */
  474. len = (u16)skb->len;
  475. tx_cmd->len = cpu_to_le16(len);
  476. iwl_dbg_log_tx_data_frame(priv, len, hdr);
  477. iwl_update_stats(priv, true, fc, len);
  478. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  479. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  480. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  481. txq->need_update = 1;
  482. } else {
  483. wait_write_ptr = 1;
  484. txq->need_update = 0;
  485. }
  486. IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
  487. le16_to_cpu(out_cmd->hdr.sequence));
  488. IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
  489. iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
  490. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
  491. ieee80211_hdrlen(fc));
  492. /*
  493. * Use the first empty entry in this queue's command buffer array
  494. * to contain the Tx command and MAC header concatenated together
  495. * (payload data will be in another buffer).
  496. * Size of this varies, due to varying MAC header length.
  497. * If end is not dword aligned, we'll have 2 extra bytes at the end
  498. * of the MAC header (device reads on dword boundaries).
  499. * We'll tell device about this padding later.
  500. */
  501. len = sizeof(struct iwl3945_tx_cmd) +
  502. sizeof(struct iwl_cmd_header) + hdr_len;
  503. len_org = len;
  504. len = (len + 3) & ~3;
  505. if (len_org != len)
  506. len_org = 1;
  507. else
  508. len_org = 0;
  509. /* Physical address of this Tx command's header (not MAC header!),
  510. * within command buffer array. */
  511. txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  512. len, PCI_DMA_TODEVICE);
  513. /* we do not map meta data ... so we can safely access address to
  514. * provide to unmap command*/
  515. dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
  516. dma_unmap_len_set(out_meta, len, len);
  517. /* Add buffer containing Tx command and MAC(!) header to TFD's
  518. * first entry */
  519. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  520. txcmd_phys, len, 1, 0);
  521. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  522. * if any (802.11 null frames have no payload). */
  523. len = skb->len - hdr_len;
  524. if (len) {
  525. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  526. len, PCI_DMA_TODEVICE);
  527. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  528. phys_addr, len,
  529. 0, U32_PAD(len));
  530. }
  531. /* Tell device the write index *just past* this latest filled TFD */
  532. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  533. iwl_txq_update_write_ptr(priv, txq);
  534. spin_unlock_irqrestore(&priv->lock, flags);
  535. if ((iwl_queue_space(q) < q->high_mark)
  536. && priv->mac80211_registered) {
  537. if (wait_write_ptr) {
  538. spin_lock_irqsave(&priv->lock, flags);
  539. txq->need_update = 1;
  540. iwl_txq_update_write_ptr(priv, txq);
  541. spin_unlock_irqrestore(&priv->lock, flags);
  542. }
  543. iwl_stop_queue(priv, skb_get_queue_mapping(skb));
  544. }
  545. return 0;
  546. drop_unlock:
  547. spin_unlock_irqrestore(&priv->lock, flags);
  548. drop:
  549. return -1;
  550. }
  551. static int iwl3945_get_measurement(struct iwl_priv *priv,
  552. struct ieee80211_measurement_params *params,
  553. u8 type)
  554. {
  555. struct iwl_spectrum_cmd spectrum;
  556. struct iwl_rx_packet *pkt;
  557. struct iwl_host_cmd cmd = {
  558. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  559. .data = (void *)&spectrum,
  560. .flags = CMD_WANT_SKB,
  561. };
  562. u32 add_time = le64_to_cpu(params->start_time);
  563. int rc;
  564. int spectrum_resp_status;
  565. int duration = le16_to_cpu(params->duration);
  566. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  567. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  568. add_time = iwl_usecs_to_beacons(priv,
  569. le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
  570. le16_to_cpu(ctx->timing.beacon_interval));
  571. memset(&spectrum, 0, sizeof(spectrum));
  572. spectrum.channel_count = cpu_to_le16(1);
  573. spectrum.flags =
  574. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  575. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  576. cmd.len = sizeof(spectrum);
  577. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  578. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  579. spectrum.start_time =
  580. iwl_add_beacon_time(priv,
  581. priv->_3945.last_beacon_time, add_time,
  582. le16_to_cpu(ctx->timing.beacon_interval));
  583. else
  584. spectrum.start_time = 0;
  585. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  586. spectrum.channels[0].channel = params->channel;
  587. spectrum.channels[0].type = type;
  588. if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
  589. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  590. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  591. rc = iwl_send_cmd_sync(priv, &cmd);
  592. if (rc)
  593. return rc;
  594. pkt = (struct iwl_rx_packet *)cmd.reply_page;
  595. if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
  596. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  597. rc = -EIO;
  598. }
  599. spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
  600. switch (spectrum_resp_status) {
  601. case 0: /* Command will be handled */
  602. if (pkt->u.spectrum.id != 0xff) {
  603. IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
  604. pkt->u.spectrum.id);
  605. priv->measurement_status &= ~MEASUREMENT_READY;
  606. }
  607. priv->measurement_status |= MEASUREMENT_ACTIVE;
  608. rc = 0;
  609. break;
  610. case 1: /* Command will not be handled */
  611. rc = -EAGAIN;
  612. break;
  613. }
  614. iwl_free_pages(priv, cmd.reply_page);
  615. return rc;
  616. }
  617. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  618. struct iwl_rx_mem_buffer *rxb)
  619. {
  620. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  621. struct iwl_alive_resp *palive;
  622. struct delayed_work *pwork;
  623. palive = &pkt->u.alive_frame;
  624. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  625. "0x%01X 0x%01X\n",
  626. palive->is_valid, palive->ver_type,
  627. palive->ver_subtype);
  628. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  629. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  630. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  631. sizeof(struct iwl_alive_resp));
  632. pwork = &priv->init_alive_start;
  633. } else {
  634. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  635. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  636. sizeof(struct iwl_alive_resp));
  637. pwork = &priv->alive_start;
  638. iwl3945_disable_events(priv);
  639. }
  640. /* We delay the ALIVE response by 5ms to
  641. * give the HW RF Kill time to activate... */
  642. if (palive->is_valid == UCODE_VALID_OK)
  643. queue_delayed_work(priv->workqueue, pwork,
  644. msecs_to_jiffies(5));
  645. else
  646. IWL_WARN(priv, "uCode did not respond OK.\n");
  647. }
  648. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  649. struct iwl_rx_mem_buffer *rxb)
  650. {
  651. #ifdef CONFIG_IWLWIFI_DEBUG
  652. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  653. #endif
  654. IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  655. }
  656. static void iwl3945_bg_beacon_update(struct work_struct *work)
  657. {
  658. struct iwl_priv *priv =
  659. container_of(work, struct iwl_priv, beacon_update);
  660. struct sk_buff *beacon;
  661. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  662. beacon = ieee80211_beacon_get(priv->hw,
  663. priv->contexts[IWL_RXON_CTX_BSS].vif);
  664. if (!beacon) {
  665. IWL_ERR(priv, "update beacon failed\n");
  666. return;
  667. }
  668. mutex_lock(&priv->mutex);
  669. /* new beacon skb is allocated every time; dispose previous.*/
  670. if (priv->ibss_beacon)
  671. dev_kfree_skb(priv->ibss_beacon);
  672. priv->ibss_beacon = beacon;
  673. mutex_unlock(&priv->mutex);
  674. iwl3945_send_beacon_cmd(priv);
  675. }
  676. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  677. struct iwl_rx_mem_buffer *rxb)
  678. {
  679. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  680. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  681. #ifdef CONFIG_IWLWIFI_DEBUG
  682. u8 rate = beacon->beacon_notify_hdr.rate;
  683. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  684. "tsf %d %d rate %d\n",
  685. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  686. beacon->beacon_notify_hdr.failure_frame,
  687. le32_to_cpu(beacon->ibss_mgr_status),
  688. le32_to_cpu(beacon->high_tsf),
  689. le32_to_cpu(beacon->low_tsf), rate);
  690. #endif
  691. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  692. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  693. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  694. queue_work(priv->workqueue, &priv->beacon_update);
  695. }
  696. /* Handle notification from uCode that card's power state is changing
  697. * due to software, hardware, or critical temperature RFKILL */
  698. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  699. struct iwl_rx_mem_buffer *rxb)
  700. {
  701. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  702. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  703. unsigned long status = priv->status;
  704. IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
  705. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  706. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  707. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  708. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  709. if (flags & HW_CARD_DISABLED)
  710. set_bit(STATUS_RF_KILL_HW, &priv->status);
  711. else
  712. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  713. iwl_scan_cancel(priv);
  714. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  715. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  716. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  717. test_bit(STATUS_RF_KILL_HW, &priv->status));
  718. else
  719. wake_up_interruptible(&priv->wait_command_queue);
  720. }
  721. /**
  722. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  723. *
  724. * Setup the RX handlers for each of the reply types sent from the uCode
  725. * to the host.
  726. *
  727. * This function chains into the hardware specific files for them to setup
  728. * any hardware specific handlers as well.
  729. */
  730. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  731. {
  732. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  733. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  734. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  735. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  736. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  737. iwl_rx_spectrum_measure_notif;
  738. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  739. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  740. iwl_rx_pm_debug_statistics_notif;
  741. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  742. /*
  743. * The same handler is used for both the REPLY to a discrete
  744. * statistics request from the host as well as for the periodic
  745. * statistics notifications (after received beacons) from the uCode.
  746. */
  747. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
  748. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  749. iwl_setup_rx_scan_handlers(priv);
  750. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  751. /* Set up hardware specific Rx handlers */
  752. iwl3945_hw_rx_handler_setup(priv);
  753. }
  754. /************************** RX-FUNCTIONS ****************************/
  755. /*
  756. * Rx theory of operation
  757. *
  758. * The host allocates 32 DMA target addresses and passes the host address
  759. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  760. * 0 to 31
  761. *
  762. * Rx Queue Indexes
  763. * The host/firmware share two index registers for managing the Rx buffers.
  764. *
  765. * The READ index maps to the first position that the firmware may be writing
  766. * to -- the driver can read up to (but not including) this position and get
  767. * good data.
  768. * The READ index is managed by the firmware once the card is enabled.
  769. *
  770. * The WRITE index maps to the last position the driver has read from -- the
  771. * position preceding WRITE is the last slot the firmware can place a packet.
  772. *
  773. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  774. * WRITE = READ.
  775. *
  776. * During initialization, the host sets up the READ queue position to the first
  777. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  778. *
  779. * When the firmware places a packet in a buffer, it will advance the READ index
  780. * and fire the RX interrupt. The driver can then query the READ index and
  781. * process as many packets as possible, moving the WRITE index forward as it
  782. * resets the Rx queue buffers with new memory.
  783. *
  784. * The management in the driver is as follows:
  785. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  786. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  787. * to replenish the iwl->rxq->rx_free.
  788. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  789. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  790. * 'processed' and 'read' driver indexes as well)
  791. * + A received packet is processed and handed to the kernel network stack,
  792. * detached from the iwl->rxq. The driver 'processed' index is updated.
  793. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  794. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  795. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  796. * were enough free buffers and RX_STALLED is set it is cleared.
  797. *
  798. *
  799. * Driver sequence:
  800. *
  801. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  802. * iwl3945_rx_queue_restock
  803. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  804. * queue, updates firmware pointers, and updates
  805. * the WRITE index. If insufficient rx_free buffers
  806. * are available, schedules iwl3945_rx_replenish
  807. *
  808. * -- enable interrupts --
  809. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  810. * READ INDEX, detaching the SKB from the pool.
  811. * Moves the packet buffer from queue to rx_used.
  812. * Calls iwl3945_rx_queue_restock to refill any empty
  813. * slots.
  814. * ...
  815. *
  816. */
  817. /**
  818. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  819. */
  820. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  821. dma_addr_t dma_addr)
  822. {
  823. return cpu_to_le32((u32)dma_addr);
  824. }
  825. /**
  826. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  827. *
  828. * If there are slots in the RX queue that need to be restocked,
  829. * and we have free pre-allocated buffers, fill the ranks as much
  830. * as we can, pulling from rx_free.
  831. *
  832. * This moves the 'write' index forward to catch up with 'processed', and
  833. * also updates the memory address in the firmware to reference the new
  834. * target buffer.
  835. */
  836. static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
  837. {
  838. struct iwl_rx_queue *rxq = &priv->rxq;
  839. struct list_head *element;
  840. struct iwl_rx_mem_buffer *rxb;
  841. unsigned long flags;
  842. int write;
  843. spin_lock_irqsave(&rxq->lock, flags);
  844. write = rxq->write & ~0x7;
  845. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  846. /* Get next free Rx buffer, remove from free list */
  847. element = rxq->rx_free.next;
  848. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  849. list_del(element);
  850. /* Point to Rx buffer via next RBD in circular buffer */
  851. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
  852. rxq->queue[rxq->write] = rxb;
  853. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  854. rxq->free_count--;
  855. }
  856. spin_unlock_irqrestore(&rxq->lock, flags);
  857. /* If the pre-allocated buffer pool is dropping low, schedule to
  858. * refill it */
  859. if (rxq->free_count <= RX_LOW_WATERMARK)
  860. queue_work(priv->workqueue, &priv->rx_replenish);
  861. /* If we've added more space for the firmware to place data, tell it.
  862. * Increment device's write pointer in multiples of 8. */
  863. if ((rxq->write_actual != (rxq->write & ~0x7))
  864. || (abs(rxq->write - rxq->read) > 7)) {
  865. spin_lock_irqsave(&rxq->lock, flags);
  866. rxq->need_update = 1;
  867. spin_unlock_irqrestore(&rxq->lock, flags);
  868. iwl_rx_queue_update_write_ptr(priv, rxq);
  869. }
  870. }
  871. /**
  872. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  873. *
  874. * When moving to rx_free an SKB is allocated for the slot.
  875. *
  876. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  877. * This is called as a scheduled work item (except for during initialization)
  878. */
  879. static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  880. {
  881. struct iwl_rx_queue *rxq = &priv->rxq;
  882. struct list_head *element;
  883. struct iwl_rx_mem_buffer *rxb;
  884. struct page *page;
  885. unsigned long flags;
  886. gfp_t gfp_mask = priority;
  887. while (1) {
  888. spin_lock_irqsave(&rxq->lock, flags);
  889. if (list_empty(&rxq->rx_used)) {
  890. spin_unlock_irqrestore(&rxq->lock, flags);
  891. return;
  892. }
  893. spin_unlock_irqrestore(&rxq->lock, flags);
  894. if (rxq->free_count > RX_LOW_WATERMARK)
  895. gfp_mask |= __GFP_NOWARN;
  896. if (priv->hw_params.rx_page_order > 0)
  897. gfp_mask |= __GFP_COMP;
  898. /* Alloc a new receive buffer */
  899. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  900. if (!page) {
  901. if (net_ratelimit())
  902. IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
  903. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  904. net_ratelimit())
  905. IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
  906. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  907. rxq->free_count);
  908. /* We don't reschedule replenish work here -- we will
  909. * call the restock method and if it still needs
  910. * more buffers it will schedule replenish */
  911. break;
  912. }
  913. spin_lock_irqsave(&rxq->lock, flags);
  914. if (list_empty(&rxq->rx_used)) {
  915. spin_unlock_irqrestore(&rxq->lock, flags);
  916. __free_pages(page, priv->hw_params.rx_page_order);
  917. return;
  918. }
  919. element = rxq->rx_used.next;
  920. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  921. list_del(element);
  922. spin_unlock_irqrestore(&rxq->lock, flags);
  923. rxb->page = page;
  924. /* Get physical address of RB/SKB */
  925. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  926. PAGE_SIZE << priv->hw_params.rx_page_order,
  927. PCI_DMA_FROMDEVICE);
  928. spin_lock_irqsave(&rxq->lock, flags);
  929. list_add_tail(&rxb->list, &rxq->rx_free);
  930. rxq->free_count++;
  931. priv->alloc_rxb_page++;
  932. spin_unlock_irqrestore(&rxq->lock, flags);
  933. }
  934. }
  935. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  936. {
  937. unsigned long flags;
  938. int i;
  939. spin_lock_irqsave(&rxq->lock, flags);
  940. INIT_LIST_HEAD(&rxq->rx_free);
  941. INIT_LIST_HEAD(&rxq->rx_used);
  942. /* Fill the rx_used queue with _all_ of the Rx buffers */
  943. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  944. /* In the reset function, these buffers may have been allocated
  945. * to an SKB, so we need to unmap and free potential storage */
  946. if (rxq->pool[i].page != NULL) {
  947. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  948. PAGE_SIZE << priv->hw_params.rx_page_order,
  949. PCI_DMA_FROMDEVICE);
  950. __iwl_free_pages(priv, rxq->pool[i].page);
  951. rxq->pool[i].page = NULL;
  952. }
  953. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  954. }
  955. /* Set us so that we have processed and used all buffers, but have
  956. * not restocked the Rx queue with fresh buffers */
  957. rxq->read = rxq->write = 0;
  958. rxq->write_actual = 0;
  959. rxq->free_count = 0;
  960. spin_unlock_irqrestore(&rxq->lock, flags);
  961. }
  962. void iwl3945_rx_replenish(void *data)
  963. {
  964. struct iwl_priv *priv = data;
  965. unsigned long flags;
  966. iwl3945_rx_allocate(priv, GFP_KERNEL);
  967. spin_lock_irqsave(&priv->lock, flags);
  968. iwl3945_rx_queue_restock(priv);
  969. spin_unlock_irqrestore(&priv->lock, flags);
  970. }
  971. static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
  972. {
  973. iwl3945_rx_allocate(priv, GFP_ATOMIC);
  974. iwl3945_rx_queue_restock(priv);
  975. }
  976. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  977. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  978. * This free routine walks the list of POOL entries and if SKB is set to
  979. * non NULL it is unmapped and freed
  980. */
  981. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  982. {
  983. int i;
  984. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  985. if (rxq->pool[i].page != NULL) {
  986. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  987. PAGE_SIZE << priv->hw_params.rx_page_order,
  988. PCI_DMA_FROMDEVICE);
  989. __iwl_free_pages(priv, rxq->pool[i].page);
  990. rxq->pool[i].page = NULL;
  991. }
  992. }
  993. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  994. rxq->bd_dma);
  995. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  996. rxq->rb_stts, rxq->rb_stts_dma);
  997. rxq->bd = NULL;
  998. rxq->rb_stts = NULL;
  999. }
  1000. /* Convert linear signal-to-noise ratio into dB */
  1001. static u8 ratio2dB[100] = {
  1002. /* 0 1 2 3 4 5 6 7 8 9 */
  1003. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  1004. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  1005. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  1006. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  1007. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  1008. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  1009. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  1010. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  1011. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  1012. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  1013. };
  1014. /* Calculates a relative dB value from a ratio of linear
  1015. * (i.e. not dB) signal levels.
  1016. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  1017. int iwl3945_calc_db_from_ratio(int sig_ratio)
  1018. {
  1019. /* 1000:1 or higher just report as 60 dB */
  1020. if (sig_ratio >= 1000)
  1021. return 60;
  1022. /* 100:1 or higher, divide by 10 and use table,
  1023. * add 20 dB to make up for divide by 10 */
  1024. if (sig_ratio >= 100)
  1025. return 20 + (int)ratio2dB[sig_ratio/10];
  1026. /* We shouldn't see this */
  1027. if (sig_ratio < 1)
  1028. return 0;
  1029. /* Use table for ratios 1:1 - 99:1 */
  1030. return (int)ratio2dB[sig_ratio];
  1031. }
  1032. /**
  1033. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  1034. *
  1035. * Uses the priv->rx_handlers callback function array to invoke
  1036. * the appropriate handlers, including command responses,
  1037. * frame-received notifications, and other notifications.
  1038. */
  1039. static void iwl3945_rx_handle(struct iwl_priv *priv)
  1040. {
  1041. struct iwl_rx_mem_buffer *rxb;
  1042. struct iwl_rx_packet *pkt;
  1043. struct iwl_rx_queue *rxq = &priv->rxq;
  1044. u32 r, i;
  1045. int reclaim;
  1046. unsigned long flags;
  1047. u8 fill_rx = 0;
  1048. u32 count = 8;
  1049. int total_empty = 0;
  1050. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  1051. * buffer that the driver may process (last buffer filled by ucode). */
  1052. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1053. i = rxq->read;
  1054. /* calculate total frames need to be restock after handling RX */
  1055. total_empty = r - rxq->write_actual;
  1056. if (total_empty < 0)
  1057. total_empty += RX_QUEUE_SIZE;
  1058. if (total_empty > (RX_QUEUE_SIZE / 2))
  1059. fill_rx = 1;
  1060. /* Rx interrupt, but nothing sent from uCode */
  1061. if (i == r)
  1062. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  1063. while (i != r) {
  1064. int len;
  1065. rxb = rxq->queue[i];
  1066. /* If an RXB doesn't have a Rx queue slot associated with it,
  1067. * then a bug has been introduced in the queue refilling
  1068. * routines -- catch it here */
  1069. BUG_ON(rxb == NULL);
  1070. rxq->queue[i] = NULL;
  1071. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  1072. PAGE_SIZE << priv->hw_params.rx_page_order,
  1073. PCI_DMA_FROMDEVICE);
  1074. pkt = rxb_addr(rxb);
  1075. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1076. len += sizeof(u32); /* account for status word */
  1077. trace_iwlwifi_dev_rx(priv, pkt, len);
  1078. /* Reclaim a command buffer only if this packet is a response
  1079. * to a (driver-originated) command.
  1080. * If the packet (e.g. Rx frame) originated from uCode,
  1081. * there is no command buffer to reclaim.
  1082. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1083. * but apparently a few don't get set; catch them here. */
  1084. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1085. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  1086. (pkt->hdr.cmd != REPLY_TX);
  1087. /* Based on type of command response or notification,
  1088. * handle those that need handling via function in
  1089. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  1090. if (priv->rx_handlers[pkt->hdr.cmd]) {
  1091. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
  1092. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  1093. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1094. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  1095. } else {
  1096. /* No handling needed */
  1097. IWL_DEBUG_RX(priv,
  1098. "r %d i %d No handler needed for %s, 0x%02x\n",
  1099. r, i, get_cmd_string(pkt->hdr.cmd),
  1100. pkt->hdr.cmd);
  1101. }
  1102. /*
  1103. * XXX: After here, we should always check rxb->page
  1104. * against NULL before touching it or its virtual
  1105. * memory (pkt). Because some rx_handler might have
  1106. * already taken or freed the pages.
  1107. */
  1108. if (reclaim) {
  1109. /* Invoke any callbacks, transfer the buffer to caller,
  1110. * and fire off the (possibly) blocking iwl_send_cmd()
  1111. * as we reclaim the driver command queue */
  1112. if (rxb->page)
  1113. iwl_tx_cmd_complete(priv, rxb);
  1114. else
  1115. IWL_WARN(priv, "Claim null rxb?\n");
  1116. }
  1117. /* Reuse the page if possible. For notification packets and
  1118. * SKBs that fail to Rx correctly, add them back into the
  1119. * rx_free list for reuse later. */
  1120. spin_lock_irqsave(&rxq->lock, flags);
  1121. if (rxb->page != NULL) {
  1122. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  1123. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  1124. PCI_DMA_FROMDEVICE);
  1125. list_add_tail(&rxb->list, &rxq->rx_free);
  1126. rxq->free_count++;
  1127. } else
  1128. list_add_tail(&rxb->list, &rxq->rx_used);
  1129. spin_unlock_irqrestore(&rxq->lock, flags);
  1130. i = (i + 1) & RX_QUEUE_MASK;
  1131. /* If there are a lot of unused frames,
  1132. * restock the Rx queue so ucode won't assert. */
  1133. if (fill_rx) {
  1134. count++;
  1135. if (count >= 8) {
  1136. rxq->read = i;
  1137. iwl3945_rx_replenish_now(priv);
  1138. count = 0;
  1139. }
  1140. }
  1141. }
  1142. /* Backtrack one entry */
  1143. rxq->read = i;
  1144. if (fill_rx)
  1145. iwl3945_rx_replenish_now(priv);
  1146. else
  1147. iwl3945_rx_queue_restock(priv);
  1148. }
  1149. /* call this function to flush any scheduled tasklet */
  1150. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  1151. {
  1152. /* wait to make sure we flush pending tasklet*/
  1153. synchronize_irq(priv->pci_dev->irq);
  1154. tasklet_kill(&priv->irq_tasklet);
  1155. }
  1156. static const char *desc_lookup(int i)
  1157. {
  1158. switch (i) {
  1159. case 1:
  1160. return "FAIL";
  1161. case 2:
  1162. return "BAD_PARAM";
  1163. case 3:
  1164. return "BAD_CHECKSUM";
  1165. case 4:
  1166. return "NMI_INTERRUPT";
  1167. case 5:
  1168. return "SYSASSERT";
  1169. case 6:
  1170. return "FATAL_ERROR";
  1171. }
  1172. return "UNKNOWN";
  1173. }
  1174. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1175. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1176. void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  1177. {
  1178. u32 i;
  1179. u32 desc, time, count, base, data1;
  1180. u32 blink1, blink2, ilink1, ilink2;
  1181. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1182. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1183. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1184. return;
  1185. }
  1186. count = iwl_read_targ_mem(priv, base);
  1187. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1188. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1189. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1190. priv->status, count);
  1191. }
  1192. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  1193. "ilink1 nmiPC Line\n");
  1194. for (i = ERROR_START_OFFSET;
  1195. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  1196. i += ERROR_ELEM_SIZE) {
  1197. desc = iwl_read_targ_mem(priv, base + i);
  1198. time =
  1199. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  1200. blink1 =
  1201. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  1202. blink2 =
  1203. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  1204. ilink1 =
  1205. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  1206. ilink2 =
  1207. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  1208. data1 =
  1209. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  1210. IWL_ERR(priv,
  1211. "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  1212. desc_lookup(desc), desc, time, blink1, blink2,
  1213. ilink1, ilink2, data1);
  1214. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
  1215. 0, blink1, blink2, ilink1, ilink2);
  1216. }
  1217. }
  1218. #define EVENT_START_OFFSET (6 * sizeof(u32))
  1219. /**
  1220. * iwl3945_print_event_log - Dump error event log to syslog
  1221. *
  1222. */
  1223. static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1224. u32 num_events, u32 mode,
  1225. int pos, char **buf, size_t bufsz)
  1226. {
  1227. u32 i;
  1228. u32 base; /* SRAM byte address of event log header */
  1229. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1230. u32 ptr; /* SRAM byte address of log data */
  1231. u32 ev, time, data; /* event log data */
  1232. unsigned long reg_flags;
  1233. if (num_events == 0)
  1234. return pos;
  1235. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1236. if (mode == 0)
  1237. event_size = 2 * sizeof(u32);
  1238. else
  1239. event_size = 3 * sizeof(u32);
  1240. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1241. /* Make sure device is powered up for SRAM reads */
  1242. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1243. iwl_grab_nic_access(priv);
  1244. /* Set starting address; reads will auto-increment */
  1245. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1246. rmb();
  1247. /* "time" is actually "data" for mode 0 (no timestamp).
  1248. * place event id # at far right for easier visual parsing. */
  1249. for (i = 0; i < num_events; i++) {
  1250. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1251. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1252. if (mode == 0) {
  1253. /* data, ev */
  1254. if (bufsz) {
  1255. pos += scnprintf(*buf + pos, bufsz - pos,
  1256. "0x%08x:%04u\n",
  1257. time, ev);
  1258. } else {
  1259. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  1260. trace_iwlwifi_dev_ucode_event(priv, 0,
  1261. time, ev);
  1262. }
  1263. } else {
  1264. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1265. if (bufsz) {
  1266. pos += scnprintf(*buf + pos, bufsz - pos,
  1267. "%010u:0x%08x:%04u\n",
  1268. time, data, ev);
  1269. } else {
  1270. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
  1271. time, data, ev);
  1272. trace_iwlwifi_dev_ucode_event(priv, time,
  1273. data, ev);
  1274. }
  1275. }
  1276. }
  1277. /* Allow device to power down */
  1278. iwl_release_nic_access(priv);
  1279. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1280. return pos;
  1281. }
  1282. /**
  1283. * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
  1284. */
  1285. static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1286. u32 num_wraps, u32 next_entry,
  1287. u32 size, u32 mode,
  1288. int pos, char **buf, size_t bufsz)
  1289. {
  1290. /*
  1291. * display the newest DEFAULT_LOG_ENTRIES entries
  1292. * i.e the entries just before the next ont that uCode would fill.
  1293. */
  1294. if (num_wraps) {
  1295. if (next_entry < size) {
  1296. pos = iwl3945_print_event_log(priv,
  1297. capacity - (size - next_entry),
  1298. size - next_entry, mode,
  1299. pos, buf, bufsz);
  1300. pos = iwl3945_print_event_log(priv, 0,
  1301. next_entry, mode,
  1302. pos, buf, bufsz);
  1303. } else
  1304. pos = iwl3945_print_event_log(priv, next_entry - size,
  1305. size, mode,
  1306. pos, buf, bufsz);
  1307. } else {
  1308. if (next_entry < size)
  1309. pos = iwl3945_print_event_log(priv, 0,
  1310. next_entry, mode,
  1311. pos, buf, bufsz);
  1312. else
  1313. pos = iwl3945_print_event_log(priv, next_entry - size,
  1314. size, mode,
  1315. pos, buf, bufsz);
  1316. }
  1317. return pos;
  1318. }
  1319. #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
  1320. int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1321. char **buf, bool display)
  1322. {
  1323. u32 base; /* SRAM byte address of event log header */
  1324. u32 capacity; /* event log capacity in # entries */
  1325. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1326. u32 num_wraps; /* # times uCode wrapped to top of log */
  1327. u32 next_entry; /* index of next entry to be written by uCode */
  1328. u32 size; /* # entries that we'll print */
  1329. int pos = 0;
  1330. size_t bufsz = 0;
  1331. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1332. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1333. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1334. return -EINVAL;
  1335. }
  1336. /* event log header */
  1337. capacity = iwl_read_targ_mem(priv, base);
  1338. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1339. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1340. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1341. if (capacity > priv->cfg->max_event_log_size) {
  1342. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1343. capacity, priv->cfg->max_event_log_size);
  1344. capacity = priv->cfg->max_event_log_size;
  1345. }
  1346. if (next_entry > priv->cfg->max_event_log_size) {
  1347. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1348. next_entry, priv->cfg->max_event_log_size);
  1349. next_entry = priv->cfg->max_event_log_size;
  1350. }
  1351. size = num_wraps ? capacity : next_entry;
  1352. /* bail out if nothing in log */
  1353. if (size == 0) {
  1354. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1355. return pos;
  1356. }
  1357. #ifdef CONFIG_IWLWIFI_DEBUG
  1358. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1359. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1360. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1361. #else
  1362. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1363. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1364. #endif
  1365. IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
  1366. size);
  1367. #ifdef CONFIG_IWLWIFI_DEBUG
  1368. if (display) {
  1369. if (full_log)
  1370. bufsz = capacity * 48;
  1371. else
  1372. bufsz = size * 48;
  1373. *buf = kmalloc(bufsz, GFP_KERNEL);
  1374. if (!*buf)
  1375. return -ENOMEM;
  1376. }
  1377. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1378. /* if uCode has wrapped back to top of log,
  1379. * start at the oldest entry,
  1380. * i.e the next one that uCode would fill.
  1381. */
  1382. if (num_wraps)
  1383. pos = iwl3945_print_event_log(priv, next_entry,
  1384. capacity - next_entry, mode,
  1385. pos, buf, bufsz);
  1386. /* (then/else) start at top of log */
  1387. pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
  1388. pos, buf, bufsz);
  1389. } else
  1390. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1391. next_entry, size, mode,
  1392. pos, buf, bufsz);
  1393. #else
  1394. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1395. next_entry, size, mode,
  1396. pos, buf, bufsz);
  1397. #endif
  1398. return pos;
  1399. }
  1400. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  1401. {
  1402. u32 inta, handled = 0;
  1403. u32 inta_fh;
  1404. unsigned long flags;
  1405. #ifdef CONFIG_IWLWIFI_DEBUG
  1406. u32 inta_mask;
  1407. #endif
  1408. spin_lock_irqsave(&priv->lock, flags);
  1409. /* Ack/clear/reset pending uCode interrupts.
  1410. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1411. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1412. inta = iwl_read32(priv, CSR_INT);
  1413. iwl_write32(priv, CSR_INT, inta);
  1414. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1415. * Any new interrupts that happen after this, either while we're
  1416. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1417. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1418. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  1419. #ifdef CONFIG_IWLWIFI_DEBUG
  1420. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1421. /* just for debug */
  1422. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1423. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1424. inta, inta_mask, inta_fh);
  1425. }
  1426. #endif
  1427. spin_unlock_irqrestore(&priv->lock, flags);
  1428. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1429. * atomic, make sure that inta covers all the interrupts that
  1430. * we've discovered, even if FH interrupt came in just after
  1431. * reading CSR_INT. */
  1432. if (inta_fh & CSR39_FH_INT_RX_MASK)
  1433. inta |= CSR_INT_BIT_FH_RX;
  1434. if (inta_fh & CSR39_FH_INT_TX_MASK)
  1435. inta |= CSR_INT_BIT_FH_TX;
  1436. /* Now service all interrupt bits discovered above. */
  1437. if (inta & CSR_INT_BIT_HW_ERR) {
  1438. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1439. /* Tell the device to stop sending interrupts */
  1440. iwl_disable_interrupts(priv);
  1441. priv->isr_stats.hw++;
  1442. iwl_irq_handle_error(priv);
  1443. handled |= CSR_INT_BIT_HW_ERR;
  1444. return;
  1445. }
  1446. #ifdef CONFIG_IWLWIFI_DEBUG
  1447. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1448. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1449. if (inta & CSR_INT_BIT_SCD) {
  1450. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1451. "the frame/frames.\n");
  1452. priv->isr_stats.sch++;
  1453. }
  1454. /* Alive notification via Rx interrupt will do the real work */
  1455. if (inta & CSR_INT_BIT_ALIVE) {
  1456. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1457. priv->isr_stats.alive++;
  1458. }
  1459. }
  1460. #endif
  1461. /* Safely ignore these bits for debug checks below */
  1462. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1463. /* Error detected by uCode */
  1464. if (inta & CSR_INT_BIT_SW_ERR) {
  1465. IWL_ERR(priv, "Microcode SW error detected. "
  1466. "Restarting 0x%X.\n", inta);
  1467. priv->isr_stats.sw++;
  1468. priv->isr_stats.sw_err = inta;
  1469. iwl_irq_handle_error(priv);
  1470. handled |= CSR_INT_BIT_SW_ERR;
  1471. }
  1472. /* uCode wakes up after power-down sleep */
  1473. if (inta & CSR_INT_BIT_WAKEUP) {
  1474. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1475. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1476. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  1477. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1478. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1479. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1480. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1481. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1482. priv->isr_stats.wakeup++;
  1483. handled |= CSR_INT_BIT_WAKEUP;
  1484. }
  1485. /* All uCode command responses, including Tx command responses,
  1486. * Rx "responses" (frame-received notification), and other
  1487. * notifications from uCode come through here*/
  1488. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1489. iwl3945_rx_handle(priv);
  1490. priv->isr_stats.rx++;
  1491. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1492. }
  1493. if (inta & CSR_INT_BIT_FH_TX) {
  1494. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1495. priv->isr_stats.tx++;
  1496. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  1497. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  1498. (FH39_SRVC_CHNL), 0x0);
  1499. handled |= CSR_INT_BIT_FH_TX;
  1500. }
  1501. if (inta & ~handled) {
  1502. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1503. priv->isr_stats.unhandled++;
  1504. }
  1505. if (inta & ~priv->inta_mask) {
  1506. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1507. inta & ~priv->inta_mask);
  1508. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1509. }
  1510. /* Re-enable all interrupts */
  1511. /* only Re-enable if disabled by irq */
  1512. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1513. iwl_enable_interrupts(priv);
  1514. #ifdef CONFIG_IWLWIFI_DEBUG
  1515. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1516. inta = iwl_read32(priv, CSR_INT);
  1517. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1518. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1519. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1520. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1521. }
  1522. #endif
  1523. }
  1524. static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
  1525. struct ieee80211_vif *vif,
  1526. enum ieee80211_band band,
  1527. struct iwl3945_scan_channel *scan_ch)
  1528. {
  1529. const struct ieee80211_supported_band *sband;
  1530. u16 passive_dwell = 0;
  1531. u16 active_dwell = 0;
  1532. int added = 0;
  1533. u8 channel = 0;
  1534. sband = iwl_get_hw_mode(priv, band);
  1535. if (!sband) {
  1536. IWL_ERR(priv, "invalid band\n");
  1537. return added;
  1538. }
  1539. active_dwell = iwl_get_active_dwell_time(priv, band, 0);
  1540. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1541. if (passive_dwell <= active_dwell)
  1542. passive_dwell = active_dwell + 1;
  1543. channel = iwl_get_single_channel_number(priv, band);
  1544. if (channel) {
  1545. scan_ch->channel = channel;
  1546. scan_ch->type = 0; /* passive */
  1547. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1548. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1549. /* Set txpower levels to defaults */
  1550. scan_ch->tpc.dsp_atten = 110;
  1551. if (band == IEEE80211_BAND_5GHZ)
  1552. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1553. else
  1554. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1555. added++;
  1556. } else
  1557. IWL_ERR(priv, "no valid channel found\n");
  1558. return added;
  1559. }
  1560. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  1561. enum ieee80211_band band,
  1562. u8 is_active, u8 n_probes,
  1563. struct iwl3945_scan_channel *scan_ch,
  1564. struct ieee80211_vif *vif)
  1565. {
  1566. struct ieee80211_channel *chan;
  1567. const struct ieee80211_supported_band *sband;
  1568. const struct iwl_channel_info *ch_info;
  1569. u16 passive_dwell = 0;
  1570. u16 active_dwell = 0;
  1571. int added, i;
  1572. sband = iwl_get_hw_mode(priv, band);
  1573. if (!sband)
  1574. return 0;
  1575. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  1576. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1577. if (passive_dwell <= active_dwell)
  1578. passive_dwell = active_dwell + 1;
  1579. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1580. chan = priv->scan_request->channels[i];
  1581. if (chan->band != band)
  1582. continue;
  1583. scan_ch->channel = chan->hw_value;
  1584. ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
  1585. if (!is_channel_valid(ch_info)) {
  1586. IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
  1587. scan_ch->channel);
  1588. continue;
  1589. }
  1590. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1591. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1592. /* If passive , set up for auto-switch
  1593. * and use long active_dwell time.
  1594. */
  1595. if (!is_active || is_channel_passive(ch_info) ||
  1596. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  1597. scan_ch->type = 0; /* passive */
  1598. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  1599. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  1600. } else {
  1601. scan_ch->type = 1; /* active */
  1602. }
  1603. /* Set direct probe bits. These may be used both for active
  1604. * scan channels (probes gets sent right away),
  1605. * or for passive channels (probes get se sent only after
  1606. * hearing clear Rx packet).*/
  1607. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  1608. if (n_probes)
  1609. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1610. } else {
  1611. /* uCode v1 does not allow setting direct probe bits on
  1612. * passive channel. */
  1613. if ((scan_ch->type & 1) && n_probes)
  1614. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1615. }
  1616. /* Set txpower levels to defaults */
  1617. scan_ch->tpc.dsp_atten = 110;
  1618. /* scan_pwr_info->tpc.dsp_atten; */
  1619. /*scan_pwr_info->tpc.tx_gain; */
  1620. if (band == IEEE80211_BAND_5GHZ)
  1621. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1622. else {
  1623. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1624. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1625. * power level:
  1626. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1627. */
  1628. }
  1629. IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
  1630. scan_ch->channel,
  1631. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  1632. (scan_ch->type & 1) ?
  1633. active_dwell : passive_dwell);
  1634. scan_ch++;
  1635. added++;
  1636. }
  1637. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1638. return added;
  1639. }
  1640. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  1641. struct ieee80211_rate *rates)
  1642. {
  1643. int i;
  1644. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  1645. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  1646. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  1647. rates[i].hw_value_short = i;
  1648. rates[i].flags = 0;
  1649. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  1650. /*
  1651. * If CCK != 1M then set short preamble rate flag.
  1652. */
  1653. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  1654. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  1655. }
  1656. }
  1657. }
  1658. /******************************************************************************
  1659. *
  1660. * uCode download functions
  1661. *
  1662. ******************************************************************************/
  1663. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  1664. {
  1665. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1666. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1667. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1668. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1669. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1670. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1671. }
  1672. /**
  1673. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  1674. * looking at all data.
  1675. */
  1676. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  1677. {
  1678. u32 val;
  1679. u32 save_len = len;
  1680. int rc = 0;
  1681. u32 errcnt;
  1682. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1683. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1684. IWL39_RTC_INST_LOWER_BOUND);
  1685. errcnt = 0;
  1686. for (; len > 0; len -= sizeof(u32), image++) {
  1687. /* read data comes through single port, auto-incr addr */
  1688. /* NOTE: Use the debugless read so we don't flood kernel log
  1689. * if IWL_DL_IO is set */
  1690. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1691. if (val != le32_to_cpu(*image)) {
  1692. IWL_ERR(priv, "uCode INST section is invalid at "
  1693. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1694. save_len - len, val, le32_to_cpu(*image));
  1695. rc = -EIO;
  1696. errcnt++;
  1697. if (errcnt >= 20)
  1698. break;
  1699. }
  1700. }
  1701. if (!errcnt)
  1702. IWL_DEBUG_INFO(priv,
  1703. "ucode image in INSTRUCTION memory is good\n");
  1704. return rc;
  1705. }
  1706. /**
  1707. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1708. * using sample data 100 bytes apart. If these sample points are good,
  1709. * it's a pretty good bet that everything between them is good, too.
  1710. */
  1711. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1712. {
  1713. u32 val;
  1714. int rc = 0;
  1715. u32 errcnt = 0;
  1716. u32 i;
  1717. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1718. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1719. /* read data comes through single port, auto-incr addr */
  1720. /* NOTE: Use the debugless read so we don't flood kernel log
  1721. * if IWL_DL_IO is set */
  1722. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1723. i + IWL39_RTC_INST_LOWER_BOUND);
  1724. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1725. if (val != le32_to_cpu(*image)) {
  1726. #if 0 /* Enable this if you want to see details */
  1727. IWL_ERR(priv, "uCode INST section is invalid at "
  1728. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1729. i, val, *image);
  1730. #endif
  1731. rc = -EIO;
  1732. errcnt++;
  1733. if (errcnt >= 3)
  1734. break;
  1735. }
  1736. }
  1737. return rc;
  1738. }
  1739. /**
  1740. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  1741. * and verify its contents
  1742. */
  1743. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  1744. {
  1745. __le32 *image;
  1746. u32 len;
  1747. int rc = 0;
  1748. /* Try bootstrap */
  1749. image = (__le32 *)priv->ucode_boot.v_addr;
  1750. len = priv->ucode_boot.len;
  1751. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1752. if (rc == 0) {
  1753. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1754. return 0;
  1755. }
  1756. /* Try initialize */
  1757. image = (__le32 *)priv->ucode_init.v_addr;
  1758. len = priv->ucode_init.len;
  1759. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1760. if (rc == 0) {
  1761. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1762. return 0;
  1763. }
  1764. /* Try runtime/protocol */
  1765. image = (__le32 *)priv->ucode_code.v_addr;
  1766. len = priv->ucode_code.len;
  1767. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1768. if (rc == 0) {
  1769. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1770. return 0;
  1771. }
  1772. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1773. /* Since nothing seems to match, show first several data entries in
  1774. * instruction SRAM, so maybe visual inspection will give a clue.
  1775. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1776. image = (__le32 *)priv->ucode_boot.v_addr;
  1777. len = priv->ucode_boot.len;
  1778. rc = iwl3945_verify_inst_full(priv, image, len);
  1779. return rc;
  1780. }
  1781. static void iwl3945_nic_start(struct iwl_priv *priv)
  1782. {
  1783. /* Remove all resets to allow NIC to operate */
  1784. iwl_write32(priv, CSR_RESET, 0);
  1785. }
  1786. #define IWL3945_UCODE_GET(item) \
  1787. static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\
  1788. { \
  1789. return le32_to_cpu(ucode->u.v1.item); \
  1790. }
  1791. static u32 iwl3945_ucode_get_header_size(u32 api_ver)
  1792. {
  1793. return 24;
  1794. }
  1795. static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode)
  1796. {
  1797. return (u8 *) ucode->u.v1.data;
  1798. }
  1799. IWL3945_UCODE_GET(inst_size);
  1800. IWL3945_UCODE_GET(data_size);
  1801. IWL3945_UCODE_GET(init_size);
  1802. IWL3945_UCODE_GET(init_data_size);
  1803. IWL3945_UCODE_GET(boot_size);
  1804. /**
  1805. * iwl3945_read_ucode - Read uCode images from disk file.
  1806. *
  1807. * Copy into buffers for card to fetch via bus-mastering
  1808. */
  1809. static int iwl3945_read_ucode(struct iwl_priv *priv)
  1810. {
  1811. const struct iwl_ucode_header *ucode;
  1812. int ret = -EINVAL, index;
  1813. const struct firmware *ucode_raw;
  1814. /* firmware file name contains uCode/driver compatibility version */
  1815. const char *name_pre = priv->cfg->fw_name_pre;
  1816. const unsigned int api_max = priv->cfg->ucode_api_max;
  1817. const unsigned int api_min = priv->cfg->ucode_api_min;
  1818. char buf[25];
  1819. u8 *src;
  1820. size_t len;
  1821. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1822. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1823. * request_firmware() is synchronous, file is in memory on return. */
  1824. for (index = api_max; index >= api_min; index--) {
  1825. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  1826. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1827. if (ret < 0) {
  1828. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1829. buf, ret);
  1830. if (ret == -ENOENT)
  1831. continue;
  1832. else
  1833. goto error;
  1834. } else {
  1835. if (index < api_max)
  1836. IWL_ERR(priv, "Loaded firmware %s, "
  1837. "which is deprecated. "
  1838. " Please use API v%u instead.\n",
  1839. buf, api_max);
  1840. IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
  1841. "(%zd bytes) from disk\n",
  1842. buf, ucode_raw->size);
  1843. break;
  1844. }
  1845. }
  1846. if (ret < 0)
  1847. goto error;
  1848. /* Make sure that we got at least our header! */
  1849. if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) {
  1850. IWL_ERR(priv, "File size way too small!\n");
  1851. ret = -EINVAL;
  1852. goto err_release;
  1853. }
  1854. /* Data from ucode file: header followed by uCode images */
  1855. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1856. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1857. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1858. inst_size = iwl3945_ucode_get_inst_size(ucode);
  1859. data_size = iwl3945_ucode_get_data_size(ucode);
  1860. init_size = iwl3945_ucode_get_init_size(ucode);
  1861. init_data_size = iwl3945_ucode_get_init_data_size(ucode);
  1862. boot_size = iwl3945_ucode_get_boot_size(ucode);
  1863. src = iwl3945_ucode_get_data(ucode);
  1864. /* api_ver should match the api version forming part of the
  1865. * firmware filename ... but we don't check for that and only rely
  1866. * on the API version read from firmware header from here on forward */
  1867. if (api_ver < api_min || api_ver > api_max) {
  1868. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1869. "Driver supports v%u, firmware is v%u.\n",
  1870. api_max, api_ver);
  1871. priv->ucode_ver = 0;
  1872. ret = -EINVAL;
  1873. goto err_release;
  1874. }
  1875. if (api_ver != api_max)
  1876. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  1877. "got %u. New firmware can be obtained "
  1878. "from http://www.intellinuxwireless.org.\n",
  1879. api_max, api_ver);
  1880. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1881. IWL_UCODE_MAJOR(priv->ucode_ver),
  1882. IWL_UCODE_MINOR(priv->ucode_ver),
  1883. IWL_UCODE_API(priv->ucode_ver),
  1884. IWL_UCODE_SERIAL(priv->ucode_ver));
  1885. snprintf(priv->hw->wiphy->fw_version,
  1886. sizeof(priv->hw->wiphy->fw_version),
  1887. "%u.%u.%u.%u",
  1888. IWL_UCODE_MAJOR(priv->ucode_ver),
  1889. IWL_UCODE_MINOR(priv->ucode_ver),
  1890. IWL_UCODE_API(priv->ucode_ver),
  1891. IWL_UCODE_SERIAL(priv->ucode_ver));
  1892. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1893. priv->ucode_ver);
  1894. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1895. inst_size);
  1896. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1897. data_size);
  1898. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1899. init_size);
  1900. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1901. init_data_size);
  1902. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1903. boot_size);
  1904. /* Verify size of file vs. image size info in file's header */
  1905. if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) +
  1906. inst_size + data_size + init_size +
  1907. init_data_size + boot_size) {
  1908. IWL_DEBUG_INFO(priv,
  1909. "uCode file size %zd does not match expected size\n",
  1910. ucode_raw->size);
  1911. ret = -EINVAL;
  1912. goto err_release;
  1913. }
  1914. /* Verify that uCode images will fit in card's SRAM */
  1915. if (inst_size > IWL39_MAX_INST_SIZE) {
  1916. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1917. inst_size);
  1918. ret = -EINVAL;
  1919. goto err_release;
  1920. }
  1921. if (data_size > IWL39_MAX_DATA_SIZE) {
  1922. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1923. data_size);
  1924. ret = -EINVAL;
  1925. goto err_release;
  1926. }
  1927. if (init_size > IWL39_MAX_INST_SIZE) {
  1928. IWL_DEBUG_INFO(priv,
  1929. "uCode init instr len %d too large to fit in\n",
  1930. init_size);
  1931. ret = -EINVAL;
  1932. goto err_release;
  1933. }
  1934. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  1935. IWL_DEBUG_INFO(priv,
  1936. "uCode init data len %d too large to fit in\n",
  1937. init_data_size);
  1938. ret = -EINVAL;
  1939. goto err_release;
  1940. }
  1941. if (boot_size > IWL39_MAX_BSM_SIZE) {
  1942. IWL_DEBUG_INFO(priv,
  1943. "uCode boot instr len %d too large to fit in\n",
  1944. boot_size);
  1945. ret = -EINVAL;
  1946. goto err_release;
  1947. }
  1948. /* Allocate ucode buffers for card's bus-master loading ... */
  1949. /* Runtime instructions and 2 copies of data:
  1950. * 1) unmodified from disk
  1951. * 2) backup cache for save/restore during power-downs */
  1952. priv->ucode_code.len = inst_size;
  1953. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1954. priv->ucode_data.len = data_size;
  1955. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1956. priv->ucode_data_backup.len = data_size;
  1957. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1958. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1959. !priv->ucode_data_backup.v_addr)
  1960. goto err_pci_alloc;
  1961. /* Initialization instructions and data */
  1962. if (init_size && init_data_size) {
  1963. priv->ucode_init.len = init_size;
  1964. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1965. priv->ucode_init_data.len = init_data_size;
  1966. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1967. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1968. goto err_pci_alloc;
  1969. }
  1970. /* Bootstrap (instructions only, no data) */
  1971. if (boot_size) {
  1972. priv->ucode_boot.len = boot_size;
  1973. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1974. if (!priv->ucode_boot.v_addr)
  1975. goto err_pci_alloc;
  1976. }
  1977. /* Copy images into buffers for card's bus-master reads ... */
  1978. /* Runtime instructions (first block of data in file) */
  1979. len = inst_size;
  1980. IWL_DEBUG_INFO(priv,
  1981. "Copying (but not loading) uCode instr len %zd\n", len);
  1982. memcpy(priv->ucode_code.v_addr, src, len);
  1983. src += len;
  1984. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1985. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1986. /* Runtime data (2nd block)
  1987. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  1988. len = data_size;
  1989. IWL_DEBUG_INFO(priv,
  1990. "Copying (but not loading) uCode data len %zd\n", len);
  1991. memcpy(priv->ucode_data.v_addr, src, len);
  1992. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1993. src += len;
  1994. /* Initialization instructions (3rd block) */
  1995. if (init_size) {
  1996. len = init_size;
  1997. IWL_DEBUG_INFO(priv,
  1998. "Copying (but not loading) init instr len %zd\n", len);
  1999. memcpy(priv->ucode_init.v_addr, src, len);
  2000. src += len;
  2001. }
  2002. /* Initialization data (4th block) */
  2003. if (init_data_size) {
  2004. len = init_data_size;
  2005. IWL_DEBUG_INFO(priv,
  2006. "Copying (but not loading) init data len %zd\n", len);
  2007. memcpy(priv->ucode_init_data.v_addr, src, len);
  2008. src += len;
  2009. }
  2010. /* Bootstrap instructions (5th block) */
  2011. len = boot_size;
  2012. IWL_DEBUG_INFO(priv,
  2013. "Copying (but not loading) boot instr len %zd\n", len);
  2014. memcpy(priv->ucode_boot.v_addr, src, len);
  2015. /* We have our copies now, allow OS release its copies */
  2016. release_firmware(ucode_raw);
  2017. return 0;
  2018. err_pci_alloc:
  2019. IWL_ERR(priv, "failed to allocate pci memory\n");
  2020. ret = -ENOMEM;
  2021. iwl3945_dealloc_ucode_pci(priv);
  2022. err_release:
  2023. release_firmware(ucode_raw);
  2024. error:
  2025. return ret;
  2026. }
  2027. /**
  2028. * iwl3945_set_ucode_ptrs - Set uCode address location
  2029. *
  2030. * Tell initialization uCode where to find runtime uCode.
  2031. *
  2032. * BSM registers initially contain pointers to initialization uCode.
  2033. * We need to replace them to load runtime uCode inst and data,
  2034. * and to save runtime data when powering down.
  2035. */
  2036. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  2037. {
  2038. dma_addr_t pinst;
  2039. dma_addr_t pdata;
  2040. /* bits 31:0 for 3945 */
  2041. pinst = priv->ucode_code.p_addr;
  2042. pdata = priv->ucode_data_backup.p_addr;
  2043. /* Tell bootstrap uCode where to find image to load */
  2044. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  2045. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  2046. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  2047. priv->ucode_data.len);
  2048. /* Inst byte count must be last to set up, bit 31 signals uCode
  2049. * that all new ptr/size info is in place */
  2050. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  2051. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  2052. IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
  2053. return 0;
  2054. }
  2055. /**
  2056. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  2057. *
  2058. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  2059. *
  2060. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  2061. */
  2062. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  2063. {
  2064. /* Check alive response for "valid" sign from uCode */
  2065. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  2066. /* We had an error bringing up the hardware, so take it
  2067. * all the way back down so we can try again */
  2068. IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
  2069. goto restart;
  2070. }
  2071. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  2072. * This is a paranoid check, because we would not have gotten the
  2073. * "initialize" alive if code weren't properly loaded. */
  2074. if (iwl3945_verify_ucode(priv)) {
  2075. /* Runtime instruction load was bad;
  2076. * take it all the way back down so we can try again */
  2077. IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
  2078. goto restart;
  2079. }
  2080. /* Send pointers to protocol/runtime uCode image ... init code will
  2081. * load and launch runtime uCode, which will send us another "Alive"
  2082. * notification. */
  2083. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  2084. if (iwl3945_set_ucode_ptrs(priv)) {
  2085. /* Runtime instruction load won't happen;
  2086. * take it all the way back down so we can try again */
  2087. IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
  2088. goto restart;
  2089. }
  2090. return;
  2091. restart:
  2092. queue_work(priv->workqueue, &priv->restart);
  2093. }
  2094. /**
  2095. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  2096. * from protocol/runtime uCode (initialization uCode's
  2097. * Alive gets handled by iwl3945_init_alive_start()).
  2098. */
  2099. static void iwl3945_alive_start(struct iwl_priv *priv)
  2100. {
  2101. int thermal_spin = 0;
  2102. u32 rfkill;
  2103. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2104. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2105. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2106. /* We had an error bringing up the hardware, so take it
  2107. * all the way back down so we can try again */
  2108. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2109. goto restart;
  2110. }
  2111. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2112. * This is a paranoid check, because we would not have gotten the
  2113. * "runtime" alive if code weren't properly loaded. */
  2114. if (iwl3945_verify_ucode(priv)) {
  2115. /* Runtime instruction load was bad;
  2116. * take it all the way back down so we can try again */
  2117. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2118. goto restart;
  2119. }
  2120. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  2121. IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
  2122. if (rfkill & 0x1) {
  2123. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2124. /* if RFKILL is not on, then wait for thermal
  2125. * sensor in adapter to kick in */
  2126. while (iwl3945_hw_get_temperature(priv) == 0) {
  2127. thermal_spin++;
  2128. udelay(10);
  2129. }
  2130. if (thermal_spin)
  2131. IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
  2132. thermal_spin * 10);
  2133. } else
  2134. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2135. /* After the ALIVE response, we can send commands to 3945 uCode */
  2136. set_bit(STATUS_ALIVE, &priv->status);
  2137. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2138. /* Enable timer to monitor the driver queues */
  2139. mod_timer(&priv->monitor_recover,
  2140. jiffies +
  2141. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  2142. }
  2143. if (iwl_is_rfkill(priv))
  2144. return;
  2145. ieee80211_wake_queues(priv->hw);
  2146. priv->active_rate = IWL_RATES_MASK;
  2147. iwl_power_update_mode(priv, true);
  2148. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2149. struct iwl3945_rxon_cmd *active_rxon =
  2150. (struct iwl3945_rxon_cmd *)(&ctx->active);
  2151. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2152. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2153. } else {
  2154. /* Initialize our rx_config data */
  2155. iwl_connection_init_rx_config(priv, NULL);
  2156. }
  2157. /* Configure Bluetooth device coexistence support */
  2158. priv->cfg->ops->hcmd->send_bt_config(priv);
  2159. /* Configure the adapter for unassociated operation */
  2160. iwlcore_commit_rxon(priv, ctx);
  2161. iwl3945_reg_txpower_periodic(priv);
  2162. iwl_leds_init(priv);
  2163. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2164. set_bit(STATUS_READY, &priv->status);
  2165. wake_up_interruptible(&priv->wait_command_queue);
  2166. return;
  2167. restart:
  2168. queue_work(priv->workqueue, &priv->restart);
  2169. }
  2170. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  2171. static void __iwl3945_down(struct iwl_priv *priv)
  2172. {
  2173. unsigned long flags;
  2174. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2175. struct ieee80211_conf *conf = NULL;
  2176. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2177. conf = ieee80211_get_hw_conf(priv->hw);
  2178. if (!exit_pending)
  2179. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2180. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2181. * to prevent rearm timer */
  2182. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2183. del_timer_sync(&priv->monitor_recover);
  2184. /* Station information will now be cleared in device */
  2185. iwl_clear_ucode_stations(priv, NULL);
  2186. iwl_dealloc_bcast_stations(priv);
  2187. iwl_clear_driver_stations(priv);
  2188. /* Unblock any waiting calls */
  2189. wake_up_interruptible_all(&priv->wait_command_queue);
  2190. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2191. * exiting the module */
  2192. if (!exit_pending)
  2193. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2194. /* stop and reset the on-board processor */
  2195. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2196. /* tell the device to stop sending interrupts */
  2197. spin_lock_irqsave(&priv->lock, flags);
  2198. iwl_disable_interrupts(priv);
  2199. spin_unlock_irqrestore(&priv->lock, flags);
  2200. iwl_synchronize_irq(priv);
  2201. if (priv->mac80211_registered)
  2202. ieee80211_stop_queues(priv->hw);
  2203. /* If we have not previously called iwl3945_init() then
  2204. * clear all bits but the RF Kill bits and return */
  2205. if (!iwl_is_init(priv)) {
  2206. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2207. STATUS_RF_KILL_HW |
  2208. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2209. STATUS_GEO_CONFIGURED |
  2210. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2211. STATUS_EXIT_PENDING;
  2212. goto exit;
  2213. }
  2214. /* ...otherwise clear out all the status bits but the RF Kill
  2215. * bit and continue taking the NIC down. */
  2216. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2217. STATUS_RF_KILL_HW |
  2218. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2219. STATUS_GEO_CONFIGURED |
  2220. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2221. STATUS_FW_ERROR |
  2222. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2223. STATUS_EXIT_PENDING;
  2224. iwl3945_hw_txq_ctx_stop(priv);
  2225. iwl3945_hw_rxq_stop(priv);
  2226. /* Power-down device's busmaster DMA clocks */
  2227. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2228. udelay(5);
  2229. /* Stop the device, and put it in low power state */
  2230. priv->cfg->ops->lib->apm_ops.stop(priv);
  2231. exit:
  2232. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2233. if (priv->ibss_beacon)
  2234. dev_kfree_skb(priv->ibss_beacon);
  2235. priv->ibss_beacon = NULL;
  2236. /* clear out any free frames */
  2237. iwl3945_clear_free_frames(priv);
  2238. }
  2239. static void iwl3945_down(struct iwl_priv *priv)
  2240. {
  2241. mutex_lock(&priv->mutex);
  2242. __iwl3945_down(priv);
  2243. mutex_unlock(&priv->mutex);
  2244. iwl3945_cancel_deferred_work(priv);
  2245. }
  2246. #define MAX_HW_RESTARTS 5
  2247. static int __iwl3945_up(struct iwl_priv *priv)
  2248. {
  2249. int rc, i;
  2250. rc = iwl_alloc_bcast_station(priv, &priv->contexts[IWL_RXON_CTX_BSS],
  2251. false);
  2252. if (rc)
  2253. return rc;
  2254. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2255. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2256. return -EIO;
  2257. }
  2258. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2259. IWL_ERR(priv, "ucode not available for device bring up\n");
  2260. return -EIO;
  2261. }
  2262. /* If platform's RF_KILL switch is NOT set to KILL */
  2263. if (iwl_read32(priv, CSR_GP_CNTRL) &
  2264. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2265. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2266. else {
  2267. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2268. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2269. return -ENODEV;
  2270. }
  2271. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2272. rc = iwl3945_hw_nic_init(priv);
  2273. if (rc) {
  2274. IWL_ERR(priv, "Unable to int nic\n");
  2275. return rc;
  2276. }
  2277. /* make sure rfkill handshake bits are cleared */
  2278. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2279. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2280. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2281. /* clear (again), then enable host interrupts */
  2282. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2283. iwl_enable_interrupts(priv);
  2284. /* really make sure rfkill handshake bits are cleared */
  2285. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2286. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2287. /* Copy original ucode data image from disk into backup cache.
  2288. * This will be used to initialize the on-board processor's
  2289. * data SRAM for a clean start when the runtime program first loads. */
  2290. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2291. priv->ucode_data.len);
  2292. /* We return success when we resume from suspend and rf_kill is on. */
  2293. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  2294. return 0;
  2295. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2296. /* load bootstrap state machine,
  2297. * load bootstrap program into processor's memory,
  2298. * prepare to load the "initialize" uCode */
  2299. rc = priv->cfg->ops->lib->load_ucode(priv);
  2300. if (rc) {
  2301. IWL_ERR(priv,
  2302. "Unable to set up bootstrap uCode: %d\n", rc);
  2303. continue;
  2304. }
  2305. /* start card; "initialize" will load runtime ucode */
  2306. iwl3945_nic_start(priv);
  2307. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2308. return 0;
  2309. }
  2310. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2311. __iwl3945_down(priv);
  2312. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2313. /* tried to restart and config the device for as long as our
  2314. * patience could withstand */
  2315. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2316. return -EIO;
  2317. }
  2318. /*****************************************************************************
  2319. *
  2320. * Workqueue callbacks
  2321. *
  2322. *****************************************************************************/
  2323. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  2324. {
  2325. struct iwl_priv *priv =
  2326. container_of(data, struct iwl_priv, init_alive_start.work);
  2327. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2328. return;
  2329. mutex_lock(&priv->mutex);
  2330. iwl3945_init_alive_start(priv);
  2331. mutex_unlock(&priv->mutex);
  2332. }
  2333. static void iwl3945_bg_alive_start(struct work_struct *data)
  2334. {
  2335. struct iwl_priv *priv =
  2336. container_of(data, struct iwl_priv, alive_start.work);
  2337. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2338. return;
  2339. mutex_lock(&priv->mutex);
  2340. iwl3945_alive_start(priv);
  2341. mutex_unlock(&priv->mutex);
  2342. }
  2343. /*
  2344. * 3945 cannot interrupt driver when hardware rf kill switch toggles;
  2345. * driver must poll CSR_GP_CNTRL_REG register for change. This register
  2346. * *is* readable even when device has been SW_RESET into low power mode
  2347. * (e.g. during RF KILL).
  2348. */
  2349. static void iwl3945_rfkill_poll(struct work_struct *data)
  2350. {
  2351. struct iwl_priv *priv =
  2352. container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
  2353. bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
  2354. bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
  2355. & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
  2356. if (new_rfkill != old_rfkill) {
  2357. if (new_rfkill)
  2358. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2359. else
  2360. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2361. wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
  2362. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  2363. new_rfkill ? "disable radio" : "enable radio");
  2364. }
  2365. /* Keep this running, even if radio now enabled. This will be
  2366. * cancelled in mac_start() if system decides to start again */
  2367. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2368. round_jiffies_relative(2 * HZ));
  2369. }
  2370. void iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2371. {
  2372. struct iwl_host_cmd cmd = {
  2373. .id = REPLY_SCAN_CMD,
  2374. .len = sizeof(struct iwl3945_scan_cmd),
  2375. .flags = CMD_SIZE_HUGE,
  2376. };
  2377. struct iwl3945_scan_cmd *scan;
  2378. struct ieee80211_conf *conf = NULL;
  2379. u8 n_probes = 0;
  2380. enum ieee80211_band band;
  2381. bool is_active = false;
  2382. conf = ieee80211_get_hw_conf(priv->hw);
  2383. cancel_delayed_work(&priv->scan_check);
  2384. if (!iwl_is_ready(priv)) {
  2385. IWL_WARN(priv, "request scan called when driver not ready.\n");
  2386. goto done;
  2387. }
  2388. /* Make sure the scan wasn't canceled before this queued work
  2389. * was given the chance to run... */
  2390. if (!test_bit(STATUS_SCANNING, &priv->status))
  2391. goto done;
  2392. /* This should never be called or scheduled if there is currently
  2393. * a scan active in the hardware. */
  2394. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  2395. IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
  2396. "Ignoring second request.\n");
  2397. goto done;
  2398. }
  2399. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2400. IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
  2401. goto done;
  2402. }
  2403. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2404. IWL_DEBUG_HC(priv,
  2405. "Scan request while abort pending. Queuing.\n");
  2406. goto done;
  2407. }
  2408. if (iwl_is_rfkill(priv)) {
  2409. IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
  2410. goto done;
  2411. }
  2412. if (!test_bit(STATUS_READY, &priv->status)) {
  2413. IWL_DEBUG_HC(priv,
  2414. "Scan request while uninitialized. Queuing.\n");
  2415. goto done;
  2416. }
  2417. if (!priv->scan_cmd) {
  2418. priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  2419. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  2420. if (!priv->scan_cmd) {
  2421. IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
  2422. goto done;
  2423. }
  2424. }
  2425. scan = priv->scan_cmd;
  2426. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  2427. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  2428. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  2429. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2430. u16 interval = 0;
  2431. u32 extra;
  2432. u32 suspend_time = 100;
  2433. u32 scan_suspend_time = 100;
  2434. unsigned long flags;
  2435. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  2436. spin_lock_irqsave(&priv->lock, flags);
  2437. if (priv->is_internal_short_scan)
  2438. interval = 0;
  2439. else
  2440. interval = vif->bss_conf.beacon_int;
  2441. spin_unlock_irqrestore(&priv->lock, flags);
  2442. scan->suspend_time = 0;
  2443. scan->max_out_time = cpu_to_le32(200 * 1024);
  2444. if (!interval)
  2445. interval = suspend_time;
  2446. /*
  2447. * suspend time format:
  2448. * 0-19: beacon interval in usec (time before exec.)
  2449. * 20-23: 0
  2450. * 24-31: number of beacons (suspend between channels)
  2451. */
  2452. extra = (suspend_time / interval) << 24;
  2453. scan_suspend_time = 0xFF0FFFFF &
  2454. (extra | ((suspend_time % interval) * 1024));
  2455. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  2456. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  2457. scan_suspend_time, interval);
  2458. }
  2459. if (priv->is_internal_short_scan) {
  2460. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  2461. } else if (priv->scan_request->n_ssids) {
  2462. int i, p = 0;
  2463. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  2464. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  2465. /* always does wildcard anyway */
  2466. if (!priv->scan_request->ssids[i].ssid_len)
  2467. continue;
  2468. scan->direct_scan[p].id = WLAN_EID_SSID;
  2469. scan->direct_scan[p].len =
  2470. priv->scan_request->ssids[i].ssid_len;
  2471. memcpy(scan->direct_scan[p].ssid,
  2472. priv->scan_request->ssids[i].ssid,
  2473. priv->scan_request->ssids[i].ssid_len);
  2474. n_probes++;
  2475. p++;
  2476. }
  2477. is_active = true;
  2478. } else
  2479. IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
  2480. /* We don't build a direct scan probe request; the uCode will do
  2481. * that based on the direct_mask added to each channel entry */
  2482. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  2483. scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
  2484. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2485. /* flags + rate selection */
  2486. switch (priv->scan_band) {
  2487. case IEEE80211_BAND_2GHZ:
  2488. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  2489. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  2490. scan->good_CRC_th = 0;
  2491. band = IEEE80211_BAND_2GHZ;
  2492. break;
  2493. case IEEE80211_BAND_5GHZ:
  2494. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  2495. /*
  2496. * If active scaning is requested but a certain channel
  2497. * is marked passive, we can do active scanning if we
  2498. * detect transmissions.
  2499. */
  2500. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  2501. IWL_GOOD_CRC_TH_DISABLED;
  2502. band = IEEE80211_BAND_5GHZ;
  2503. break;
  2504. default:
  2505. IWL_WARN(priv, "Invalid scan band\n");
  2506. goto done;
  2507. }
  2508. if (!priv->is_internal_short_scan) {
  2509. scan->tx_cmd.len = cpu_to_le16(
  2510. iwl_fill_probe_req(priv,
  2511. (struct ieee80211_mgmt *)scan->data,
  2512. vif->addr,
  2513. priv->scan_request->ie,
  2514. priv->scan_request->ie_len,
  2515. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2516. } else {
  2517. /* use bcast addr, will not be transmitted but must be valid */
  2518. scan->tx_cmd.len = cpu_to_le16(
  2519. iwl_fill_probe_req(priv,
  2520. (struct ieee80211_mgmt *)scan->data,
  2521. iwl_bcast_addr, NULL, 0,
  2522. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2523. }
  2524. /* select Rx antennas */
  2525. scan->flags |= iwl3945_get_antenna_flags(priv);
  2526. if (priv->is_internal_short_scan) {
  2527. scan->channel_count =
  2528. iwl3945_get_single_channel_for_scan(priv, vif, band,
  2529. (void *)&scan->data[le16_to_cpu(
  2530. scan->tx_cmd.len)]);
  2531. } else {
  2532. scan->channel_count =
  2533. iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
  2534. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
  2535. }
  2536. if (scan->channel_count == 0) {
  2537. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  2538. goto done;
  2539. }
  2540. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  2541. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  2542. cmd.data = scan;
  2543. scan->len = cpu_to_le16(cmd.len);
  2544. set_bit(STATUS_SCAN_HW, &priv->status);
  2545. if (iwl_send_cmd_sync(priv, &cmd))
  2546. goto done;
  2547. queue_delayed_work(priv->workqueue, &priv->scan_check,
  2548. IWL_SCAN_CHECK_WATCHDOG);
  2549. return;
  2550. done:
  2551. /* can not perform scan make sure we clear scanning
  2552. * bits from status so next scan request can be performed.
  2553. * if we dont clear scanning status bit here all next scan
  2554. * will fail
  2555. */
  2556. clear_bit(STATUS_SCAN_HW, &priv->status);
  2557. clear_bit(STATUS_SCANNING, &priv->status);
  2558. /* inform mac80211 scan aborted */
  2559. queue_work(priv->workqueue, &priv->scan_completed);
  2560. }
  2561. static void iwl3945_bg_restart(struct work_struct *data)
  2562. {
  2563. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2564. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2565. return;
  2566. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2567. struct iwl_rxon_context *ctx;
  2568. mutex_lock(&priv->mutex);
  2569. for_each_context(priv, ctx)
  2570. ctx->vif = NULL;
  2571. priv->is_open = 0;
  2572. mutex_unlock(&priv->mutex);
  2573. iwl3945_down(priv);
  2574. ieee80211_restart_hw(priv->hw);
  2575. } else {
  2576. iwl3945_down(priv);
  2577. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2578. return;
  2579. mutex_lock(&priv->mutex);
  2580. __iwl3945_up(priv);
  2581. mutex_unlock(&priv->mutex);
  2582. }
  2583. }
  2584. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  2585. {
  2586. struct iwl_priv *priv =
  2587. container_of(data, struct iwl_priv, rx_replenish);
  2588. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2589. return;
  2590. mutex_lock(&priv->mutex);
  2591. iwl3945_rx_replenish(priv);
  2592. mutex_unlock(&priv->mutex);
  2593. }
  2594. void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2595. {
  2596. int rc = 0;
  2597. struct ieee80211_conf *conf = NULL;
  2598. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2599. if (!vif || !priv->is_open)
  2600. return;
  2601. if (vif->type == NL80211_IFTYPE_AP) {
  2602. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2603. return;
  2604. }
  2605. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2606. vif->bss_conf.aid, ctx->active.bssid_addr);
  2607. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2608. return;
  2609. iwl_scan_cancel_timeout(priv, 200);
  2610. conf = ieee80211_get_hw_conf(priv->hw);
  2611. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2612. iwlcore_commit_rxon(priv, ctx);
  2613. rc = iwl_send_rxon_timing(priv, vif);
  2614. if (rc)
  2615. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2616. "Attempting to continue.\n");
  2617. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2618. ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2619. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2620. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2621. if (vif->bss_conf.use_short_preamble)
  2622. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2623. else
  2624. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2625. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2626. if (vif->bss_conf.use_short_slot)
  2627. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2628. else
  2629. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2630. }
  2631. iwlcore_commit_rxon(priv, ctx);
  2632. switch (vif->type) {
  2633. case NL80211_IFTYPE_STATION:
  2634. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  2635. break;
  2636. case NL80211_IFTYPE_ADHOC:
  2637. iwl3945_send_beacon_cmd(priv);
  2638. break;
  2639. default:
  2640. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2641. __func__, vif->type);
  2642. break;
  2643. }
  2644. }
  2645. /*****************************************************************************
  2646. *
  2647. * mac80211 entry point functions
  2648. *
  2649. *****************************************************************************/
  2650. #define UCODE_READY_TIMEOUT (2 * HZ)
  2651. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  2652. {
  2653. struct iwl_priv *priv = hw->priv;
  2654. int ret;
  2655. IWL_DEBUG_MAC80211(priv, "enter\n");
  2656. /* we should be verifying the device is ready to be opened */
  2657. mutex_lock(&priv->mutex);
  2658. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2659. * ucode filename and max sizes are card-specific. */
  2660. if (!priv->ucode_code.len) {
  2661. ret = iwl3945_read_ucode(priv);
  2662. if (ret) {
  2663. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2664. mutex_unlock(&priv->mutex);
  2665. goto out_release_irq;
  2666. }
  2667. }
  2668. ret = __iwl3945_up(priv);
  2669. mutex_unlock(&priv->mutex);
  2670. if (ret)
  2671. goto out_release_irq;
  2672. IWL_DEBUG_INFO(priv, "Start UP work.\n");
  2673. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  2674. * mac80211 will not be run successfully. */
  2675. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2676. test_bit(STATUS_READY, &priv->status),
  2677. UCODE_READY_TIMEOUT);
  2678. if (!ret) {
  2679. if (!test_bit(STATUS_READY, &priv->status)) {
  2680. IWL_ERR(priv,
  2681. "Wait for START_ALIVE timeout after %dms.\n",
  2682. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2683. ret = -ETIMEDOUT;
  2684. goto out_release_irq;
  2685. }
  2686. }
  2687. /* ucode is running and will send rfkill notifications,
  2688. * no need to poll the killswitch state anymore */
  2689. cancel_delayed_work(&priv->_3945.rfkill_poll);
  2690. iwl_led_start(priv);
  2691. priv->is_open = 1;
  2692. IWL_DEBUG_MAC80211(priv, "leave\n");
  2693. return 0;
  2694. out_release_irq:
  2695. priv->is_open = 0;
  2696. IWL_DEBUG_MAC80211(priv, "leave - failed\n");
  2697. return ret;
  2698. }
  2699. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  2700. {
  2701. struct iwl_priv *priv = hw->priv;
  2702. IWL_DEBUG_MAC80211(priv, "enter\n");
  2703. if (!priv->is_open) {
  2704. IWL_DEBUG_MAC80211(priv, "leave - skip\n");
  2705. return;
  2706. }
  2707. priv->is_open = 0;
  2708. if (iwl_is_ready_rf(priv)) {
  2709. /* stop mac, cancel any scan request and clear
  2710. * RXON_FILTER_ASSOC_MSK BIT
  2711. */
  2712. mutex_lock(&priv->mutex);
  2713. iwl_scan_cancel_timeout(priv, 100);
  2714. mutex_unlock(&priv->mutex);
  2715. }
  2716. iwl3945_down(priv);
  2717. flush_workqueue(priv->workqueue);
  2718. /* start polling the killswitch state again */
  2719. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2720. round_jiffies_relative(2 * HZ));
  2721. IWL_DEBUG_MAC80211(priv, "leave\n");
  2722. }
  2723. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2724. {
  2725. struct iwl_priv *priv = hw->priv;
  2726. IWL_DEBUG_MAC80211(priv, "enter\n");
  2727. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2728. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2729. if (iwl3945_tx_skb(priv, skb))
  2730. dev_kfree_skb_any(skb);
  2731. IWL_DEBUG_MAC80211(priv, "leave\n");
  2732. return NETDEV_TX_OK;
  2733. }
  2734. void iwl3945_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2735. {
  2736. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2737. int rc = 0;
  2738. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2739. return;
  2740. /* The following should be done only at AP bring up */
  2741. if (!(iwl_is_associated(priv, IWL_RXON_CTX_BSS))) {
  2742. /* RXON - unassoc (to set timing command) */
  2743. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2744. iwlcore_commit_rxon(priv, ctx);
  2745. /* RXON Timing */
  2746. rc = iwl_send_rxon_timing(priv, vif);
  2747. if (rc)
  2748. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2749. "Attempting to continue.\n");
  2750. ctx->staging.assoc_id = 0;
  2751. if (vif->bss_conf.use_short_preamble)
  2752. ctx->staging.flags |=
  2753. RXON_FLG_SHORT_PREAMBLE_MSK;
  2754. else
  2755. ctx->staging.flags &=
  2756. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2757. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2758. if (vif->bss_conf.use_short_slot)
  2759. ctx->staging.flags |=
  2760. RXON_FLG_SHORT_SLOT_MSK;
  2761. else
  2762. ctx->staging.flags &=
  2763. ~RXON_FLG_SHORT_SLOT_MSK;
  2764. }
  2765. /* restore RXON assoc */
  2766. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2767. iwlcore_commit_rxon(priv, ctx);
  2768. }
  2769. iwl3945_send_beacon_cmd(priv);
  2770. /* FIXME - we need to add code here to detect a totally new
  2771. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2772. * clear sta table, add BCAST sta... */
  2773. }
  2774. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2775. struct ieee80211_vif *vif,
  2776. struct ieee80211_sta *sta,
  2777. struct ieee80211_key_conf *key)
  2778. {
  2779. struct iwl_priv *priv = hw->priv;
  2780. int ret = 0;
  2781. u8 sta_id = IWL_INVALID_STATION;
  2782. u8 static_key;
  2783. IWL_DEBUG_MAC80211(priv, "enter\n");
  2784. if (iwl3945_mod_params.sw_crypto) {
  2785. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2786. return -EOPNOTSUPP;
  2787. }
  2788. static_key = !iwl_is_associated(priv, IWL_RXON_CTX_BSS);
  2789. if (!static_key) {
  2790. sta_id = iwl_sta_id_or_broadcast(
  2791. priv, &priv->contexts[IWL_RXON_CTX_BSS], sta);
  2792. if (sta_id == IWL_INVALID_STATION)
  2793. return -EINVAL;
  2794. }
  2795. mutex_lock(&priv->mutex);
  2796. iwl_scan_cancel_timeout(priv, 100);
  2797. switch (cmd) {
  2798. case SET_KEY:
  2799. if (static_key)
  2800. ret = iwl3945_set_static_key(priv, key);
  2801. else
  2802. ret = iwl3945_set_dynamic_key(priv, key, sta_id);
  2803. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2804. break;
  2805. case DISABLE_KEY:
  2806. if (static_key)
  2807. ret = iwl3945_remove_static_key(priv);
  2808. else
  2809. ret = iwl3945_clear_sta_key_info(priv, sta_id);
  2810. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2811. break;
  2812. default:
  2813. ret = -EINVAL;
  2814. }
  2815. mutex_unlock(&priv->mutex);
  2816. IWL_DEBUG_MAC80211(priv, "leave\n");
  2817. return ret;
  2818. }
  2819. static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
  2820. struct ieee80211_vif *vif,
  2821. struct ieee80211_sta *sta)
  2822. {
  2823. struct iwl_priv *priv = hw->priv;
  2824. struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv;
  2825. int ret;
  2826. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2827. u8 sta_id;
  2828. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2829. sta->addr);
  2830. mutex_lock(&priv->mutex);
  2831. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2832. sta->addr);
  2833. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2834. ret = iwl_add_station_common(priv, &priv->contexts[IWL_RXON_CTX_BSS],
  2835. sta->addr, is_ap, sta, &sta_id);
  2836. if (ret) {
  2837. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2838. sta->addr, ret);
  2839. /* Should we return success if return code is EEXIST ? */
  2840. mutex_unlock(&priv->mutex);
  2841. return ret;
  2842. }
  2843. sta_priv->common.sta_id = sta_id;
  2844. /* Initialize rate scaling */
  2845. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2846. sta->addr);
  2847. iwl3945_rs_rate_init(priv, sta, sta_id);
  2848. mutex_unlock(&priv->mutex);
  2849. return 0;
  2850. }
  2851. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  2852. unsigned int changed_flags,
  2853. unsigned int *total_flags,
  2854. u64 multicast)
  2855. {
  2856. struct iwl_priv *priv = hw->priv;
  2857. __le32 filter_or = 0, filter_nand = 0;
  2858. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2859. #define CHK(test, flag) do { \
  2860. if (*total_flags & (test)) \
  2861. filter_or |= (flag); \
  2862. else \
  2863. filter_nand |= (flag); \
  2864. } while (0)
  2865. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2866. changed_flags, *total_flags);
  2867. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2868. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  2869. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2870. #undef CHK
  2871. mutex_lock(&priv->mutex);
  2872. ctx->staging.filter_flags &= ~filter_nand;
  2873. ctx->staging.filter_flags |= filter_or;
  2874. /*
  2875. * Committing directly here breaks for some reason,
  2876. * but we'll eventually commit the filter flags
  2877. * change anyway.
  2878. */
  2879. mutex_unlock(&priv->mutex);
  2880. /*
  2881. * Receiving all multicast frames is always enabled by the
  2882. * default flags setup in iwl_connection_init_rx_config()
  2883. * since we currently do not support programming multicast
  2884. * filters into the device.
  2885. */
  2886. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2887. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2888. }
  2889. /*****************************************************************************
  2890. *
  2891. * sysfs attributes
  2892. *
  2893. *****************************************************************************/
  2894. #ifdef CONFIG_IWLWIFI_DEBUG
  2895. /*
  2896. * The following adds a new attribute to the sysfs representation
  2897. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  2898. * used for controlling the debug level.
  2899. *
  2900. * See the level definitions in iwl for details.
  2901. *
  2902. * The debug_level being managed using sysfs below is a per device debug
  2903. * level that is used instead of the global debug level if it (the per
  2904. * device debug level) is set.
  2905. */
  2906. static ssize_t show_debug_level(struct device *d,
  2907. struct device_attribute *attr, char *buf)
  2908. {
  2909. struct iwl_priv *priv = dev_get_drvdata(d);
  2910. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2911. }
  2912. static ssize_t store_debug_level(struct device *d,
  2913. struct device_attribute *attr,
  2914. const char *buf, size_t count)
  2915. {
  2916. struct iwl_priv *priv = dev_get_drvdata(d);
  2917. unsigned long val;
  2918. int ret;
  2919. ret = strict_strtoul(buf, 0, &val);
  2920. if (ret)
  2921. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  2922. else {
  2923. priv->debug_level = val;
  2924. if (iwl_alloc_traffic_mem(priv))
  2925. IWL_ERR(priv,
  2926. "Not enough memory to generate traffic log\n");
  2927. }
  2928. return strnlen(buf, count);
  2929. }
  2930. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2931. show_debug_level, store_debug_level);
  2932. #endif /* CONFIG_IWLWIFI_DEBUG */
  2933. static ssize_t show_temperature(struct device *d,
  2934. struct device_attribute *attr, char *buf)
  2935. {
  2936. struct iwl_priv *priv = dev_get_drvdata(d);
  2937. if (!iwl_is_alive(priv))
  2938. return -EAGAIN;
  2939. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  2940. }
  2941. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2942. static ssize_t show_tx_power(struct device *d,
  2943. struct device_attribute *attr, char *buf)
  2944. {
  2945. struct iwl_priv *priv = dev_get_drvdata(d);
  2946. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2947. }
  2948. static ssize_t store_tx_power(struct device *d,
  2949. struct device_attribute *attr,
  2950. const char *buf, size_t count)
  2951. {
  2952. struct iwl_priv *priv = dev_get_drvdata(d);
  2953. char *p = (char *)buf;
  2954. u32 val;
  2955. val = simple_strtoul(p, &p, 10);
  2956. if (p == buf)
  2957. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  2958. else
  2959. iwl3945_hw_reg_set_txpower(priv, val);
  2960. return count;
  2961. }
  2962. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2963. static ssize_t show_flags(struct device *d,
  2964. struct device_attribute *attr, char *buf)
  2965. {
  2966. struct iwl_priv *priv = dev_get_drvdata(d);
  2967. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2968. return sprintf(buf, "0x%04X\n", ctx->active.flags);
  2969. }
  2970. static ssize_t store_flags(struct device *d,
  2971. struct device_attribute *attr,
  2972. const char *buf, size_t count)
  2973. {
  2974. struct iwl_priv *priv = dev_get_drvdata(d);
  2975. u32 flags = simple_strtoul(buf, NULL, 0);
  2976. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2977. mutex_lock(&priv->mutex);
  2978. if (le32_to_cpu(ctx->staging.flags) != flags) {
  2979. /* Cancel any currently running scans... */
  2980. if (iwl_scan_cancel_timeout(priv, 100))
  2981. IWL_WARN(priv, "Could not cancel scan.\n");
  2982. else {
  2983. IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
  2984. flags);
  2985. ctx->staging.flags = cpu_to_le32(flags);
  2986. iwlcore_commit_rxon(priv, ctx);
  2987. }
  2988. }
  2989. mutex_unlock(&priv->mutex);
  2990. return count;
  2991. }
  2992. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2993. static ssize_t show_filter_flags(struct device *d,
  2994. struct device_attribute *attr, char *buf)
  2995. {
  2996. struct iwl_priv *priv = dev_get_drvdata(d);
  2997. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2998. return sprintf(buf, "0x%04X\n",
  2999. le32_to_cpu(ctx->active.filter_flags));
  3000. }
  3001. static ssize_t store_filter_flags(struct device *d,
  3002. struct device_attribute *attr,
  3003. const char *buf, size_t count)
  3004. {
  3005. struct iwl_priv *priv = dev_get_drvdata(d);
  3006. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  3007. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  3008. mutex_lock(&priv->mutex);
  3009. if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
  3010. /* Cancel any currently running scans... */
  3011. if (iwl_scan_cancel_timeout(priv, 100))
  3012. IWL_WARN(priv, "Could not cancel scan.\n");
  3013. else {
  3014. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  3015. "0x%04X\n", filter_flags);
  3016. ctx->staging.filter_flags =
  3017. cpu_to_le32(filter_flags);
  3018. iwlcore_commit_rxon(priv, ctx);
  3019. }
  3020. }
  3021. mutex_unlock(&priv->mutex);
  3022. return count;
  3023. }
  3024. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  3025. store_filter_flags);
  3026. static ssize_t show_measurement(struct device *d,
  3027. struct device_attribute *attr, char *buf)
  3028. {
  3029. struct iwl_priv *priv = dev_get_drvdata(d);
  3030. struct iwl_spectrum_notification measure_report;
  3031. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  3032. u8 *data = (u8 *)&measure_report;
  3033. unsigned long flags;
  3034. spin_lock_irqsave(&priv->lock, flags);
  3035. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  3036. spin_unlock_irqrestore(&priv->lock, flags);
  3037. return 0;
  3038. }
  3039. memcpy(&measure_report, &priv->measure_report, size);
  3040. priv->measurement_status = 0;
  3041. spin_unlock_irqrestore(&priv->lock, flags);
  3042. while (size && (PAGE_SIZE - len)) {
  3043. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  3044. PAGE_SIZE - len, 1);
  3045. len = strlen(buf);
  3046. if (PAGE_SIZE - len)
  3047. buf[len++] = '\n';
  3048. ofs += 16;
  3049. size -= min(size, 16U);
  3050. }
  3051. return len;
  3052. }
  3053. static ssize_t store_measurement(struct device *d,
  3054. struct device_attribute *attr,
  3055. const char *buf, size_t count)
  3056. {
  3057. struct iwl_priv *priv = dev_get_drvdata(d);
  3058. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  3059. struct ieee80211_measurement_params params = {
  3060. .channel = le16_to_cpu(ctx->active.channel),
  3061. .start_time = cpu_to_le64(priv->_3945.last_tsf),
  3062. .duration = cpu_to_le16(1),
  3063. };
  3064. u8 type = IWL_MEASURE_BASIC;
  3065. u8 buffer[32];
  3066. u8 channel;
  3067. if (count) {
  3068. char *p = buffer;
  3069. strncpy(buffer, buf, min(sizeof(buffer), count));
  3070. channel = simple_strtoul(p, NULL, 0);
  3071. if (channel)
  3072. params.channel = channel;
  3073. p = buffer;
  3074. while (*p && *p != ' ')
  3075. p++;
  3076. if (*p)
  3077. type = simple_strtoul(p + 1, NULL, 0);
  3078. }
  3079. IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
  3080. "channel %d (for '%s')\n", type, params.channel, buf);
  3081. iwl3945_get_measurement(priv, &params, type);
  3082. return count;
  3083. }
  3084. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  3085. show_measurement, store_measurement);
  3086. static ssize_t store_retry_rate(struct device *d,
  3087. struct device_attribute *attr,
  3088. const char *buf, size_t count)
  3089. {
  3090. struct iwl_priv *priv = dev_get_drvdata(d);
  3091. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  3092. if (priv->retry_rate <= 0)
  3093. priv->retry_rate = 1;
  3094. return count;
  3095. }
  3096. static ssize_t show_retry_rate(struct device *d,
  3097. struct device_attribute *attr, char *buf)
  3098. {
  3099. struct iwl_priv *priv = dev_get_drvdata(d);
  3100. return sprintf(buf, "%d", priv->retry_rate);
  3101. }
  3102. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  3103. store_retry_rate);
  3104. static ssize_t show_channels(struct device *d,
  3105. struct device_attribute *attr, char *buf)
  3106. {
  3107. /* all this shit doesn't belong into sysfs anyway */
  3108. return 0;
  3109. }
  3110. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  3111. static ssize_t show_antenna(struct device *d,
  3112. struct device_attribute *attr, char *buf)
  3113. {
  3114. struct iwl_priv *priv = dev_get_drvdata(d);
  3115. if (!iwl_is_alive(priv))
  3116. return -EAGAIN;
  3117. return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
  3118. }
  3119. static ssize_t store_antenna(struct device *d,
  3120. struct device_attribute *attr,
  3121. const char *buf, size_t count)
  3122. {
  3123. struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
  3124. int ant;
  3125. if (count == 0)
  3126. return 0;
  3127. if (sscanf(buf, "%1i", &ant) != 1) {
  3128. IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
  3129. return count;
  3130. }
  3131. if ((ant >= 0) && (ant <= 2)) {
  3132. IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
  3133. iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
  3134. } else
  3135. IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
  3136. return count;
  3137. }
  3138. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  3139. static ssize_t show_status(struct device *d,
  3140. struct device_attribute *attr, char *buf)
  3141. {
  3142. struct iwl_priv *priv = dev_get_drvdata(d);
  3143. if (!iwl_is_alive(priv))
  3144. return -EAGAIN;
  3145. return sprintf(buf, "0x%08x\n", (int)priv->status);
  3146. }
  3147. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  3148. static ssize_t dump_error_log(struct device *d,
  3149. struct device_attribute *attr,
  3150. const char *buf, size_t count)
  3151. {
  3152. struct iwl_priv *priv = dev_get_drvdata(d);
  3153. char *p = (char *)buf;
  3154. if (p[0] == '1')
  3155. iwl3945_dump_nic_error_log(priv);
  3156. return strnlen(buf, count);
  3157. }
  3158. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  3159. /*****************************************************************************
  3160. *
  3161. * driver setup and tear down
  3162. *
  3163. *****************************************************************************/
  3164. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  3165. {
  3166. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3167. init_waitqueue_head(&priv->wait_command_queue);
  3168. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  3169. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  3170. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  3171. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  3172. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  3173. INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
  3174. iwl_setup_scan_deferred_work(priv);
  3175. iwl3945_hw_setup_deferred_work(priv);
  3176. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3177. init_timer(&priv->monitor_recover);
  3178. priv->monitor_recover.data = (unsigned long)priv;
  3179. priv->monitor_recover.function =
  3180. priv->cfg->ops->lib->recover_from_tx_stall;
  3181. }
  3182. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3183. iwl3945_irq_tasklet, (unsigned long)priv);
  3184. }
  3185. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  3186. {
  3187. iwl3945_hw_cancel_deferred_work(priv);
  3188. cancel_delayed_work_sync(&priv->init_alive_start);
  3189. cancel_delayed_work(&priv->scan_check);
  3190. cancel_delayed_work(&priv->alive_start);
  3191. cancel_work_sync(&priv->start_internal_scan);
  3192. cancel_work_sync(&priv->beacon_update);
  3193. }
  3194. static struct attribute *iwl3945_sysfs_entries[] = {
  3195. &dev_attr_antenna.attr,
  3196. &dev_attr_channels.attr,
  3197. &dev_attr_dump_errors.attr,
  3198. &dev_attr_flags.attr,
  3199. &dev_attr_filter_flags.attr,
  3200. &dev_attr_measurement.attr,
  3201. &dev_attr_retry_rate.attr,
  3202. &dev_attr_status.attr,
  3203. &dev_attr_temperature.attr,
  3204. &dev_attr_tx_power.attr,
  3205. #ifdef CONFIG_IWLWIFI_DEBUG
  3206. &dev_attr_debug_level.attr,
  3207. #endif
  3208. NULL
  3209. };
  3210. static struct attribute_group iwl3945_attribute_group = {
  3211. .name = NULL, /* put in device directory */
  3212. .attrs = iwl3945_sysfs_entries,
  3213. };
  3214. static struct ieee80211_ops iwl3945_hw_ops = {
  3215. .tx = iwl3945_mac_tx,
  3216. .start = iwl3945_mac_start,
  3217. .stop = iwl3945_mac_stop,
  3218. .add_interface = iwl_mac_add_interface,
  3219. .remove_interface = iwl_mac_remove_interface,
  3220. .config = iwl_mac_config,
  3221. .configure_filter = iwl3945_configure_filter,
  3222. .set_key = iwl3945_mac_set_key,
  3223. .conf_tx = iwl_mac_conf_tx,
  3224. .reset_tsf = iwl_mac_reset_tsf,
  3225. .bss_info_changed = iwl_bss_info_changed,
  3226. .hw_scan = iwl_mac_hw_scan,
  3227. .sta_add = iwl3945_mac_sta_add,
  3228. .sta_remove = iwl_mac_sta_remove,
  3229. .tx_last_beacon = iwl_mac_tx_last_beacon,
  3230. };
  3231. static int iwl3945_init_drv(struct iwl_priv *priv)
  3232. {
  3233. int ret;
  3234. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3235. priv->retry_rate = 1;
  3236. priv->ibss_beacon = NULL;
  3237. spin_lock_init(&priv->sta_lock);
  3238. spin_lock_init(&priv->hcmd_lock);
  3239. INIT_LIST_HEAD(&priv->free_frames);
  3240. mutex_init(&priv->mutex);
  3241. mutex_init(&priv->sync_cmd_mutex);
  3242. priv->ieee_channels = NULL;
  3243. priv->ieee_rates = NULL;
  3244. priv->band = IEEE80211_BAND_2GHZ;
  3245. priv->iw_mode = NL80211_IFTYPE_STATION;
  3246. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3247. priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
  3248. if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
  3249. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3250. eeprom->version);
  3251. ret = -EINVAL;
  3252. goto err;
  3253. }
  3254. ret = iwl_init_channel_map(priv);
  3255. if (ret) {
  3256. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3257. goto err;
  3258. }
  3259. /* Set up txpower settings in driver for all channels */
  3260. if (iwl3945_txpower_set_from_eeprom(priv)) {
  3261. ret = -EIO;
  3262. goto err_free_channel_map;
  3263. }
  3264. ret = iwlcore_init_geos(priv);
  3265. if (ret) {
  3266. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3267. goto err_free_channel_map;
  3268. }
  3269. iwl3945_init_hw_rates(priv, priv->ieee_rates);
  3270. return 0;
  3271. err_free_channel_map:
  3272. iwl_free_channel_map(priv);
  3273. err:
  3274. return ret;
  3275. }
  3276. #define IWL3945_MAX_PROBE_REQUEST 200
  3277. static int iwl3945_setup_mac(struct iwl_priv *priv)
  3278. {
  3279. int ret;
  3280. struct ieee80211_hw *hw = priv->hw;
  3281. hw->rate_control_algorithm = "iwl-3945-rs";
  3282. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  3283. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  3284. /* Tell mac80211 our characteristics */
  3285. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  3286. IEEE80211_HW_SPECTRUM_MGMT;
  3287. if (!priv->cfg->broken_powersave)
  3288. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  3289. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  3290. hw->wiphy->interface_modes =
  3291. BIT(NL80211_IFTYPE_STATION) |
  3292. BIT(NL80211_IFTYPE_ADHOC);
  3293. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  3294. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  3295. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
  3296. /* we create the 802.11 header and a zero-length SSID element */
  3297. hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2;
  3298. /* Default value; 4 EDCA QOS priorities */
  3299. hw->queues = 4;
  3300. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3301. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3302. &priv->bands[IEEE80211_BAND_2GHZ];
  3303. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3304. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3305. &priv->bands[IEEE80211_BAND_5GHZ];
  3306. ret = ieee80211_register_hw(priv->hw);
  3307. if (ret) {
  3308. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  3309. return ret;
  3310. }
  3311. priv->mac80211_registered = 1;
  3312. return 0;
  3313. }
  3314. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3315. {
  3316. int err = 0, i;
  3317. struct iwl_priv *priv;
  3318. struct ieee80211_hw *hw;
  3319. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3320. struct iwl3945_eeprom *eeprom;
  3321. unsigned long flags;
  3322. /***********************
  3323. * 1. Allocating HW data
  3324. * ********************/
  3325. /* mac80211 allocates memory for this device instance, including
  3326. * space for this driver's private structure */
  3327. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  3328. if (hw == NULL) {
  3329. pr_err("Can not allocate network device\n");
  3330. err = -ENOMEM;
  3331. goto out;
  3332. }
  3333. priv = hw->priv;
  3334. SET_IEEE80211_DEV(hw, &pdev->dev);
  3335. priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
  3336. /* 3945 has only one valid context */
  3337. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  3338. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  3339. priv->contexts[i].ctxid = i;
  3340. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  3341. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  3342. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  3343. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  3344. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  3345. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  3346. /*
  3347. * Disabling hardware scan means that mac80211 will perform scans
  3348. * "the hard way", rather than using device's scan.
  3349. */
  3350. if (iwl3945_mod_params.disable_hw_scan) {
  3351. IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
  3352. iwl3945_hw_ops.hw_scan = NULL;
  3353. }
  3354. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3355. priv->cfg = cfg;
  3356. priv->pci_dev = pdev;
  3357. priv->inta_mask = CSR_INI_SET_MASK;
  3358. if (iwl_alloc_traffic_mem(priv))
  3359. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3360. /***************************
  3361. * 2. Initializing PCI bus
  3362. * *************************/
  3363. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3364. PCIE_LINK_STATE_CLKPM);
  3365. if (pci_enable_device(pdev)) {
  3366. err = -ENODEV;
  3367. goto out_ieee80211_free_hw;
  3368. }
  3369. pci_set_master(pdev);
  3370. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3371. if (!err)
  3372. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3373. if (err) {
  3374. IWL_WARN(priv, "No suitable DMA available.\n");
  3375. goto out_pci_disable_device;
  3376. }
  3377. pci_set_drvdata(pdev, priv);
  3378. err = pci_request_regions(pdev, DRV_NAME);
  3379. if (err)
  3380. goto out_pci_disable_device;
  3381. /***********************
  3382. * 3. Read REV Register
  3383. * ********************/
  3384. priv->hw_base = pci_iomap(pdev, 0, 0);
  3385. if (!priv->hw_base) {
  3386. err = -ENODEV;
  3387. goto out_pci_release_regions;
  3388. }
  3389. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3390. (unsigned long long) pci_resource_len(pdev, 0));
  3391. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3392. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3393. * PCI Tx retries from interfering with C3 CPU state */
  3394. pci_write_config_byte(pdev, 0x41, 0x00);
  3395. /* these spin locks will be used in apm_ops.init and EEPROM access
  3396. * we should init now
  3397. */
  3398. spin_lock_init(&priv->reg_lock);
  3399. spin_lock_init(&priv->lock);
  3400. /*
  3401. * stop and reset the on-board processor just in case it is in a
  3402. * strange state ... like being left stranded by a primary kernel
  3403. * and this is now the kdump kernel trying to start up
  3404. */
  3405. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3406. /***********************
  3407. * 4. Read EEPROM
  3408. * ********************/
  3409. /* Read the EEPROM */
  3410. err = iwl_eeprom_init(priv);
  3411. if (err) {
  3412. IWL_ERR(priv, "Unable to init EEPROM\n");
  3413. goto out_iounmap;
  3414. }
  3415. /* MAC Address location in EEPROM same for 3945/4965 */
  3416. eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3417. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address);
  3418. SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address);
  3419. /***********************
  3420. * 5. Setup HW Constants
  3421. * ********************/
  3422. /* Device-specific setup */
  3423. if (iwl3945_hw_set_hw_params(priv)) {
  3424. IWL_ERR(priv, "failed to set hw settings\n");
  3425. goto out_eeprom_free;
  3426. }
  3427. /***********************
  3428. * 6. Setup priv
  3429. * ********************/
  3430. err = iwl3945_init_drv(priv);
  3431. if (err) {
  3432. IWL_ERR(priv, "initializing driver failed\n");
  3433. goto out_unset_hw_params;
  3434. }
  3435. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  3436. priv->cfg->name);
  3437. /***********************
  3438. * 7. Setup Services
  3439. * ********************/
  3440. spin_lock_irqsave(&priv->lock, flags);
  3441. iwl_disable_interrupts(priv);
  3442. spin_unlock_irqrestore(&priv->lock, flags);
  3443. pci_enable_msi(priv->pci_dev);
  3444. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3445. IRQF_SHARED, DRV_NAME, priv);
  3446. if (err) {
  3447. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3448. goto out_disable_msi;
  3449. }
  3450. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3451. if (err) {
  3452. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3453. goto out_release_irq;
  3454. }
  3455. iwl_set_rxon_channel(priv,
  3456. &priv->bands[IEEE80211_BAND_2GHZ].channels[5],
  3457. &priv->contexts[IWL_RXON_CTX_BSS]);
  3458. iwl3945_setup_deferred_work(priv);
  3459. iwl3945_setup_rx_handlers(priv);
  3460. iwl_power_initialize(priv);
  3461. /*********************************
  3462. * 8. Setup and Register mac80211
  3463. * *******************************/
  3464. iwl_enable_interrupts(priv);
  3465. err = iwl3945_setup_mac(priv);
  3466. if (err)
  3467. goto out_remove_sysfs;
  3468. err = iwl_dbgfs_register(priv, DRV_NAME);
  3469. if (err)
  3470. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  3471. /* Start monitoring the killswitch */
  3472. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  3473. 2 * HZ);
  3474. return 0;
  3475. out_remove_sysfs:
  3476. destroy_workqueue(priv->workqueue);
  3477. priv->workqueue = NULL;
  3478. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3479. out_release_irq:
  3480. free_irq(priv->pci_dev->irq, priv);
  3481. out_disable_msi:
  3482. pci_disable_msi(priv->pci_dev);
  3483. iwlcore_free_geos(priv);
  3484. iwl_free_channel_map(priv);
  3485. out_unset_hw_params:
  3486. iwl3945_unset_hw_params(priv);
  3487. out_eeprom_free:
  3488. iwl_eeprom_free(priv);
  3489. out_iounmap:
  3490. pci_iounmap(pdev, priv->hw_base);
  3491. out_pci_release_regions:
  3492. pci_release_regions(pdev);
  3493. out_pci_disable_device:
  3494. pci_set_drvdata(pdev, NULL);
  3495. pci_disable_device(pdev);
  3496. out_ieee80211_free_hw:
  3497. iwl_free_traffic_mem(priv);
  3498. ieee80211_free_hw(priv->hw);
  3499. out:
  3500. return err;
  3501. }
  3502. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  3503. {
  3504. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3505. unsigned long flags;
  3506. if (!priv)
  3507. return;
  3508. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3509. iwl_dbgfs_unregister(priv);
  3510. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3511. if (priv->mac80211_registered) {
  3512. ieee80211_unregister_hw(priv->hw);
  3513. priv->mac80211_registered = 0;
  3514. } else {
  3515. iwl3945_down(priv);
  3516. }
  3517. /*
  3518. * Make sure device is reset to low power before unloading driver.
  3519. * This may be redundant with iwl_down(), but there are paths to
  3520. * run iwl_down() without calling apm_ops.stop(), and there are
  3521. * paths to avoid running iwl_down() at all before leaving driver.
  3522. * This (inexpensive) call *makes sure* device is reset.
  3523. */
  3524. priv->cfg->ops->lib->apm_ops.stop(priv);
  3525. /* make sure we flush any pending irq or
  3526. * tasklet for the driver
  3527. */
  3528. spin_lock_irqsave(&priv->lock, flags);
  3529. iwl_disable_interrupts(priv);
  3530. spin_unlock_irqrestore(&priv->lock, flags);
  3531. iwl_synchronize_irq(priv);
  3532. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3533. cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
  3534. iwl3945_dealloc_ucode_pci(priv);
  3535. if (priv->rxq.bd)
  3536. iwl3945_rx_queue_free(priv, &priv->rxq);
  3537. iwl3945_hw_txq_ctx_free(priv);
  3538. iwl3945_unset_hw_params(priv);
  3539. /*netif_stop_queue(dev); */
  3540. flush_workqueue(priv->workqueue);
  3541. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  3542. * priv->workqueue... so we can't take down the workqueue
  3543. * until now... */
  3544. destroy_workqueue(priv->workqueue);
  3545. priv->workqueue = NULL;
  3546. iwl_free_traffic_mem(priv);
  3547. free_irq(pdev->irq, priv);
  3548. pci_disable_msi(pdev);
  3549. pci_iounmap(pdev, priv->hw_base);
  3550. pci_release_regions(pdev);
  3551. pci_disable_device(pdev);
  3552. pci_set_drvdata(pdev, NULL);
  3553. iwl_free_channel_map(priv);
  3554. iwlcore_free_geos(priv);
  3555. kfree(priv->scan_cmd);
  3556. if (priv->ibss_beacon)
  3557. dev_kfree_skb(priv->ibss_beacon);
  3558. ieee80211_free_hw(priv->hw);
  3559. }
  3560. /*****************************************************************************
  3561. *
  3562. * driver and module entry point
  3563. *
  3564. *****************************************************************************/
  3565. static struct pci_driver iwl3945_driver = {
  3566. .name = DRV_NAME,
  3567. .id_table = iwl3945_hw_card_ids,
  3568. .probe = iwl3945_pci_probe,
  3569. .remove = __devexit_p(iwl3945_pci_remove),
  3570. #ifdef CONFIG_PM
  3571. .suspend = iwl_pci_suspend,
  3572. .resume = iwl_pci_resume,
  3573. #endif
  3574. };
  3575. static int __init iwl3945_init(void)
  3576. {
  3577. int ret;
  3578. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3579. pr_info(DRV_COPYRIGHT "\n");
  3580. ret = iwl3945_rate_control_register();
  3581. if (ret) {
  3582. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3583. return ret;
  3584. }
  3585. ret = pci_register_driver(&iwl3945_driver);
  3586. if (ret) {
  3587. pr_err("Unable to initialize PCI module\n");
  3588. goto error_register;
  3589. }
  3590. return ret;
  3591. error_register:
  3592. iwl3945_rate_control_unregister();
  3593. return ret;
  3594. }
  3595. static void __exit iwl3945_exit(void)
  3596. {
  3597. pci_unregister_driver(&iwl3945_driver);
  3598. iwl3945_rate_control_unregister();
  3599. }
  3600. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  3601. module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
  3602. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3603. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
  3604. MODULE_PARM_DESC(swcrypto,
  3605. "using software crypto (default 1 [software])\n");
  3606. #ifdef CONFIG_IWLWIFI_DEBUG
  3607. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3608. MODULE_PARM_DESC(debug, "debug output mask");
  3609. #endif
  3610. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
  3611. int, S_IRUGO);
  3612. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3613. module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
  3614. MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
  3615. module_exit(iwl3945_exit);
  3616. module_init(iwl3945_init);