ql4_mbx.c 36 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine isssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. /* Make sure that pointers are valid */
  33. if (!mbx_cmd || !mbx_sts) {
  34. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  35. "pointer\n", ha->host_no, __func__));
  36. return status;
  37. }
  38. if (is_qla8022(ha) &&
  39. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  40. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: prematurely "
  41. "completing mbx cmd as firmware recovery detected\n",
  42. ha->host_no, __func__));
  43. return status;
  44. }
  45. if ((is_aer_supported(ha)) &&
  46. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  47. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  48. "timeout MBX Exiting.\n", ha->host_no, __func__));
  49. return status;
  50. }
  51. /* Mailbox code active */
  52. wait_count = MBOX_TOV * 100;
  53. while (wait_count--) {
  54. mutex_lock(&ha->mbox_sem);
  55. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  56. set_bit(AF_MBOX_COMMAND, &ha->flags);
  57. mutex_unlock(&ha->mbox_sem);
  58. break;
  59. }
  60. mutex_unlock(&ha->mbox_sem);
  61. if (!wait_count) {
  62. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  63. ha->host_no, __func__));
  64. return status;
  65. }
  66. msleep(10);
  67. }
  68. /* To prevent overwriting mailbox registers for a command that has
  69. * not yet been serviced, check to see if an active command
  70. * (AEN, IOCB, etc.) is interrupting, then service it.
  71. * -----------------------------------------------------------------
  72. */
  73. spin_lock_irqsave(&ha->hardware_lock, flags);
  74. if (is_qla8022(ha)) {
  75. intr_status = readl(&ha->qla4_8xxx_reg->host_int);
  76. if (intr_status & ISRX_82XX_RISC_INT) {
  77. /* Service existing interrupt */
  78. DEBUG2(printk("scsi%ld: %s: "
  79. "servicing existing interrupt\n",
  80. ha->host_no, __func__));
  81. intr_status = readl(&ha->qla4_8xxx_reg->host_status);
  82. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  83. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  84. if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  85. test_bit(AF_INTx_ENABLED, &ha->flags))
  86. qla4_8xxx_wr_32(ha,
  87. ha->nx_legacy_intr.tgt_mask_reg,
  88. 0xfbff);
  89. }
  90. } else {
  91. intr_status = readl(&ha->reg->ctrl_status);
  92. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  93. /* Service existing interrupt */
  94. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  95. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  96. }
  97. }
  98. ha->mbox_status_count = outCount;
  99. for (i = 0; i < outCount; i++)
  100. ha->mbox_status[i] = 0;
  101. if (is_qla8022(ha)) {
  102. /* Load all mailbox registers, except mailbox 0. */
  103. DEBUG5(
  104. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  105. for (i = 0; i < inCount; i++)
  106. printk("mb%d=%04x ", i, mbx_cmd[i]);
  107. printk("\n"));
  108. for (i = 1; i < inCount; i++)
  109. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  110. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  111. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  112. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  113. } else {
  114. /* Load all mailbox registers, except mailbox 0. */
  115. for (i = 1; i < inCount; i++)
  116. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  117. /* Wakeup firmware */
  118. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  119. readl(&ha->reg->mailbox[0]);
  120. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  121. readl(&ha->reg->ctrl_status);
  122. }
  123. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  124. /* Wait for completion */
  125. /*
  126. * If we don't want status, don't wait for the mailbox command to
  127. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  128. * you must poll the inbound Interrupt Mask for completion.
  129. */
  130. if (outCount == 0) {
  131. status = QLA_SUCCESS;
  132. goto mbox_exit;
  133. }
  134. /*
  135. * Wait for completion: Poll or completion queue
  136. */
  137. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  138. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  139. test_bit(AF_ONLINE, &ha->flags) &&
  140. !test_bit(AF_HBA_GOING_AWAY, &ha->flags)) {
  141. /* Do not poll for completion. Use completion queue */
  142. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  143. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  144. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  145. } else {
  146. /* Poll for command to complete */
  147. wait_count = jiffies + MBOX_TOV * HZ;
  148. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  149. if (time_after_eq(jiffies, wait_count))
  150. break;
  151. /*
  152. * Service the interrupt.
  153. * The ISR will save the mailbox status registers
  154. * to a temporary storage location in the adapter
  155. * structure.
  156. */
  157. spin_lock_irqsave(&ha->hardware_lock, flags);
  158. if (is_qla8022(ha)) {
  159. intr_status =
  160. readl(&ha->qla4_8xxx_reg->host_int);
  161. if (intr_status & ISRX_82XX_RISC_INT) {
  162. ha->mbox_status_count = outCount;
  163. intr_status =
  164. readl(&ha->qla4_8xxx_reg->host_status);
  165. ha->isp_ops->interrupt_service_routine(
  166. ha, intr_status);
  167. if (test_bit(AF_INTERRUPTS_ON,
  168. &ha->flags) &&
  169. test_bit(AF_INTx_ENABLED,
  170. &ha->flags))
  171. qla4_8xxx_wr_32(ha,
  172. ha->nx_legacy_intr.tgt_mask_reg,
  173. 0xfbff);
  174. }
  175. } else {
  176. intr_status = readl(&ha->reg->ctrl_status);
  177. if (intr_status & INTR_PENDING) {
  178. /*
  179. * Service the interrupt.
  180. * The ISR will save the mailbox status
  181. * registers to a temporary storage
  182. * location in the adapter structure.
  183. */
  184. ha->mbox_status_count = outCount;
  185. ha->isp_ops->interrupt_service_routine(
  186. ha, intr_status);
  187. }
  188. }
  189. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  190. msleep(10);
  191. }
  192. }
  193. /* Check for mailbox timeout. */
  194. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  195. if (is_qla8022(ha) &&
  196. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  197. DEBUG2(ql4_printk(KERN_INFO, ha,
  198. "scsi%ld: %s: prematurely completing mbx cmd as "
  199. "firmware recovery detected\n",
  200. ha->host_no, __func__));
  201. goto mbox_exit;
  202. }
  203. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  204. " Scheduling Adapter Reset\n", ha->host_no,
  205. mbx_cmd[0]));
  206. ha->mailbox_timeout_count++;
  207. mbx_sts[0] = (-1);
  208. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  209. goto mbox_exit;
  210. }
  211. /*
  212. * Copy the mailbox out registers to the caller's mailbox in/out
  213. * structure.
  214. */
  215. spin_lock_irqsave(&ha->hardware_lock, flags);
  216. for (i = 0; i < outCount; i++)
  217. mbx_sts[i] = ha->mbox_status[i];
  218. /* Set return status and error flags (if applicable). */
  219. switch (ha->mbox_status[0]) {
  220. case MBOX_STS_COMMAND_COMPLETE:
  221. status = QLA_SUCCESS;
  222. break;
  223. case MBOX_STS_INTERMEDIATE_COMPLETION:
  224. status = QLA_SUCCESS;
  225. break;
  226. case MBOX_STS_BUSY:
  227. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  228. ha->host_no, __func__, mbx_cmd[0]));
  229. ha->mailbox_timeout_count++;
  230. break;
  231. default:
  232. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  233. "sts = %08X ****\n", ha->host_no, __func__,
  234. mbx_cmd[0], mbx_sts[0]));
  235. break;
  236. }
  237. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  238. mbox_exit:
  239. mutex_lock(&ha->mbox_sem);
  240. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  241. mutex_unlock(&ha->mbox_sem);
  242. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  243. return status;
  244. }
  245. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  246. {
  247. set_bit(AF_FW_RECOVERY, &ha->flags);
  248. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  249. ha->host_no, __func__);
  250. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  251. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  252. complete(&ha->mbx_intr_comp);
  253. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  254. "recovery, doing premature completion of "
  255. "mbx cmd\n", ha->host_no, __func__);
  256. } else {
  257. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  258. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  259. "recovery, doing premature completion of "
  260. "polling mbx cmd\n", ha->host_no, __func__);
  261. }
  262. }
  263. }
  264. static uint8_t
  265. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  266. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  267. {
  268. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  269. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  270. if (is_qla8022(ha))
  271. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  272. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  273. mbox_cmd[1] = 0;
  274. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  275. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  276. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  277. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  278. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  279. QLA_SUCCESS) {
  280. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  281. "MBOX_CMD_INITIALIZE_FIRMWARE"
  282. " failed w/ status %04X\n",
  283. ha->host_no, __func__, mbox_sts[0]));
  284. return QLA_ERROR;
  285. }
  286. return QLA_SUCCESS;
  287. }
  288. static uint8_t
  289. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  290. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  291. {
  292. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  293. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  294. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  295. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  296. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  297. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  298. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  299. QLA_SUCCESS) {
  300. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  301. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  302. " failed w/ status %04X\n",
  303. ha->host_no, __func__, mbox_sts[0]));
  304. return QLA_ERROR;
  305. }
  306. return QLA_SUCCESS;
  307. }
  308. static void
  309. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  310. struct addr_ctrl_blk *init_fw_cb)
  311. {
  312. /* Save IPv4 Address Info */
  313. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  314. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  315. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  316. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  317. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  318. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  319. if (is_ipv6_enabled(ha)) {
  320. /* Save IPv6 Address */
  321. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  322. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  323. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  324. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  325. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  326. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  327. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  328. init_fw_cb->ipv6_if_id,
  329. min(sizeof(ha->ipv6_link_local_addr)/2,
  330. sizeof(init_fw_cb->ipv6_if_id)));
  331. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  332. min(sizeof(ha->ipv6_addr0),
  333. sizeof(init_fw_cb->ipv6_addr0)));
  334. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  335. min(sizeof(ha->ipv6_addr1),
  336. sizeof(init_fw_cb->ipv6_addr1)));
  337. memcpy(&ha->ipv6_default_router_addr,
  338. init_fw_cb->ipv6_dflt_rtr_addr,
  339. min(sizeof(ha->ipv6_default_router_addr),
  340. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  341. }
  342. }
  343. static uint8_t
  344. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  345. uint32_t *mbox_cmd,
  346. uint32_t *mbox_sts,
  347. struct addr_ctrl_blk *init_fw_cb,
  348. dma_addr_t init_fw_cb_dma)
  349. {
  350. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  351. != QLA_SUCCESS) {
  352. DEBUG2(printk(KERN_WARNING
  353. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  354. ha->host_no, __func__));
  355. return QLA_ERROR;
  356. }
  357. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  358. /* Save some info in adapter structure. */
  359. ha->acb_version = init_fw_cb->acb_version;
  360. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  361. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  362. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  363. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  364. ha->heartbeat_interval = init_fw_cb->hb_interval;
  365. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  366. min(sizeof(ha->name_string),
  367. sizeof(init_fw_cb->iscsi_name)));
  368. /*memcpy(ha->alias, init_fw_cb->Alias,
  369. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  370. /* Save Command Line Paramater info */
  371. ha->discovery_wait = ql4xdiscoverywait;
  372. if (ha->acb_version == ACB_SUPPORTED) {
  373. ha->ipv6_options = init_fw_cb->ipv6_opts;
  374. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  375. }
  376. qla4xxx_update_local_ip(ha, init_fw_cb);
  377. return QLA_SUCCESS;
  378. }
  379. /**
  380. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  381. * @ha: Pointer to host adapter structure.
  382. **/
  383. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  384. {
  385. struct addr_ctrl_blk *init_fw_cb;
  386. dma_addr_t init_fw_cb_dma;
  387. uint32_t mbox_cmd[MBOX_REG_COUNT];
  388. uint32_t mbox_sts[MBOX_REG_COUNT];
  389. int status = QLA_ERROR;
  390. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  391. sizeof(struct addr_ctrl_blk),
  392. &init_fw_cb_dma, GFP_KERNEL);
  393. if (init_fw_cb == NULL) {
  394. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  395. ha->host_no, __func__));
  396. goto exit_init_fw_cb_no_free;
  397. }
  398. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  399. /* Get Initialize Firmware Control Block. */
  400. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  401. memset(&mbox_sts, 0, sizeof(mbox_sts));
  402. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  403. QLA_SUCCESS) {
  404. dma_free_coherent(&ha->pdev->dev,
  405. sizeof(struct addr_ctrl_blk),
  406. init_fw_cb, init_fw_cb_dma);
  407. goto exit_init_fw_cb;
  408. }
  409. /* Initialize request and response queues. */
  410. qla4xxx_init_rings(ha);
  411. /* Fill in the request and response queue information. */
  412. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  413. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  414. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  415. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  416. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  417. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  418. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  419. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  420. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  421. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  422. /* Set up required options. */
  423. init_fw_cb->fw_options |=
  424. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  425. FWOPT_INITIATOR_MODE);
  426. if (is_qla8022(ha))
  427. init_fw_cb->fw_options |=
  428. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  429. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  430. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  431. != QLA_SUCCESS) {
  432. DEBUG2(printk(KERN_WARNING
  433. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  434. ha->host_no, __func__));
  435. goto exit_init_fw_cb;
  436. }
  437. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  438. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  439. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  440. ha->host_no, __func__));
  441. goto exit_init_fw_cb;
  442. }
  443. status = QLA_SUCCESS;
  444. exit_init_fw_cb:
  445. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  446. init_fw_cb, init_fw_cb_dma);
  447. exit_init_fw_cb_no_free:
  448. return status;
  449. }
  450. /**
  451. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  452. * @ha: Pointer to host adapter structure.
  453. **/
  454. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  455. {
  456. struct addr_ctrl_blk *init_fw_cb;
  457. dma_addr_t init_fw_cb_dma;
  458. uint32_t mbox_cmd[MBOX_REG_COUNT];
  459. uint32_t mbox_sts[MBOX_REG_COUNT];
  460. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  461. sizeof(struct addr_ctrl_blk),
  462. &init_fw_cb_dma, GFP_KERNEL);
  463. if (init_fw_cb == NULL) {
  464. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  465. __func__);
  466. return QLA_ERROR;
  467. }
  468. /* Get Initialize Firmware Control Block. */
  469. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  470. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  471. QLA_SUCCESS) {
  472. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  473. ha->host_no, __func__));
  474. dma_free_coherent(&ha->pdev->dev,
  475. sizeof(struct addr_ctrl_blk),
  476. init_fw_cb, init_fw_cb_dma);
  477. return QLA_ERROR;
  478. }
  479. /* Save IP Address. */
  480. qla4xxx_update_local_ip(ha, init_fw_cb);
  481. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  482. init_fw_cb, init_fw_cb_dma);
  483. return QLA_SUCCESS;
  484. }
  485. /**
  486. * qla4xxx_get_firmware_state - gets firmware state of HBA
  487. * @ha: Pointer to host adapter structure.
  488. **/
  489. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  490. {
  491. uint32_t mbox_cmd[MBOX_REG_COUNT];
  492. uint32_t mbox_sts[MBOX_REG_COUNT];
  493. /* Get firmware version */
  494. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  495. memset(&mbox_sts, 0, sizeof(mbox_sts));
  496. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  497. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  498. QLA_SUCCESS) {
  499. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  500. "status %04X\n", ha->host_no, __func__,
  501. mbox_sts[0]));
  502. return QLA_ERROR;
  503. }
  504. ha->firmware_state = mbox_sts[1];
  505. ha->board_id = mbox_sts[2];
  506. ha->addl_fw_state = mbox_sts[3];
  507. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  508. ha->host_no, __func__, ha->firmware_state);)
  509. return QLA_SUCCESS;
  510. }
  511. /**
  512. * qla4xxx_get_firmware_status - retrieves firmware status
  513. * @ha: Pointer to host adapter structure.
  514. **/
  515. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  516. {
  517. uint32_t mbox_cmd[MBOX_REG_COUNT];
  518. uint32_t mbox_sts[MBOX_REG_COUNT];
  519. /* Get firmware version */
  520. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  521. memset(&mbox_sts, 0, sizeof(mbox_sts));
  522. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  523. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  524. QLA_SUCCESS) {
  525. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  526. "status %04X\n", ha->host_no, __func__,
  527. mbox_sts[0]));
  528. return QLA_ERROR;
  529. }
  530. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  531. ha->host_no, mbox_sts[2]);
  532. return QLA_SUCCESS;
  533. }
  534. /**
  535. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  536. * @ha: Pointer to host adapter structure.
  537. * @fw_ddb_index: Firmware's device database index
  538. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  539. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  540. * @next_ddb_index: Pointer to next valid device database index
  541. * @fw_ddb_device_state: Pointer to device state
  542. **/
  543. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  544. uint16_t fw_ddb_index,
  545. struct dev_db_entry *fw_ddb_entry,
  546. dma_addr_t fw_ddb_entry_dma,
  547. uint32_t *num_valid_ddb_entries,
  548. uint32_t *next_ddb_index,
  549. uint32_t *fw_ddb_device_state,
  550. uint32_t *conn_err_detail,
  551. uint16_t *tcp_source_port_num,
  552. uint16_t *connection_id)
  553. {
  554. int status = QLA_ERROR;
  555. uint16_t options;
  556. uint32_t mbox_cmd[MBOX_REG_COUNT];
  557. uint32_t mbox_sts[MBOX_REG_COUNT];
  558. /* Make sure the device index is valid */
  559. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  560. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  561. ha->host_no, __func__, fw_ddb_index));
  562. goto exit_get_fwddb;
  563. }
  564. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  565. memset(&mbox_sts, 0, sizeof(mbox_sts));
  566. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  567. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  568. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  569. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  570. mbox_cmd[4] = sizeof(struct dev_db_entry);
  571. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  572. QLA_ERROR) {
  573. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  574. " with status 0x%04X\n", ha->host_no, __func__,
  575. mbox_sts[0]));
  576. goto exit_get_fwddb;
  577. }
  578. if (fw_ddb_index != mbox_sts[1]) {
  579. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  580. ha->host_no, __func__, fw_ddb_index,
  581. mbox_sts[1]));
  582. goto exit_get_fwddb;
  583. }
  584. if (fw_ddb_entry) {
  585. options = le16_to_cpu(fw_ddb_entry->options);
  586. if (options & DDB_OPT_IPV6_DEVICE) {
  587. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  588. "Next %d State %04x ConnErr %08x %pI6 "
  589. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  590. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  591. mbox_sts[4], mbox_sts[5],
  592. fw_ddb_entry->ip_addr,
  593. le16_to_cpu(fw_ddb_entry->port),
  594. fw_ddb_entry->iscsi_name);
  595. } else {
  596. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  597. "Next %d State %04x ConnErr %08x %pI4 "
  598. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  599. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  600. mbox_sts[4], mbox_sts[5],
  601. fw_ddb_entry->ip_addr,
  602. le16_to_cpu(fw_ddb_entry->port),
  603. fw_ddb_entry->iscsi_name);
  604. }
  605. }
  606. if (num_valid_ddb_entries)
  607. *num_valid_ddb_entries = mbox_sts[2];
  608. if (next_ddb_index)
  609. *next_ddb_index = mbox_sts[3];
  610. if (fw_ddb_device_state)
  611. *fw_ddb_device_state = mbox_sts[4];
  612. /*
  613. * RA: This mailbox has been changed to pass connection error and
  614. * details. Its true for ISP4010 as per Version E - Not sure when it
  615. * was changed. Get the time2wait from the fw_dd_entry field :
  616. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  617. * struct.
  618. */
  619. if (conn_err_detail)
  620. *conn_err_detail = mbox_sts[5];
  621. if (tcp_source_port_num)
  622. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  623. if (connection_id)
  624. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  625. status = QLA_SUCCESS;
  626. exit_get_fwddb:
  627. return status;
  628. }
  629. /**
  630. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  631. * @ha: Pointer to host adapter structure.
  632. * @fw_ddb_index: Firmware's device database index
  633. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  634. *
  635. * This routine initializes or updates the adapter's device database
  636. * entry for the specified device. It also triggers a login for the
  637. * specified device. Therefore, it may also be used as a secondary
  638. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  639. **/
  640. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  641. dma_addr_t fw_ddb_entry_dma)
  642. {
  643. uint32_t mbox_cmd[MBOX_REG_COUNT];
  644. uint32_t mbox_sts[MBOX_REG_COUNT];
  645. int status;
  646. /* Do not wait for completion. The firmware will send us an
  647. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  648. */
  649. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  650. memset(&mbox_sts, 0, sizeof(mbox_sts));
  651. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  652. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  653. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  654. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  655. mbox_cmd[4] = sizeof(struct dev_db_entry);
  656. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  657. &mbox_sts[0]);
  658. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  659. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  660. return status;
  661. }
  662. /**
  663. * qla4xxx_get_crash_record - retrieves crash record.
  664. * @ha: Pointer to host adapter structure.
  665. *
  666. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  667. **/
  668. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  669. {
  670. uint32_t mbox_cmd[MBOX_REG_COUNT];
  671. uint32_t mbox_sts[MBOX_REG_COUNT];
  672. struct crash_record *crash_record = NULL;
  673. dma_addr_t crash_record_dma = 0;
  674. uint32_t crash_record_size = 0;
  675. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  676. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  677. /* Get size of crash record. */
  678. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  679. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  680. QLA_SUCCESS) {
  681. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  682. ha->host_no, __func__));
  683. goto exit_get_crash_record;
  684. }
  685. crash_record_size = mbox_sts[4];
  686. if (crash_record_size == 0) {
  687. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  688. ha->host_no, __func__));
  689. goto exit_get_crash_record;
  690. }
  691. /* Alloc Memory for Crash Record. */
  692. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  693. &crash_record_dma, GFP_KERNEL);
  694. if (crash_record == NULL)
  695. goto exit_get_crash_record;
  696. /* Get Crash Record. */
  697. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  698. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  699. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  700. mbox_cmd[2] = LSDW(crash_record_dma);
  701. mbox_cmd[3] = MSDW(crash_record_dma);
  702. mbox_cmd[4] = crash_record_size;
  703. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  704. QLA_SUCCESS)
  705. goto exit_get_crash_record;
  706. /* Dump Crash Record. */
  707. exit_get_crash_record:
  708. if (crash_record)
  709. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  710. crash_record, crash_record_dma);
  711. }
  712. /**
  713. * qla4xxx_get_conn_event_log - retrieves connection event log
  714. * @ha: Pointer to host adapter structure.
  715. **/
  716. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  717. {
  718. uint32_t mbox_cmd[MBOX_REG_COUNT];
  719. uint32_t mbox_sts[MBOX_REG_COUNT];
  720. struct conn_event_log_entry *event_log = NULL;
  721. dma_addr_t event_log_dma = 0;
  722. uint32_t event_log_size = 0;
  723. uint32_t num_valid_entries;
  724. uint32_t oldest_entry = 0;
  725. uint32_t max_event_log_entries;
  726. uint8_t i;
  727. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  728. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  729. /* Get size of crash record. */
  730. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  731. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  732. QLA_SUCCESS)
  733. goto exit_get_event_log;
  734. event_log_size = mbox_sts[4];
  735. if (event_log_size == 0)
  736. goto exit_get_event_log;
  737. /* Alloc Memory for Crash Record. */
  738. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  739. &event_log_dma, GFP_KERNEL);
  740. if (event_log == NULL)
  741. goto exit_get_event_log;
  742. /* Get Crash Record. */
  743. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  744. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  745. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  746. mbox_cmd[2] = LSDW(event_log_dma);
  747. mbox_cmd[3] = MSDW(event_log_dma);
  748. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  749. QLA_SUCCESS) {
  750. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  751. "log!\n", ha->host_no, __func__));
  752. goto exit_get_event_log;
  753. }
  754. /* Dump Event Log. */
  755. num_valid_entries = mbox_sts[1];
  756. max_event_log_entries = event_log_size /
  757. sizeof(struct conn_event_log_entry);
  758. if (num_valid_entries > max_event_log_entries)
  759. oldest_entry = num_valid_entries % max_event_log_entries;
  760. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  761. ha->host_no, num_valid_entries));
  762. if (ql4xextended_error_logging == 3) {
  763. if (oldest_entry == 0) {
  764. /* Circular Buffer has not wrapped around */
  765. for (i=0; i < num_valid_entries; i++) {
  766. qla4xxx_dump_buffer((uint8_t *)event_log+
  767. (i*sizeof(*event_log)),
  768. sizeof(*event_log));
  769. }
  770. }
  771. else {
  772. /* Circular Buffer has wrapped around -
  773. * display accordingly*/
  774. for (i=oldest_entry; i < max_event_log_entries; i++) {
  775. qla4xxx_dump_buffer((uint8_t *)event_log+
  776. (i*sizeof(*event_log)),
  777. sizeof(*event_log));
  778. }
  779. for (i=0; i < oldest_entry; i++) {
  780. qla4xxx_dump_buffer((uint8_t *)event_log+
  781. (i*sizeof(*event_log)),
  782. sizeof(*event_log));
  783. }
  784. }
  785. }
  786. exit_get_event_log:
  787. if (event_log)
  788. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  789. event_log_dma);
  790. }
  791. /**
  792. * qla4xxx_abort_task - issues Abort Task
  793. * @ha: Pointer to host adapter structure.
  794. * @srb: Pointer to srb entry
  795. *
  796. * This routine performs a LUN RESET on the specified target/lun.
  797. * The caller must ensure that the ddb_entry and lun_entry pointers
  798. * are valid before calling this routine.
  799. **/
  800. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  801. {
  802. uint32_t mbox_cmd[MBOX_REG_COUNT];
  803. uint32_t mbox_sts[MBOX_REG_COUNT];
  804. struct scsi_cmnd *cmd = srb->cmd;
  805. int status = QLA_SUCCESS;
  806. unsigned long flags = 0;
  807. uint32_t index;
  808. /*
  809. * Send abort task command to ISP, so that the ISP will return
  810. * request with ABORT status
  811. */
  812. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  813. memset(&mbox_sts, 0, sizeof(mbox_sts));
  814. spin_lock_irqsave(&ha->hardware_lock, flags);
  815. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  816. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  817. /* Firmware already posted completion on response queue */
  818. if (index == MAX_SRBS)
  819. return status;
  820. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  821. mbox_cmd[1] = srb->fw_ddb_index;
  822. mbox_cmd[2] = index;
  823. /* Immediate Command Enable */
  824. mbox_cmd[5] = 0x01;
  825. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  826. &mbox_sts[0]);
  827. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  828. status = QLA_ERROR;
  829. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  830. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  831. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  832. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  833. }
  834. return status;
  835. }
  836. /**
  837. * qla4xxx_reset_lun - issues LUN Reset
  838. * @ha: Pointer to host adapter structure.
  839. * @ddb_entry: Pointer to device database entry
  840. * @lun: lun number
  841. *
  842. * This routine performs a LUN RESET on the specified target/lun.
  843. * The caller must ensure that the ddb_entry and lun_entry pointers
  844. * are valid before calling this routine.
  845. **/
  846. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  847. int lun)
  848. {
  849. uint32_t mbox_cmd[MBOX_REG_COUNT];
  850. uint32_t mbox_sts[MBOX_REG_COUNT];
  851. int status = QLA_SUCCESS;
  852. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  853. ddb_entry->fw_ddb_index, lun));
  854. /*
  855. * Send lun reset command to ISP, so that the ISP will return all
  856. * outstanding requests with RESET status
  857. */
  858. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  859. memset(&mbox_sts, 0, sizeof(mbox_sts));
  860. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  861. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  862. mbox_cmd[2] = lun << 8;
  863. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  864. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  865. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  866. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  867. status = QLA_ERROR;
  868. return status;
  869. }
  870. /**
  871. * qla4xxx_reset_target - issues target Reset
  872. * @ha: Pointer to host adapter structure.
  873. * @db_entry: Pointer to device database entry
  874. * @un_entry: Pointer to lun entry structure
  875. *
  876. * This routine performs a TARGET RESET on the specified target.
  877. * The caller must ensure that the ddb_entry pointers
  878. * are valid before calling this routine.
  879. **/
  880. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  881. struct ddb_entry *ddb_entry)
  882. {
  883. uint32_t mbox_cmd[MBOX_REG_COUNT];
  884. uint32_t mbox_sts[MBOX_REG_COUNT];
  885. int status = QLA_SUCCESS;
  886. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  887. ddb_entry->fw_ddb_index));
  888. /*
  889. * Send target reset command to ISP, so that the ISP will return all
  890. * outstanding requests with RESET status
  891. */
  892. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  893. memset(&mbox_sts, 0, sizeof(mbox_sts));
  894. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  895. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  896. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  897. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  898. &mbox_sts[0]);
  899. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  900. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  901. status = QLA_ERROR;
  902. return status;
  903. }
  904. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  905. uint32_t offset, uint32_t len)
  906. {
  907. uint32_t mbox_cmd[MBOX_REG_COUNT];
  908. uint32_t mbox_sts[MBOX_REG_COUNT];
  909. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  910. memset(&mbox_sts, 0, sizeof(mbox_sts));
  911. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  912. mbox_cmd[1] = LSDW(dma_addr);
  913. mbox_cmd[2] = MSDW(dma_addr);
  914. mbox_cmd[3] = offset;
  915. mbox_cmd[4] = len;
  916. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  917. QLA_SUCCESS) {
  918. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  919. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  920. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  921. return QLA_ERROR;
  922. }
  923. return QLA_SUCCESS;
  924. }
  925. /**
  926. * qla4xxx_get_fw_version - gets firmware version
  927. * @ha: Pointer to host adapter structure.
  928. *
  929. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  930. * hold an address for data. Make sure that we write 0 to those mailboxes,
  931. * if unused.
  932. **/
  933. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  934. {
  935. uint32_t mbox_cmd[MBOX_REG_COUNT];
  936. uint32_t mbox_sts[MBOX_REG_COUNT];
  937. /* Get firmware version. */
  938. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  939. memset(&mbox_sts, 0, sizeof(mbox_sts));
  940. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  941. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  942. QLA_SUCCESS) {
  943. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  944. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  945. return QLA_ERROR;
  946. }
  947. /* Save firmware version information. */
  948. ha->firmware_version[0] = mbox_sts[1];
  949. ha->firmware_version[1] = mbox_sts[2];
  950. ha->patch_number = mbox_sts[3];
  951. ha->build_number = mbox_sts[4];
  952. return QLA_SUCCESS;
  953. }
  954. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  955. dma_addr_t dma_addr)
  956. {
  957. uint32_t mbox_cmd[MBOX_REG_COUNT];
  958. uint32_t mbox_sts[MBOX_REG_COUNT];
  959. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  960. memset(&mbox_sts, 0, sizeof(mbox_sts));
  961. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  962. mbox_cmd[2] = LSDW(dma_addr);
  963. mbox_cmd[3] = MSDW(dma_addr);
  964. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  965. QLA_SUCCESS) {
  966. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  967. ha->host_no, __func__, mbox_sts[0]));
  968. return QLA_ERROR;
  969. }
  970. return QLA_SUCCESS;
  971. }
  972. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  973. {
  974. uint32_t mbox_cmd[MBOX_REG_COUNT];
  975. uint32_t mbox_sts[MBOX_REG_COUNT];
  976. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  977. memset(&mbox_sts, 0, sizeof(mbox_sts));
  978. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  979. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  980. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  981. QLA_SUCCESS) {
  982. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  983. *ddb_index = mbox_sts[2];
  984. } else {
  985. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  986. ha->host_no, __func__, mbox_sts[0]));
  987. return QLA_ERROR;
  988. }
  989. } else {
  990. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  991. }
  992. return QLA_SUCCESS;
  993. }
  994. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  995. {
  996. struct dev_db_entry *fw_ddb_entry;
  997. dma_addr_t fw_ddb_entry_dma;
  998. uint32_t ddb_index;
  999. int ret_val = QLA_SUCCESS;
  1000. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  1001. sizeof(*fw_ddb_entry),
  1002. &fw_ddb_entry_dma, GFP_KERNEL);
  1003. if (!fw_ddb_entry) {
  1004. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  1005. ha->host_no, __func__));
  1006. ret_val = QLA_ERROR;
  1007. goto exit_send_tgts_no_free;
  1008. }
  1009. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  1010. if (ret_val != QLA_SUCCESS)
  1011. goto exit_send_tgts;
  1012. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  1013. if (ret_val != QLA_SUCCESS)
  1014. goto exit_send_tgts;
  1015. memset(fw_ddb_entry->iscsi_alias, 0,
  1016. sizeof(fw_ddb_entry->iscsi_alias));
  1017. memset(fw_ddb_entry->iscsi_name, 0,
  1018. sizeof(fw_ddb_entry->iscsi_name));
  1019. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1020. memset(fw_ddb_entry->tgt_addr, 0,
  1021. sizeof(fw_ddb_entry->tgt_addr));
  1022. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1023. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1024. fw_ddb_entry->ip_addr[0] = *ip;
  1025. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1026. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1027. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1028. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1029. exit_send_tgts:
  1030. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1031. fw_ddb_entry, fw_ddb_entry_dma);
  1032. exit_send_tgts_no_free:
  1033. return ret_val;
  1034. }