qla_os.c 109 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO|S_IRUSR);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO|S_IRUSR);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO|S_IRUSR);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO|S_IRUSR);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO|S_IRUSR);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO|S_IRUSR);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO|S_IRUSR);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO|S_IRUSR);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO|S_IRUSR);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO|S_IRUSR);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO|S_IRUSR);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO|S_IRUSR);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xdontresethba;
  126. module_param(ql2xdontresethba, int, S_IRUGO|S_IRUSR);
  127. MODULE_PARM_DESC(ql2xdontresethba,
  128. "Option to specify reset behaviour\n"
  129. " 0 (Default) -- Reset on failure.\n"
  130. " 1 -- Do not reset on failure.\n");
  131. int ql2xtargetreset = 1;
  132. module_param(ql2xtargetreset, int, S_IRUGO|S_IRUSR);
  133. MODULE_PARM_DESC(ql2xtargetreset,
  134. "Enable target reset."
  135. "Default is 1 - use hw defaults.");
  136. int ql2xgffidenable;
  137. module_param(ql2xgffidenable, int, S_IRUGO|S_IRUSR);
  138. MODULE_PARM_DESC(ql2xgffidenable,
  139. "Enables GFF_ID checks of port type. "
  140. "Default is 0 - Do not use GFF_ID information.");
  141. int ql2xasynctmfenable;
  142. module_param(ql2xasynctmfenable, int, S_IRUGO|S_IRUSR);
  143. MODULE_PARM_DESC(ql2xasynctmfenable,
  144. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  145. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  146. /*
  147. * SCSI host template entry points
  148. */
  149. static int qla2xxx_slave_configure(struct scsi_device * device);
  150. static int qla2xxx_slave_alloc(struct scsi_device *);
  151. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  152. static void qla2xxx_scan_start(struct Scsi_Host *);
  153. static void qla2xxx_slave_destroy(struct scsi_device *);
  154. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  155. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  156. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  157. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  158. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  159. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  160. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  161. static int qla2x00_change_queue_type(struct scsi_device *, int);
  162. struct scsi_host_template qla2xxx_driver_template = {
  163. .module = THIS_MODULE,
  164. .name = QLA2XXX_DRIVER_NAME,
  165. .queuecommand = qla2xxx_queuecommand,
  166. .eh_abort_handler = qla2xxx_eh_abort,
  167. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  168. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  169. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  170. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  171. .slave_configure = qla2xxx_slave_configure,
  172. .slave_alloc = qla2xxx_slave_alloc,
  173. .slave_destroy = qla2xxx_slave_destroy,
  174. .scan_finished = qla2xxx_scan_finished,
  175. .scan_start = qla2xxx_scan_start,
  176. .change_queue_depth = qla2x00_change_queue_depth,
  177. .change_queue_type = qla2x00_change_queue_type,
  178. .this_id = -1,
  179. .cmd_per_lun = 3,
  180. .use_clustering = ENABLE_CLUSTERING,
  181. .sg_tablesize = SG_ALL,
  182. .max_sectors = 0xFFFF,
  183. .shost_attrs = qla2x00_host_attrs,
  184. };
  185. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  186. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  187. /* TODO Convert to inlines
  188. *
  189. * Timer routines
  190. */
  191. __inline__ void
  192. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  193. {
  194. init_timer(&vha->timer);
  195. vha->timer.expires = jiffies + interval * HZ;
  196. vha->timer.data = (unsigned long)vha;
  197. vha->timer.function = (void (*)(unsigned long))func;
  198. add_timer(&vha->timer);
  199. vha->timer_active = 1;
  200. }
  201. static inline void
  202. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  203. {
  204. /* Currently used for 82XX only. */
  205. if (vha->device_flags & DFLG_DEV_FAILED)
  206. return;
  207. mod_timer(&vha->timer, jiffies + interval * HZ);
  208. }
  209. static __inline__ void
  210. qla2x00_stop_timer(scsi_qla_host_t *vha)
  211. {
  212. del_timer_sync(&vha->timer);
  213. vha->timer_active = 0;
  214. }
  215. static int qla2x00_do_dpc(void *data);
  216. static void qla2x00_rst_aen(scsi_qla_host_t *);
  217. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  218. struct req_que **, struct rsp_que **);
  219. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  220. static void qla2x00_mem_free(struct qla_hw_data *);
  221. static void qla2x00_sp_free_dma(srb_t *);
  222. /* -------------------------------------------------------------------------- */
  223. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  224. {
  225. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  226. GFP_KERNEL);
  227. if (!ha->req_q_map) {
  228. qla_printk(KERN_WARNING, ha,
  229. "Unable to allocate memory for request queue ptrs\n");
  230. goto fail_req_map;
  231. }
  232. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  233. GFP_KERNEL);
  234. if (!ha->rsp_q_map) {
  235. qla_printk(KERN_WARNING, ha,
  236. "Unable to allocate memory for response queue ptrs\n");
  237. goto fail_rsp_map;
  238. }
  239. set_bit(0, ha->rsp_qid_map);
  240. set_bit(0, ha->req_qid_map);
  241. return 1;
  242. fail_rsp_map:
  243. kfree(ha->req_q_map);
  244. ha->req_q_map = NULL;
  245. fail_req_map:
  246. return -ENOMEM;
  247. }
  248. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  249. {
  250. if (req && req->ring)
  251. dma_free_coherent(&ha->pdev->dev,
  252. (req->length + 1) * sizeof(request_t),
  253. req->ring, req->dma);
  254. kfree(req);
  255. req = NULL;
  256. }
  257. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  258. {
  259. if (rsp && rsp->ring)
  260. dma_free_coherent(&ha->pdev->dev,
  261. (rsp->length + 1) * sizeof(response_t),
  262. rsp->ring, rsp->dma);
  263. kfree(rsp);
  264. rsp = NULL;
  265. }
  266. static void qla2x00_free_queues(struct qla_hw_data *ha)
  267. {
  268. struct req_que *req;
  269. struct rsp_que *rsp;
  270. int cnt;
  271. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  272. req = ha->req_q_map[cnt];
  273. qla2x00_free_req_que(ha, req);
  274. }
  275. kfree(ha->req_q_map);
  276. ha->req_q_map = NULL;
  277. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  278. rsp = ha->rsp_q_map[cnt];
  279. qla2x00_free_rsp_que(ha, rsp);
  280. }
  281. kfree(ha->rsp_q_map);
  282. ha->rsp_q_map = NULL;
  283. }
  284. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  285. {
  286. uint16_t options = 0;
  287. int ques, req, ret;
  288. struct qla_hw_data *ha = vha->hw;
  289. if (!(ha->fw_attributes & BIT_6)) {
  290. qla_printk(KERN_INFO, ha,
  291. "Firmware is not multi-queue capable\n");
  292. goto fail;
  293. }
  294. if (ql2xmultique_tag) {
  295. /* create a request queue for IO */
  296. options |= BIT_7;
  297. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  298. QLA_DEFAULT_QUE_QOS);
  299. if (!req) {
  300. qla_printk(KERN_WARNING, ha,
  301. "Can't create request queue\n");
  302. goto fail;
  303. }
  304. ha->wq = create_workqueue("qla2xxx_wq");
  305. vha->req = ha->req_q_map[req];
  306. options |= BIT_1;
  307. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  308. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  309. if (!ret) {
  310. qla_printk(KERN_WARNING, ha,
  311. "Response Queue create failed\n");
  312. goto fail2;
  313. }
  314. }
  315. ha->flags.cpu_affinity_enabled = 1;
  316. DEBUG2(qla_printk(KERN_INFO, ha,
  317. "CPU affinity mode enabled, no. of response"
  318. " queues:%d, no. of request queues:%d\n",
  319. ha->max_rsp_queues, ha->max_req_queues));
  320. }
  321. return 0;
  322. fail2:
  323. qla25xx_delete_queues(vha);
  324. destroy_workqueue(ha->wq);
  325. ha->wq = NULL;
  326. fail:
  327. ha->mqenable = 0;
  328. kfree(ha->req_q_map);
  329. kfree(ha->rsp_q_map);
  330. ha->max_req_queues = ha->max_rsp_queues = 1;
  331. return 1;
  332. }
  333. static char *
  334. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  335. {
  336. struct qla_hw_data *ha = vha->hw;
  337. static char *pci_bus_modes[] = {
  338. "33", "66", "100", "133",
  339. };
  340. uint16_t pci_bus;
  341. strcpy(str, "PCI");
  342. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  343. if (pci_bus) {
  344. strcat(str, "-X (");
  345. strcat(str, pci_bus_modes[pci_bus]);
  346. } else {
  347. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  348. strcat(str, " (");
  349. strcat(str, pci_bus_modes[pci_bus]);
  350. }
  351. strcat(str, " MHz)");
  352. return (str);
  353. }
  354. static char *
  355. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  356. {
  357. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  358. struct qla_hw_data *ha = vha->hw;
  359. uint32_t pci_bus;
  360. int pcie_reg;
  361. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  362. if (pcie_reg) {
  363. char lwstr[6];
  364. uint16_t pcie_lstat, lspeed, lwidth;
  365. pcie_reg += 0x12;
  366. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  367. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  368. lwidth = (pcie_lstat &
  369. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  370. strcpy(str, "PCIe (");
  371. if (lspeed == 1)
  372. strcat(str, "2.5GT/s ");
  373. else if (lspeed == 2)
  374. strcat(str, "5.0GT/s ");
  375. else
  376. strcat(str, "<unknown> ");
  377. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  378. strcat(str, lwstr);
  379. return str;
  380. }
  381. strcpy(str, "PCI");
  382. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  383. if (pci_bus == 0 || pci_bus == 8) {
  384. strcat(str, " (");
  385. strcat(str, pci_bus_modes[pci_bus >> 3]);
  386. } else {
  387. strcat(str, "-X ");
  388. if (pci_bus & BIT_2)
  389. strcat(str, "Mode 2");
  390. else
  391. strcat(str, "Mode 1");
  392. strcat(str, " (");
  393. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  394. }
  395. strcat(str, " MHz)");
  396. return str;
  397. }
  398. static char *
  399. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  400. {
  401. char un_str[10];
  402. struct qla_hw_data *ha = vha->hw;
  403. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  404. ha->fw_minor_version,
  405. ha->fw_subminor_version);
  406. if (ha->fw_attributes & BIT_9) {
  407. strcat(str, "FLX");
  408. return (str);
  409. }
  410. switch (ha->fw_attributes & 0xFF) {
  411. case 0x7:
  412. strcat(str, "EF");
  413. break;
  414. case 0x17:
  415. strcat(str, "TP");
  416. break;
  417. case 0x37:
  418. strcat(str, "IP");
  419. break;
  420. case 0x77:
  421. strcat(str, "VI");
  422. break;
  423. default:
  424. sprintf(un_str, "(%x)", ha->fw_attributes);
  425. strcat(str, un_str);
  426. break;
  427. }
  428. if (ha->fw_attributes & 0x100)
  429. strcat(str, "X");
  430. return (str);
  431. }
  432. static char *
  433. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  434. {
  435. struct qla_hw_data *ha = vha->hw;
  436. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  437. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  438. return str;
  439. }
  440. static inline srb_t *
  441. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  442. struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  443. {
  444. srb_t *sp;
  445. struct qla_hw_data *ha = vha->hw;
  446. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  447. if (!sp)
  448. return sp;
  449. atomic_set(&sp->ref_count, 1);
  450. sp->fcport = fcport;
  451. sp->cmd = cmd;
  452. sp->flags = 0;
  453. CMD_SP(cmd) = (void *)sp;
  454. cmd->scsi_done = done;
  455. sp->ctx = NULL;
  456. return sp;
  457. }
  458. static int
  459. qla2xxx_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  460. {
  461. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  462. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  463. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  464. struct qla_hw_data *ha = vha->hw;
  465. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  466. srb_t *sp;
  467. int rval;
  468. spin_unlock_irq(vha->host->host_lock);
  469. if (ha->flags.eeh_busy) {
  470. if (ha->flags.pci_channel_io_perm_failure)
  471. cmd->result = DID_NO_CONNECT << 16;
  472. else
  473. cmd->result = DID_REQUEUE << 16;
  474. goto qc24_fail_command;
  475. }
  476. rval = fc_remote_port_chkready(rport);
  477. if (rval) {
  478. cmd->result = rval;
  479. goto qc24_fail_command;
  480. }
  481. if (!vha->flags.difdix_supported &&
  482. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  483. DEBUG2(qla_printk(KERN_ERR, ha,
  484. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  485. cmd->cmnd[0]));
  486. cmd->result = DID_NO_CONNECT << 16;
  487. goto qc24_fail_command;
  488. }
  489. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  490. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  491. atomic_read(&fcport->state) == FCS_DEVICE_LOST ||
  492. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  493. cmd->result = DID_NO_CONNECT << 16;
  494. goto qc24_fail_command;
  495. }
  496. goto qc24_target_busy;
  497. }
  498. sp = qla2x00_get_new_sp(base_vha, fcport, cmd, done);
  499. if (!sp)
  500. goto qc24_host_busy_lock;
  501. rval = ha->isp_ops->start_scsi(sp);
  502. if (rval != QLA_SUCCESS)
  503. goto qc24_host_busy_free_sp;
  504. spin_lock_irq(vha->host->host_lock);
  505. return 0;
  506. qc24_host_busy_free_sp:
  507. qla2x00_sp_free_dma(sp);
  508. mempool_free(sp, ha->srb_mempool);
  509. qc24_host_busy_lock:
  510. spin_lock_irq(vha->host->host_lock);
  511. return SCSI_MLQUEUE_HOST_BUSY;
  512. qc24_target_busy:
  513. spin_lock_irq(vha->host->host_lock);
  514. return SCSI_MLQUEUE_TARGET_BUSY;
  515. qc24_fail_command:
  516. spin_lock_irq(vha->host->host_lock);
  517. done(cmd);
  518. return 0;
  519. }
  520. static DEF_SCSI_QCMD(qla2xxx_queuecommand)
  521. /*
  522. * qla2x00_eh_wait_on_command
  523. * Waits for the command to be returned by the Firmware for some
  524. * max time.
  525. *
  526. * Input:
  527. * cmd = Scsi Command to wait on.
  528. *
  529. * Return:
  530. * Not Found : 0
  531. * Found : 1
  532. */
  533. static int
  534. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  535. {
  536. #define ABORT_POLLING_PERIOD 1000
  537. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  538. unsigned long wait_iter = ABORT_WAIT_ITER;
  539. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  540. struct qla_hw_data *ha = vha->hw;
  541. int ret = QLA_SUCCESS;
  542. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  543. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  544. return ret;
  545. }
  546. while (CMD_SP(cmd) && wait_iter--) {
  547. msleep(ABORT_POLLING_PERIOD);
  548. }
  549. if (CMD_SP(cmd))
  550. ret = QLA_FUNCTION_FAILED;
  551. return ret;
  552. }
  553. /*
  554. * qla2x00_wait_for_hba_online
  555. * Wait till the HBA is online after going through
  556. * <= MAX_RETRIES_OF_ISP_ABORT or
  557. * finally HBA is disabled ie marked offline
  558. *
  559. * Input:
  560. * ha - pointer to host adapter structure
  561. *
  562. * Note:
  563. * Does context switching-Release SPIN_LOCK
  564. * (if any) before calling this routine.
  565. *
  566. * Return:
  567. * Success (Adapter is online) : 0
  568. * Failed (Adapter is offline/disabled) : 1
  569. */
  570. int
  571. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  572. {
  573. int return_status;
  574. unsigned long wait_online;
  575. struct qla_hw_data *ha = vha->hw;
  576. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  577. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  578. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  579. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  580. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  581. ha->dpc_active) && time_before(jiffies, wait_online)) {
  582. msleep(1000);
  583. }
  584. if (base_vha->flags.online)
  585. return_status = QLA_SUCCESS;
  586. else
  587. return_status = QLA_FUNCTION_FAILED;
  588. return (return_status);
  589. }
  590. /*
  591. * qla2x00_wait_for_reset_ready
  592. * Wait till the HBA is online after going through
  593. * <= MAX_RETRIES_OF_ISP_ABORT or
  594. * finally HBA is disabled ie marked offline or flash
  595. * operations are in progress.
  596. *
  597. * Input:
  598. * ha - pointer to host adapter structure
  599. *
  600. * Note:
  601. * Does context switching-Release SPIN_LOCK
  602. * (if any) before calling this routine.
  603. *
  604. * Return:
  605. * Success (Adapter is online/no flash ops) : 0
  606. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  607. */
  608. static int
  609. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  610. {
  611. int return_status;
  612. unsigned long wait_online;
  613. struct qla_hw_data *ha = vha->hw;
  614. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  615. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  616. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  617. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  618. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  619. ha->optrom_state != QLA_SWAITING ||
  620. ha->dpc_active) && time_before(jiffies, wait_online))
  621. msleep(1000);
  622. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  623. return_status = QLA_SUCCESS;
  624. else
  625. return_status = QLA_FUNCTION_FAILED;
  626. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  627. return return_status;
  628. }
  629. int
  630. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  631. {
  632. int return_status;
  633. unsigned long wait_reset;
  634. struct qla_hw_data *ha = vha->hw;
  635. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  636. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  637. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  638. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  639. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  640. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  641. msleep(1000);
  642. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  643. ha->flags.chip_reset_done)
  644. break;
  645. }
  646. if (ha->flags.chip_reset_done)
  647. return_status = QLA_SUCCESS;
  648. else
  649. return_status = QLA_FUNCTION_FAILED;
  650. return return_status;
  651. }
  652. /*
  653. * qla2x00_wait_for_loop_ready
  654. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  655. * to be in LOOP_READY state.
  656. * Input:
  657. * ha - pointer to host adapter structure
  658. *
  659. * Note:
  660. * Does context switching-Release SPIN_LOCK
  661. * (if any) before calling this routine.
  662. *
  663. *
  664. * Return:
  665. * Success (LOOP_READY) : 0
  666. * Failed (LOOP_NOT_READY) : 1
  667. */
  668. static inline int
  669. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  670. {
  671. int return_status = QLA_SUCCESS;
  672. unsigned long loop_timeout ;
  673. struct qla_hw_data *ha = vha->hw;
  674. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  675. /* wait for 5 min at the max for loop to be ready */
  676. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  677. while ((!atomic_read(&base_vha->loop_down_timer) &&
  678. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  679. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  680. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  681. return_status = QLA_FUNCTION_FAILED;
  682. break;
  683. }
  684. msleep(1000);
  685. if (time_after_eq(jiffies, loop_timeout)) {
  686. return_status = QLA_FUNCTION_FAILED;
  687. break;
  688. }
  689. }
  690. return (return_status);
  691. }
  692. static void
  693. sp_get(struct srb *sp)
  694. {
  695. atomic_inc(&sp->ref_count);
  696. }
  697. /**************************************************************************
  698. * qla2xxx_eh_abort
  699. *
  700. * Description:
  701. * The abort function will abort the specified command.
  702. *
  703. * Input:
  704. * cmd = Linux SCSI command packet to be aborted.
  705. *
  706. * Returns:
  707. * Either SUCCESS or FAILED.
  708. *
  709. * Note:
  710. * Only return FAILED if command not returned by firmware.
  711. **************************************************************************/
  712. static int
  713. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  714. {
  715. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  716. srb_t *sp;
  717. int ret = SUCCESS;
  718. unsigned int id, lun;
  719. unsigned long flags;
  720. int wait = 0;
  721. struct qla_hw_data *ha = vha->hw;
  722. fc_block_scsi_eh(cmd);
  723. if (!CMD_SP(cmd))
  724. return SUCCESS;
  725. id = cmd->device->id;
  726. lun = cmd->device->lun;
  727. spin_lock_irqsave(&ha->hardware_lock, flags);
  728. sp = (srb_t *) CMD_SP(cmd);
  729. if (!sp) {
  730. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  731. return SUCCESS;
  732. }
  733. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  734. __func__, vha->host_no, sp));
  735. /* Get a reference to the sp and drop the lock.*/
  736. sp_get(sp);
  737. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  738. if (ha->isp_ops->abort_command(sp)) {
  739. DEBUG2(printk("%s(%ld): abort_command "
  740. "mbx failed.\n", __func__, vha->host_no));
  741. ret = FAILED;
  742. } else {
  743. DEBUG3(printk("%s(%ld): abort_command "
  744. "mbx success.\n", __func__, vha->host_no));
  745. wait = 1;
  746. }
  747. qla2x00_sp_compl(ha, sp);
  748. /* Wait for the command to be returned. */
  749. if (wait) {
  750. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  751. qla_printk(KERN_ERR, ha,
  752. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  753. vha->host_no, id, lun, ret);
  754. ret = FAILED;
  755. }
  756. }
  757. qla_printk(KERN_INFO, ha,
  758. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  759. vha->host_no, id, lun, wait, ret);
  760. return ret;
  761. }
  762. int
  763. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  764. unsigned int l, enum nexus_wait_type type)
  765. {
  766. int cnt, match, status;
  767. unsigned long flags;
  768. struct qla_hw_data *ha = vha->hw;
  769. struct req_que *req;
  770. srb_t *sp;
  771. status = QLA_SUCCESS;
  772. spin_lock_irqsave(&ha->hardware_lock, flags);
  773. req = vha->req;
  774. for (cnt = 1; status == QLA_SUCCESS &&
  775. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  776. sp = req->outstanding_cmds[cnt];
  777. if (!sp)
  778. continue;
  779. if ((sp->ctx) && !IS_PROT_IO(sp))
  780. continue;
  781. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  782. continue;
  783. match = 0;
  784. switch (type) {
  785. case WAIT_HOST:
  786. match = 1;
  787. break;
  788. case WAIT_TARGET:
  789. match = sp->cmd->device->id == t;
  790. break;
  791. case WAIT_LUN:
  792. match = (sp->cmd->device->id == t &&
  793. sp->cmd->device->lun == l);
  794. break;
  795. }
  796. if (!match)
  797. continue;
  798. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  799. status = qla2x00_eh_wait_on_command(sp->cmd);
  800. spin_lock_irqsave(&ha->hardware_lock, flags);
  801. }
  802. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  803. return status;
  804. }
  805. static char *reset_errors[] = {
  806. "HBA not online",
  807. "HBA not ready",
  808. "Task management failed",
  809. "Waiting for command completions",
  810. };
  811. static int
  812. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  813. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  814. {
  815. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  816. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  817. int err;
  818. fc_block_scsi_eh(cmd);
  819. if (!fcport)
  820. return FAILED;
  821. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  822. vha->host_no, cmd->device->id, cmd->device->lun, name);
  823. err = 0;
  824. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  825. goto eh_reset_failed;
  826. err = 1;
  827. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  828. goto eh_reset_failed;
  829. err = 2;
  830. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  831. != QLA_SUCCESS)
  832. goto eh_reset_failed;
  833. err = 3;
  834. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  835. cmd->device->lun, type) != QLA_SUCCESS)
  836. goto eh_reset_failed;
  837. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  838. vha->host_no, cmd->device->id, cmd->device->lun, name);
  839. return SUCCESS;
  840. eh_reset_failed:
  841. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  842. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  843. reset_errors[err]);
  844. return FAILED;
  845. }
  846. static int
  847. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  848. {
  849. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  850. struct qla_hw_data *ha = vha->hw;
  851. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  852. ha->isp_ops->lun_reset);
  853. }
  854. static int
  855. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  856. {
  857. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  858. struct qla_hw_data *ha = vha->hw;
  859. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  860. ha->isp_ops->target_reset);
  861. }
  862. /**************************************************************************
  863. * qla2xxx_eh_bus_reset
  864. *
  865. * Description:
  866. * The bus reset function will reset the bus and abort any executing
  867. * commands.
  868. *
  869. * Input:
  870. * cmd = Linux SCSI command packet of the command that cause the
  871. * bus reset.
  872. *
  873. * Returns:
  874. * SUCCESS/FAILURE (defined as macro in scsi.h).
  875. *
  876. **************************************************************************/
  877. static int
  878. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  879. {
  880. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  881. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  882. int ret = FAILED;
  883. unsigned int id, lun;
  884. fc_block_scsi_eh(cmd);
  885. id = cmd->device->id;
  886. lun = cmd->device->lun;
  887. if (!fcport)
  888. return ret;
  889. qla_printk(KERN_INFO, vha->hw,
  890. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  891. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  892. DEBUG2(printk("%s failed:board disabled\n",__func__));
  893. goto eh_bus_reset_done;
  894. }
  895. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  896. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  897. ret = SUCCESS;
  898. }
  899. if (ret == FAILED)
  900. goto eh_bus_reset_done;
  901. /* Flush outstanding commands. */
  902. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  903. QLA_SUCCESS)
  904. ret = FAILED;
  905. eh_bus_reset_done:
  906. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  907. (ret == FAILED) ? "failed" : "succeded");
  908. return ret;
  909. }
  910. /**************************************************************************
  911. * qla2xxx_eh_host_reset
  912. *
  913. * Description:
  914. * The reset function will reset the Adapter.
  915. *
  916. * Input:
  917. * cmd = Linux SCSI command packet of the command that cause the
  918. * adapter reset.
  919. *
  920. * Returns:
  921. * Either SUCCESS or FAILED.
  922. *
  923. * Note:
  924. **************************************************************************/
  925. static int
  926. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  927. {
  928. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  929. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  930. struct qla_hw_data *ha = vha->hw;
  931. int ret = FAILED;
  932. unsigned int id, lun;
  933. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  934. fc_block_scsi_eh(cmd);
  935. id = cmd->device->id;
  936. lun = cmd->device->lun;
  937. if (!fcport)
  938. return ret;
  939. qla_printk(KERN_INFO, ha,
  940. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  941. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  942. goto eh_host_reset_lock;
  943. /*
  944. * Fixme-may be dpc thread is active and processing
  945. * loop_resync,so wait a while for it to
  946. * be completed and then issue big hammer.Otherwise
  947. * it may cause I/O failure as big hammer marks the
  948. * devices as lost kicking of the port_down_timer
  949. * while dpc is stuck for the mailbox to complete.
  950. */
  951. qla2x00_wait_for_loop_ready(vha);
  952. if (vha != base_vha) {
  953. if (qla2x00_vp_abort_isp(vha))
  954. goto eh_host_reset_lock;
  955. } else {
  956. if (IS_QLA82XX(vha->hw)) {
  957. if (!qla82xx_fcoe_ctx_reset(vha)) {
  958. /* Ctx reset success */
  959. ret = SUCCESS;
  960. goto eh_host_reset_lock;
  961. }
  962. /* fall thru if ctx reset failed */
  963. }
  964. if (ha->wq)
  965. flush_workqueue(ha->wq);
  966. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  967. if (ha->isp_ops->abort_isp(base_vha)) {
  968. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  969. /* failed. schedule dpc to try */
  970. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  971. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  972. goto eh_host_reset_lock;
  973. }
  974. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  975. }
  976. /* Waiting for command to be returned to OS.*/
  977. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  978. QLA_SUCCESS)
  979. ret = SUCCESS;
  980. eh_host_reset_lock:
  981. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  982. (ret == FAILED) ? "failed" : "succeded");
  983. return ret;
  984. }
  985. /*
  986. * qla2x00_loop_reset
  987. * Issue loop reset.
  988. *
  989. * Input:
  990. * ha = adapter block pointer.
  991. *
  992. * Returns:
  993. * 0 = success
  994. */
  995. int
  996. qla2x00_loop_reset(scsi_qla_host_t *vha)
  997. {
  998. int ret;
  999. struct fc_port *fcport;
  1000. struct qla_hw_data *ha = vha->hw;
  1001. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  1002. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1003. if (fcport->port_type != FCT_TARGET)
  1004. continue;
  1005. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1006. if (ret != QLA_SUCCESS) {
  1007. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1008. "target_reset=%d d_id=%x.\n", __func__,
  1009. vha->host_no, ret, fcport->d_id.b24));
  1010. }
  1011. }
  1012. }
  1013. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1014. ret = qla2x00_full_login_lip(vha);
  1015. if (ret != QLA_SUCCESS) {
  1016. DEBUG2_3(printk("%s(%ld): failed: "
  1017. "full_login_lip=%d.\n", __func__, vha->host_no,
  1018. ret));
  1019. }
  1020. atomic_set(&vha->loop_state, LOOP_DOWN);
  1021. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1022. qla2x00_mark_all_devices_lost(vha, 0);
  1023. qla2x00_wait_for_loop_ready(vha);
  1024. }
  1025. if (ha->flags.enable_lip_reset) {
  1026. ret = qla2x00_lip_reset(vha);
  1027. if (ret != QLA_SUCCESS) {
  1028. DEBUG2_3(printk("%s(%ld): failed: "
  1029. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1030. } else
  1031. qla2x00_wait_for_loop_ready(vha);
  1032. }
  1033. /* Issue marker command only when we are going to start the I/O */
  1034. vha->marker_needed = 1;
  1035. return QLA_SUCCESS;
  1036. }
  1037. void
  1038. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1039. {
  1040. int que, cnt;
  1041. unsigned long flags;
  1042. srb_t *sp;
  1043. struct srb_ctx *ctx;
  1044. struct qla_hw_data *ha = vha->hw;
  1045. struct req_que *req;
  1046. spin_lock_irqsave(&ha->hardware_lock, flags);
  1047. for (que = 0; que < ha->max_req_queues; que++) {
  1048. req = ha->req_q_map[que];
  1049. if (!req)
  1050. continue;
  1051. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1052. sp = req->outstanding_cmds[cnt];
  1053. if (sp) {
  1054. req->outstanding_cmds[cnt] = NULL;
  1055. if (!sp->ctx ||
  1056. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1057. IS_PROT_IO(sp)) {
  1058. sp->cmd->result = res;
  1059. qla2x00_sp_compl(ha, sp);
  1060. } else {
  1061. ctx = sp->ctx;
  1062. if (ctx->type == SRB_LOGIN_CMD ||
  1063. ctx->type == SRB_LOGOUT_CMD) {
  1064. ctx->u.iocb_cmd->free(sp);
  1065. } else {
  1066. struct fc_bsg_job *bsg_job =
  1067. ctx->u.bsg_job;
  1068. if (bsg_job->request->msgcode
  1069. == FC_BSG_HST_CT)
  1070. kfree(sp->fcport);
  1071. bsg_job->req->errors = 0;
  1072. bsg_job->reply->result = res;
  1073. bsg_job->job_done(bsg_job);
  1074. kfree(sp->ctx);
  1075. mempool_free(sp,
  1076. ha->srb_mempool);
  1077. }
  1078. }
  1079. }
  1080. }
  1081. }
  1082. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1083. }
  1084. static int
  1085. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1086. {
  1087. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1088. if (!rport || fc_remote_port_chkready(rport))
  1089. return -ENXIO;
  1090. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1091. return 0;
  1092. }
  1093. static int
  1094. qla2xxx_slave_configure(struct scsi_device *sdev)
  1095. {
  1096. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1097. struct req_que *req = vha->req;
  1098. if (sdev->tagged_supported)
  1099. scsi_activate_tcq(sdev, req->max_q_depth);
  1100. else
  1101. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1102. return 0;
  1103. }
  1104. static void
  1105. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1106. {
  1107. sdev->hostdata = NULL;
  1108. }
  1109. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1110. {
  1111. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1112. if (!scsi_track_queue_full(sdev, qdepth))
  1113. return;
  1114. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1115. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1116. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1117. sdev->queue_depth));
  1118. }
  1119. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1120. {
  1121. fc_port_t *fcport = sdev->hostdata;
  1122. struct scsi_qla_host *vha = fcport->vha;
  1123. struct qla_hw_data *ha = vha->hw;
  1124. struct req_que *req = NULL;
  1125. req = vha->req;
  1126. if (!req)
  1127. return;
  1128. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1129. return;
  1130. if (sdev->ordered_tags)
  1131. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1132. else
  1133. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1134. DEBUG2(qla_printk(KERN_INFO, ha,
  1135. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1136. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1137. sdev->queue_depth));
  1138. }
  1139. static int
  1140. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1141. {
  1142. switch (reason) {
  1143. case SCSI_QDEPTH_DEFAULT:
  1144. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1145. break;
  1146. case SCSI_QDEPTH_QFULL:
  1147. qla2x00_handle_queue_full(sdev, qdepth);
  1148. break;
  1149. case SCSI_QDEPTH_RAMP_UP:
  1150. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1151. break;
  1152. default:
  1153. return -EOPNOTSUPP;
  1154. }
  1155. return sdev->queue_depth;
  1156. }
  1157. static int
  1158. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1159. {
  1160. if (sdev->tagged_supported) {
  1161. scsi_set_tag_type(sdev, tag_type);
  1162. if (tag_type)
  1163. scsi_activate_tcq(sdev, sdev->queue_depth);
  1164. else
  1165. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1166. } else
  1167. tag_type = 0;
  1168. return tag_type;
  1169. }
  1170. /**
  1171. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1172. * @ha: HA context
  1173. *
  1174. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1175. * supported addressing method.
  1176. */
  1177. static void
  1178. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1179. {
  1180. /* Assume a 32bit DMA mask. */
  1181. ha->flags.enable_64bit_addressing = 0;
  1182. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1183. /* Any upper-dword bits set? */
  1184. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1185. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1186. /* Ok, a 64bit DMA mask is applicable. */
  1187. ha->flags.enable_64bit_addressing = 1;
  1188. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1189. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1190. return;
  1191. }
  1192. }
  1193. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1194. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1195. }
  1196. static void
  1197. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1198. {
  1199. unsigned long flags = 0;
  1200. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1201. spin_lock_irqsave(&ha->hardware_lock, flags);
  1202. ha->interrupts_on = 1;
  1203. /* enable risc and host interrupts */
  1204. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1205. RD_REG_WORD(&reg->ictrl);
  1206. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1207. }
  1208. static void
  1209. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1210. {
  1211. unsigned long flags = 0;
  1212. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1213. spin_lock_irqsave(&ha->hardware_lock, flags);
  1214. ha->interrupts_on = 0;
  1215. /* disable risc and host interrupts */
  1216. WRT_REG_WORD(&reg->ictrl, 0);
  1217. RD_REG_WORD(&reg->ictrl);
  1218. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1219. }
  1220. static void
  1221. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1222. {
  1223. unsigned long flags = 0;
  1224. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1225. spin_lock_irqsave(&ha->hardware_lock, flags);
  1226. ha->interrupts_on = 1;
  1227. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1228. RD_REG_DWORD(&reg->ictrl);
  1229. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1230. }
  1231. static void
  1232. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1233. {
  1234. unsigned long flags = 0;
  1235. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1236. if (IS_NOPOLLING_TYPE(ha))
  1237. return;
  1238. spin_lock_irqsave(&ha->hardware_lock, flags);
  1239. ha->interrupts_on = 0;
  1240. WRT_REG_DWORD(&reg->ictrl, 0);
  1241. RD_REG_DWORD(&reg->ictrl);
  1242. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1243. }
  1244. static struct isp_operations qla2100_isp_ops = {
  1245. .pci_config = qla2100_pci_config,
  1246. .reset_chip = qla2x00_reset_chip,
  1247. .chip_diag = qla2x00_chip_diag,
  1248. .config_rings = qla2x00_config_rings,
  1249. .reset_adapter = qla2x00_reset_adapter,
  1250. .nvram_config = qla2x00_nvram_config,
  1251. .update_fw_options = qla2x00_update_fw_options,
  1252. .load_risc = qla2x00_load_risc,
  1253. .pci_info_str = qla2x00_pci_info_str,
  1254. .fw_version_str = qla2x00_fw_version_str,
  1255. .intr_handler = qla2100_intr_handler,
  1256. .enable_intrs = qla2x00_enable_intrs,
  1257. .disable_intrs = qla2x00_disable_intrs,
  1258. .abort_command = qla2x00_abort_command,
  1259. .target_reset = qla2x00_abort_target,
  1260. .lun_reset = qla2x00_lun_reset,
  1261. .fabric_login = qla2x00_login_fabric,
  1262. .fabric_logout = qla2x00_fabric_logout,
  1263. .calc_req_entries = qla2x00_calc_iocbs_32,
  1264. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1265. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1266. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1267. .read_nvram = qla2x00_read_nvram_data,
  1268. .write_nvram = qla2x00_write_nvram_data,
  1269. .fw_dump = qla2100_fw_dump,
  1270. .beacon_on = NULL,
  1271. .beacon_off = NULL,
  1272. .beacon_blink = NULL,
  1273. .read_optrom = qla2x00_read_optrom_data,
  1274. .write_optrom = qla2x00_write_optrom_data,
  1275. .get_flash_version = qla2x00_get_flash_version,
  1276. .start_scsi = qla2x00_start_scsi,
  1277. .abort_isp = qla2x00_abort_isp,
  1278. };
  1279. static struct isp_operations qla2300_isp_ops = {
  1280. .pci_config = qla2300_pci_config,
  1281. .reset_chip = qla2x00_reset_chip,
  1282. .chip_diag = qla2x00_chip_diag,
  1283. .config_rings = qla2x00_config_rings,
  1284. .reset_adapter = qla2x00_reset_adapter,
  1285. .nvram_config = qla2x00_nvram_config,
  1286. .update_fw_options = qla2x00_update_fw_options,
  1287. .load_risc = qla2x00_load_risc,
  1288. .pci_info_str = qla2x00_pci_info_str,
  1289. .fw_version_str = qla2x00_fw_version_str,
  1290. .intr_handler = qla2300_intr_handler,
  1291. .enable_intrs = qla2x00_enable_intrs,
  1292. .disable_intrs = qla2x00_disable_intrs,
  1293. .abort_command = qla2x00_abort_command,
  1294. .target_reset = qla2x00_abort_target,
  1295. .lun_reset = qla2x00_lun_reset,
  1296. .fabric_login = qla2x00_login_fabric,
  1297. .fabric_logout = qla2x00_fabric_logout,
  1298. .calc_req_entries = qla2x00_calc_iocbs_32,
  1299. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1300. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1301. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1302. .read_nvram = qla2x00_read_nvram_data,
  1303. .write_nvram = qla2x00_write_nvram_data,
  1304. .fw_dump = qla2300_fw_dump,
  1305. .beacon_on = qla2x00_beacon_on,
  1306. .beacon_off = qla2x00_beacon_off,
  1307. .beacon_blink = qla2x00_beacon_blink,
  1308. .read_optrom = qla2x00_read_optrom_data,
  1309. .write_optrom = qla2x00_write_optrom_data,
  1310. .get_flash_version = qla2x00_get_flash_version,
  1311. .start_scsi = qla2x00_start_scsi,
  1312. .abort_isp = qla2x00_abort_isp,
  1313. };
  1314. static struct isp_operations qla24xx_isp_ops = {
  1315. .pci_config = qla24xx_pci_config,
  1316. .reset_chip = qla24xx_reset_chip,
  1317. .chip_diag = qla24xx_chip_diag,
  1318. .config_rings = qla24xx_config_rings,
  1319. .reset_adapter = qla24xx_reset_adapter,
  1320. .nvram_config = qla24xx_nvram_config,
  1321. .update_fw_options = qla24xx_update_fw_options,
  1322. .load_risc = qla24xx_load_risc,
  1323. .pci_info_str = qla24xx_pci_info_str,
  1324. .fw_version_str = qla24xx_fw_version_str,
  1325. .intr_handler = qla24xx_intr_handler,
  1326. .enable_intrs = qla24xx_enable_intrs,
  1327. .disable_intrs = qla24xx_disable_intrs,
  1328. .abort_command = qla24xx_abort_command,
  1329. .target_reset = qla24xx_abort_target,
  1330. .lun_reset = qla24xx_lun_reset,
  1331. .fabric_login = qla24xx_login_fabric,
  1332. .fabric_logout = qla24xx_fabric_logout,
  1333. .calc_req_entries = NULL,
  1334. .build_iocbs = NULL,
  1335. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1336. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1337. .read_nvram = qla24xx_read_nvram_data,
  1338. .write_nvram = qla24xx_write_nvram_data,
  1339. .fw_dump = qla24xx_fw_dump,
  1340. .beacon_on = qla24xx_beacon_on,
  1341. .beacon_off = qla24xx_beacon_off,
  1342. .beacon_blink = qla24xx_beacon_blink,
  1343. .read_optrom = qla24xx_read_optrom_data,
  1344. .write_optrom = qla24xx_write_optrom_data,
  1345. .get_flash_version = qla24xx_get_flash_version,
  1346. .start_scsi = qla24xx_start_scsi,
  1347. .abort_isp = qla2x00_abort_isp,
  1348. };
  1349. static struct isp_operations qla25xx_isp_ops = {
  1350. .pci_config = qla25xx_pci_config,
  1351. .reset_chip = qla24xx_reset_chip,
  1352. .chip_diag = qla24xx_chip_diag,
  1353. .config_rings = qla24xx_config_rings,
  1354. .reset_adapter = qla24xx_reset_adapter,
  1355. .nvram_config = qla24xx_nvram_config,
  1356. .update_fw_options = qla24xx_update_fw_options,
  1357. .load_risc = qla24xx_load_risc,
  1358. .pci_info_str = qla24xx_pci_info_str,
  1359. .fw_version_str = qla24xx_fw_version_str,
  1360. .intr_handler = qla24xx_intr_handler,
  1361. .enable_intrs = qla24xx_enable_intrs,
  1362. .disable_intrs = qla24xx_disable_intrs,
  1363. .abort_command = qla24xx_abort_command,
  1364. .target_reset = qla24xx_abort_target,
  1365. .lun_reset = qla24xx_lun_reset,
  1366. .fabric_login = qla24xx_login_fabric,
  1367. .fabric_logout = qla24xx_fabric_logout,
  1368. .calc_req_entries = NULL,
  1369. .build_iocbs = NULL,
  1370. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1371. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1372. .read_nvram = qla25xx_read_nvram_data,
  1373. .write_nvram = qla25xx_write_nvram_data,
  1374. .fw_dump = qla25xx_fw_dump,
  1375. .beacon_on = qla24xx_beacon_on,
  1376. .beacon_off = qla24xx_beacon_off,
  1377. .beacon_blink = qla24xx_beacon_blink,
  1378. .read_optrom = qla25xx_read_optrom_data,
  1379. .write_optrom = qla24xx_write_optrom_data,
  1380. .get_flash_version = qla24xx_get_flash_version,
  1381. .start_scsi = qla24xx_dif_start_scsi,
  1382. .abort_isp = qla2x00_abort_isp,
  1383. };
  1384. static struct isp_operations qla81xx_isp_ops = {
  1385. .pci_config = qla25xx_pci_config,
  1386. .reset_chip = qla24xx_reset_chip,
  1387. .chip_diag = qla24xx_chip_diag,
  1388. .config_rings = qla24xx_config_rings,
  1389. .reset_adapter = qla24xx_reset_adapter,
  1390. .nvram_config = qla81xx_nvram_config,
  1391. .update_fw_options = qla81xx_update_fw_options,
  1392. .load_risc = qla81xx_load_risc,
  1393. .pci_info_str = qla24xx_pci_info_str,
  1394. .fw_version_str = qla24xx_fw_version_str,
  1395. .intr_handler = qla24xx_intr_handler,
  1396. .enable_intrs = qla24xx_enable_intrs,
  1397. .disable_intrs = qla24xx_disable_intrs,
  1398. .abort_command = qla24xx_abort_command,
  1399. .target_reset = qla24xx_abort_target,
  1400. .lun_reset = qla24xx_lun_reset,
  1401. .fabric_login = qla24xx_login_fabric,
  1402. .fabric_logout = qla24xx_fabric_logout,
  1403. .calc_req_entries = NULL,
  1404. .build_iocbs = NULL,
  1405. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1406. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1407. .read_nvram = NULL,
  1408. .write_nvram = NULL,
  1409. .fw_dump = qla81xx_fw_dump,
  1410. .beacon_on = qla24xx_beacon_on,
  1411. .beacon_off = qla24xx_beacon_off,
  1412. .beacon_blink = qla24xx_beacon_blink,
  1413. .read_optrom = qla25xx_read_optrom_data,
  1414. .write_optrom = qla24xx_write_optrom_data,
  1415. .get_flash_version = qla24xx_get_flash_version,
  1416. .start_scsi = qla24xx_dif_start_scsi,
  1417. .abort_isp = qla2x00_abort_isp,
  1418. };
  1419. static struct isp_operations qla82xx_isp_ops = {
  1420. .pci_config = qla82xx_pci_config,
  1421. .reset_chip = qla82xx_reset_chip,
  1422. .chip_diag = qla24xx_chip_diag,
  1423. .config_rings = qla82xx_config_rings,
  1424. .reset_adapter = qla24xx_reset_adapter,
  1425. .nvram_config = qla81xx_nvram_config,
  1426. .update_fw_options = qla24xx_update_fw_options,
  1427. .load_risc = qla82xx_load_risc,
  1428. .pci_info_str = qla82xx_pci_info_str,
  1429. .fw_version_str = qla24xx_fw_version_str,
  1430. .intr_handler = qla82xx_intr_handler,
  1431. .enable_intrs = qla82xx_enable_intrs,
  1432. .disable_intrs = qla82xx_disable_intrs,
  1433. .abort_command = qla24xx_abort_command,
  1434. .target_reset = qla24xx_abort_target,
  1435. .lun_reset = qla24xx_lun_reset,
  1436. .fabric_login = qla24xx_login_fabric,
  1437. .fabric_logout = qla24xx_fabric_logout,
  1438. .calc_req_entries = NULL,
  1439. .build_iocbs = NULL,
  1440. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1441. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1442. .read_nvram = qla24xx_read_nvram_data,
  1443. .write_nvram = qla24xx_write_nvram_data,
  1444. .fw_dump = qla24xx_fw_dump,
  1445. .beacon_on = qla24xx_beacon_on,
  1446. .beacon_off = qla24xx_beacon_off,
  1447. .beacon_blink = qla24xx_beacon_blink,
  1448. .read_optrom = qla82xx_read_optrom_data,
  1449. .write_optrom = qla82xx_write_optrom_data,
  1450. .get_flash_version = qla24xx_get_flash_version,
  1451. .start_scsi = qla82xx_start_scsi,
  1452. .abort_isp = qla82xx_abort_isp,
  1453. };
  1454. static inline void
  1455. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1456. {
  1457. ha->device_type = DT_EXTENDED_IDS;
  1458. switch (ha->pdev->device) {
  1459. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1460. ha->device_type |= DT_ISP2100;
  1461. ha->device_type &= ~DT_EXTENDED_IDS;
  1462. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1463. break;
  1464. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1465. ha->device_type |= DT_ISP2200;
  1466. ha->device_type &= ~DT_EXTENDED_IDS;
  1467. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1468. break;
  1469. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1470. ha->device_type |= DT_ISP2300;
  1471. ha->device_type |= DT_ZIO_SUPPORTED;
  1472. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1473. break;
  1474. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1475. ha->device_type |= DT_ISP2312;
  1476. ha->device_type |= DT_ZIO_SUPPORTED;
  1477. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1478. break;
  1479. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1480. ha->device_type |= DT_ISP2322;
  1481. ha->device_type |= DT_ZIO_SUPPORTED;
  1482. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1483. ha->pdev->subsystem_device == 0x0170)
  1484. ha->device_type |= DT_OEM_001;
  1485. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1486. break;
  1487. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1488. ha->device_type |= DT_ISP6312;
  1489. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1490. break;
  1491. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1492. ha->device_type |= DT_ISP6322;
  1493. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1494. break;
  1495. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1496. ha->device_type |= DT_ISP2422;
  1497. ha->device_type |= DT_ZIO_SUPPORTED;
  1498. ha->device_type |= DT_FWI2;
  1499. ha->device_type |= DT_IIDMA;
  1500. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1501. break;
  1502. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1503. ha->device_type |= DT_ISP2432;
  1504. ha->device_type |= DT_ZIO_SUPPORTED;
  1505. ha->device_type |= DT_FWI2;
  1506. ha->device_type |= DT_IIDMA;
  1507. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1508. break;
  1509. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1510. ha->device_type |= DT_ISP8432;
  1511. ha->device_type |= DT_ZIO_SUPPORTED;
  1512. ha->device_type |= DT_FWI2;
  1513. ha->device_type |= DT_IIDMA;
  1514. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1515. break;
  1516. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1517. ha->device_type |= DT_ISP5422;
  1518. ha->device_type |= DT_FWI2;
  1519. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1520. break;
  1521. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1522. ha->device_type |= DT_ISP5432;
  1523. ha->device_type |= DT_FWI2;
  1524. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1525. break;
  1526. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1527. ha->device_type |= DT_ISP2532;
  1528. ha->device_type |= DT_ZIO_SUPPORTED;
  1529. ha->device_type |= DT_FWI2;
  1530. ha->device_type |= DT_IIDMA;
  1531. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1532. break;
  1533. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1534. ha->device_type |= DT_ISP8001;
  1535. ha->device_type |= DT_ZIO_SUPPORTED;
  1536. ha->device_type |= DT_FWI2;
  1537. ha->device_type |= DT_IIDMA;
  1538. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1539. break;
  1540. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1541. ha->device_type |= DT_ISP8021;
  1542. ha->device_type |= DT_ZIO_SUPPORTED;
  1543. ha->device_type |= DT_FWI2;
  1544. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1545. /* Initialize 82XX ISP flags */
  1546. qla82xx_init_flags(ha);
  1547. break;
  1548. }
  1549. if (IS_QLA82XX(ha))
  1550. ha->port_no = !(ha->portnum & 1);
  1551. else
  1552. /* Get adapter physical port no from interrupt pin register. */
  1553. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1554. if (ha->port_no & 1)
  1555. ha->flags.port0 = 1;
  1556. else
  1557. ha->flags.port0 = 0;
  1558. }
  1559. static int
  1560. qla2x00_iospace_config(struct qla_hw_data *ha)
  1561. {
  1562. resource_size_t pio;
  1563. uint16_t msix;
  1564. int cpus;
  1565. if (IS_QLA82XX(ha))
  1566. return qla82xx_iospace_config(ha);
  1567. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1568. QLA2XXX_DRIVER_NAME)) {
  1569. qla_printk(KERN_WARNING, ha,
  1570. "Failed to reserve PIO/MMIO regions (%s)\n",
  1571. pci_name(ha->pdev));
  1572. goto iospace_error_exit;
  1573. }
  1574. if (!(ha->bars & 1))
  1575. goto skip_pio;
  1576. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1577. pio = pci_resource_start(ha->pdev, 0);
  1578. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1579. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1580. qla_printk(KERN_WARNING, ha,
  1581. "Invalid PCI I/O region size (%s)...\n",
  1582. pci_name(ha->pdev));
  1583. pio = 0;
  1584. }
  1585. } else {
  1586. qla_printk(KERN_WARNING, ha,
  1587. "region #0 not a PIO resource (%s)...\n",
  1588. pci_name(ha->pdev));
  1589. pio = 0;
  1590. }
  1591. ha->pio_address = pio;
  1592. skip_pio:
  1593. /* Use MMIO operations for all accesses. */
  1594. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1595. qla_printk(KERN_ERR, ha,
  1596. "region #1 not an MMIO resource (%s), aborting\n",
  1597. pci_name(ha->pdev));
  1598. goto iospace_error_exit;
  1599. }
  1600. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1601. qla_printk(KERN_ERR, ha,
  1602. "Invalid PCI mem region size (%s), aborting\n",
  1603. pci_name(ha->pdev));
  1604. goto iospace_error_exit;
  1605. }
  1606. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1607. if (!ha->iobase) {
  1608. qla_printk(KERN_ERR, ha,
  1609. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1610. goto iospace_error_exit;
  1611. }
  1612. /* Determine queue resources */
  1613. ha->max_req_queues = ha->max_rsp_queues = 1;
  1614. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1615. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1616. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1617. goto mqiobase_exit;
  1618. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1619. pci_resource_len(ha->pdev, 3));
  1620. if (ha->mqiobase) {
  1621. /* Read MSIX vector size of the board */
  1622. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1623. ha->msix_count = msix;
  1624. /* Max queues are bounded by available msix vectors */
  1625. /* queue 0 uses two msix vectors */
  1626. if (ql2xmultique_tag) {
  1627. cpus = num_online_cpus();
  1628. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1629. (cpus + 1) : (ha->msix_count - 1);
  1630. ha->max_req_queues = 2;
  1631. } else if (ql2xmaxqueues > 1) {
  1632. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1633. QLA_MQ_SIZE : ql2xmaxqueues;
  1634. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1635. " of request queues:%d\n", ha->max_req_queues));
  1636. }
  1637. qla_printk(KERN_INFO, ha,
  1638. "MSI-X vector count: %d\n", msix);
  1639. } else
  1640. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1641. mqiobase_exit:
  1642. ha->msix_count = ha->max_rsp_queues + 1;
  1643. return (0);
  1644. iospace_error_exit:
  1645. return (-ENOMEM);
  1646. }
  1647. static void
  1648. qla2xxx_scan_start(struct Scsi_Host *shost)
  1649. {
  1650. scsi_qla_host_t *vha = shost_priv(shost);
  1651. if (vha->hw->flags.running_gold_fw)
  1652. return;
  1653. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1654. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1655. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1656. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1657. }
  1658. static int
  1659. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1660. {
  1661. scsi_qla_host_t *vha = shost_priv(shost);
  1662. if (!vha->host)
  1663. return 1;
  1664. if (time > vha->hw->loop_reset_delay * HZ)
  1665. return 1;
  1666. return atomic_read(&vha->loop_state) == LOOP_READY;
  1667. }
  1668. /*
  1669. * PCI driver interface
  1670. */
  1671. static int __devinit
  1672. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1673. {
  1674. int ret = -ENODEV;
  1675. struct Scsi_Host *host;
  1676. scsi_qla_host_t *base_vha = NULL;
  1677. struct qla_hw_data *ha;
  1678. char pci_info[30];
  1679. char fw_str[30];
  1680. struct scsi_host_template *sht;
  1681. int bars, max_id, mem_only = 0;
  1682. uint16_t req_length = 0, rsp_length = 0;
  1683. struct req_que *req = NULL;
  1684. struct rsp_que *rsp = NULL;
  1685. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1686. sht = &qla2xxx_driver_template;
  1687. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1688. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1689. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1690. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1691. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1692. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1693. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1694. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1695. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1696. mem_only = 1;
  1697. }
  1698. if (mem_only) {
  1699. if (pci_enable_device_mem(pdev))
  1700. goto probe_out;
  1701. } else {
  1702. if (pci_enable_device(pdev))
  1703. goto probe_out;
  1704. }
  1705. /* This may fail but that's ok */
  1706. pci_enable_pcie_error_reporting(pdev);
  1707. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1708. if (!ha) {
  1709. DEBUG(printk("Unable to allocate memory for ha\n"));
  1710. goto probe_out;
  1711. }
  1712. ha->pdev = pdev;
  1713. /* Clear our data area */
  1714. ha->bars = bars;
  1715. ha->mem_only = mem_only;
  1716. spin_lock_init(&ha->hardware_lock);
  1717. spin_lock_init(&ha->vport_slock);
  1718. /* Set ISP-type information. */
  1719. qla2x00_set_isp_flags(ha);
  1720. /* Set EEH reset type to fundamental if required by hba */
  1721. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1722. pdev->needs_freset = 1;
  1723. }
  1724. /* Configure PCI I/O space */
  1725. ret = qla2x00_iospace_config(ha);
  1726. if (ret)
  1727. goto probe_hw_failed;
  1728. qla_printk(KERN_INFO, ha,
  1729. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1730. ha->iobase);
  1731. ha->prev_topology = 0;
  1732. ha->init_cb_size = sizeof(init_cb_t);
  1733. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1734. ha->optrom_size = OPTROM_SIZE_2300;
  1735. /* Assign ISP specific operations. */
  1736. max_id = MAX_TARGETS_2200;
  1737. if (IS_QLA2100(ha)) {
  1738. max_id = MAX_TARGETS_2100;
  1739. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1740. req_length = REQUEST_ENTRY_CNT_2100;
  1741. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1742. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1743. ha->gid_list_info_size = 4;
  1744. ha->flash_conf_off = ~0;
  1745. ha->flash_data_off = ~0;
  1746. ha->nvram_conf_off = ~0;
  1747. ha->nvram_data_off = ~0;
  1748. ha->isp_ops = &qla2100_isp_ops;
  1749. } else if (IS_QLA2200(ha)) {
  1750. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1751. req_length = REQUEST_ENTRY_CNT_2200;
  1752. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1753. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1754. ha->gid_list_info_size = 4;
  1755. ha->flash_conf_off = ~0;
  1756. ha->flash_data_off = ~0;
  1757. ha->nvram_conf_off = ~0;
  1758. ha->nvram_data_off = ~0;
  1759. ha->isp_ops = &qla2100_isp_ops;
  1760. } else if (IS_QLA23XX(ha)) {
  1761. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1762. req_length = REQUEST_ENTRY_CNT_2200;
  1763. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1764. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1765. ha->gid_list_info_size = 6;
  1766. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1767. ha->optrom_size = OPTROM_SIZE_2322;
  1768. ha->flash_conf_off = ~0;
  1769. ha->flash_data_off = ~0;
  1770. ha->nvram_conf_off = ~0;
  1771. ha->nvram_data_off = ~0;
  1772. ha->isp_ops = &qla2300_isp_ops;
  1773. } else if (IS_QLA24XX_TYPE(ha)) {
  1774. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1775. req_length = REQUEST_ENTRY_CNT_24XX;
  1776. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1777. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1778. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1779. ha->gid_list_info_size = 8;
  1780. ha->optrom_size = OPTROM_SIZE_24XX;
  1781. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1782. ha->isp_ops = &qla24xx_isp_ops;
  1783. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1784. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1785. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1786. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1787. } else if (IS_QLA25XX(ha)) {
  1788. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1789. req_length = REQUEST_ENTRY_CNT_24XX;
  1790. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1791. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1792. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1793. ha->gid_list_info_size = 8;
  1794. ha->optrom_size = OPTROM_SIZE_25XX;
  1795. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1796. ha->isp_ops = &qla25xx_isp_ops;
  1797. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1798. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1799. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1800. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1801. } else if (IS_QLA81XX(ha)) {
  1802. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1803. req_length = REQUEST_ENTRY_CNT_24XX;
  1804. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1805. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1806. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1807. ha->gid_list_info_size = 8;
  1808. ha->optrom_size = OPTROM_SIZE_81XX;
  1809. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1810. ha->isp_ops = &qla81xx_isp_ops;
  1811. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1812. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1813. ha->nvram_conf_off = ~0;
  1814. ha->nvram_data_off = ~0;
  1815. } else if (IS_QLA82XX(ha)) {
  1816. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1817. req_length = REQUEST_ENTRY_CNT_82XX;
  1818. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1819. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1820. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1821. ha->gid_list_info_size = 8;
  1822. ha->optrom_size = OPTROM_SIZE_82XX;
  1823. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1824. ha->isp_ops = &qla82xx_isp_ops;
  1825. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1826. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1827. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1828. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1829. }
  1830. mutex_init(&ha->vport_lock);
  1831. init_completion(&ha->mbx_cmd_comp);
  1832. complete(&ha->mbx_cmd_comp);
  1833. init_completion(&ha->mbx_intr_comp);
  1834. init_completion(&ha->dcbx_comp);
  1835. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1836. qla2x00_config_dma_addressing(ha);
  1837. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1838. if (!ret) {
  1839. qla_printk(KERN_WARNING, ha,
  1840. "[ERROR] Failed to allocate memory for adapter\n");
  1841. goto probe_hw_failed;
  1842. }
  1843. req->max_q_depth = MAX_Q_DEPTH;
  1844. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1845. req->max_q_depth = ql2xmaxqdepth;
  1846. base_vha = qla2x00_create_host(sht, ha);
  1847. if (!base_vha) {
  1848. qla_printk(KERN_WARNING, ha,
  1849. "[ERROR] Failed to allocate memory for scsi_host\n");
  1850. ret = -ENOMEM;
  1851. qla2x00_mem_free(ha);
  1852. qla2x00_free_req_que(ha, req);
  1853. qla2x00_free_rsp_que(ha, rsp);
  1854. goto probe_hw_failed;
  1855. }
  1856. pci_set_drvdata(pdev, base_vha);
  1857. host = base_vha->host;
  1858. base_vha->req = req;
  1859. host->can_queue = req->length + 128;
  1860. if (IS_QLA2XXX_MIDTYPE(ha))
  1861. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1862. else
  1863. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1864. base_vha->vp_idx;
  1865. /* Set the SG table size based on ISP type */
  1866. if (!IS_FWI2_CAPABLE(ha)) {
  1867. if (IS_QLA2100(ha))
  1868. host->sg_tablesize = 32;
  1869. } else {
  1870. if (!IS_QLA82XX(ha))
  1871. host->sg_tablesize = QLA_SG_ALL;
  1872. }
  1873. host->max_id = max_id;
  1874. host->this_id = 255;
  1875. host->cmd_per_lun = 3;
  1876. host->unique_id = host->host_no;
  1877. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1878. host->max_cmd_len = 32;
  1879. else
  1880. host->max_cmd_len = MAX_CMDSZ;
  1881. host->max_channel = MAX_BUSES - 1;
  1882. host->max_lun = MAX_LUNS;
  1883. host->transportt = qla2xxx_transport_template;
  1884. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1885. /* Set up the irqs */
  1886. ret = qla2x00_request_irqs(ha, rsp);
  1887. if (ret)
  1888. goto probe_init_failed;
  1889. pci_save_state(pdev);
  1890. /* Alloc arrays of request and response ring ptrs */
  1891. que_init:
  1892. if (!qla2x00_alloc_queues(ha)) {
  1893. qla_printk(KERN_WARNING, ha,
  1894. "[ERROR] Failed to allocate memory for queue"
  1895. " pointers\n");
  1896. goto probe_init_failed;
  1897. }
  1898. ha->rsp_q_map[0] = rsp;
  1899. ha->req_q_map[0] = req;
  1900. rsp->req = req;
  1901. req->rsp = rsp;
  1902. set_bit(0, ha->req_qid_map);
  1903. set_bit(0, ha->rsp_qid_map);
  1904. /* FWI2-capable only. */
  1905. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1906. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1907. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1908. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1909. if (ha->mqenable) {
  1910. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1911. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1912. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1913. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1914. }
  1915. if (IS_QLA82XX(ha)) {
  1916. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1917. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1918. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1919. }
  1920. if (qla2x00_initialize_adapter(base_vha)) {
  1921. qla_printk(KERN_WARNING, ha,
  1922. "Failed to initialize adapter\n");
  1923. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1924. "Adapter flags %x.\n",
  1925. base_vha->host_no, base_vha->device_flags));
  1926. if (IS_QLA82XX(ha)) {
  1927. qla82xx_idc_lock(ha);
  1928. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1929. QLA82XX_DEV_FAILED);
  1930. qla82xx_idc_unlock(ha);
  1931. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1932. }
  1933. ret = -ENODEV;
  1934. goto probe_failed;
  1935. }
  1936. if (ha->mqenable) {
  1937. if (qla25xx_setup_mode(base_vha)) {
  1938. qla_printk(KERN_WARNING, ha,
  1939. "Can't create queues, falling back to single"
  1940. " queue mode\n");
  1941. goto que_init;
  1942. }
  1943. }
  1944. if (ha->flags.running_gold_fw)
  1945. goto skip_dpc;
  1946. /*
  1947. * Startup the kernel thread for this host adapter
  1948. */
  1949. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1950. "%s_dpc", base_vha->host_str);
  1951. if (IS_ERR(ha->dpc_thread)) {
  1952. qla_printk(KERN_WARNING, ha,
  1953. "Unable to start DPC thread!\n");
  1954. ret = PTR_ERR(ha->dpc_thread);
  1955. goto probe_failed;
  1956. }
  1957. skip_dpc:
  1958. list_add_tail(&base_vha->list, &ha->vp_list);
  1959. base_vha->host->irq = ha->pdev->irq;
  1960. /* Initialized the timer */
  1961. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1962. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1963. base_vha->host_no, ha));
  1964. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1965. if (ha->fw_attributes & BIT_4) {
  1966. base_vha->flags.difdix_supported = 1;
  1967. DEBUG18(qla_printk(KERN_INFO, ha,
  1968. "Registering for DIF/DIX type 1 and 3"
  1969. " protection.\n"));
  1970. scsi_host_set_prot(host,
  1971. SHOST_DIF_TYPE1_PROTECTION
  1972. | SHOST_DIF_TYPE2_PROTECTION
  1973. | SHOST_DIF_TYPE3_PROTECTION
  1974. | SHOST_DIX_TYPE1_PROTECTION
  1975. | SHOST_DIX_TYPE2_PROTECTION
  1976. | SHOST_DIX_TYPE3_PROTECTION);
  1977. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1978. } else
  1979. base_vha->flags.difdix_supported = 0;
  1980. }
  1981. ha->isp_ops->enable_intrs(ha);
  1982. ret = scsi_add_host(host, &pdev->dev);
  1983. if (ret)
  1984. goto probe_failed;
  1985. base_vha->flags.init_done = 1;
  1986. base_vha->flags.online = 1;
  1987. scsi_scan_host(host);
  1988. qla2x00_alloc_sysfs_attr(base_vha);
  1989. qla2x00_init_host_attr(base_vha);
  1990. qla2x00_dfs_setup(base_vha);
  1991. qla_printk(KERN_INFO, ha, "\n"
  1992. " QLogic Fibre Channel HBA Driver: %s\n"
  1993. " QLogic %s - %s\n"
  1994. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  1995. qla2x00_version_str, ha->model_number,
  1996. ha->model_desc ? ha->model_desc : "", pdev->device,
  1997. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  1998. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  1999. ha->isp_ops->fw_version_str(base_vha, fw_str));
  2000. return 0;
  2001. probe_init_failed:
  2002. qla2x00_free_req_que(ha, req);
  2003. qla2x00_free_rsp_que(ha, rsp);
  2004. ha->max_req_queues = ha->max_rsp_queues = 0;
  2005. probe_failed:
  2006. if (base_vha->timer_active)
  2007. qla2x00_stop_timer(base_vha);
  2008. base_vha->flags.online = 0;
  2009. if (ha->dpc_thread) {
  2010. struct task_struct *t = ha->dpc_thread;
  2011. ha->dpc_thread = NULL;
  2012. kthread_stop(t);
  2013. }
  2014. qla2x00_free_device(base_vha);
  2015. scsi_host_put(base_vha->host);
  2016. probe_hw_failed:
  2017. if (IS_QLA82XX(ha)) {
  2018. qla82xx_idc_lock(ha);
  2019. qla82xx_clear_drv_active(ha);
  2020. qla82xx_idc_unlock(ha);
  2021. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2022. if (!ql2xdbwr)
  2023. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2024. } else {
  2025. if (ha->iobase)
  2026. iounmap(ha->iobase);
  2027. }
  2028. pci_release_selected_regions(ha->pdev, ha->bars);
  2029. kfree(ha);
  2030. ha = NULL;
  2031. probe_out:
  2032. pci_disable_device(pdev);
  2033. return ret;
  2034. }
  2035. static void
  2036. qla2x00_shutdown(struct pci_dev *pdev)
  2037. {
  2038. scsi_qla_host_t *vha;
  2039. struct qla_hw_data *ha;
  2040. vha = pci_get_drvdata(pdev);
  2041. ha = vha->hw;
  2042. /* Turn-off FCE trace */
  2043. if (ha->flags.fce_enabled) {
  2044. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2045. ha->flags.fce_enabled = 0;
  2046. }
  2047. /* Turn-off EFT trace */
  2048. if (ha->eft)
  2049. qla2x00_disable_eft_trace(vha);
  2050. /* Stop currently executing firmware. */
  2051. qla2x00_try_to_stop_firmware(vha);
  2052. /* Turn adapter off line */
  2053. vha->flags.online = 0;
  2054. /* turn-off interrupts on the card */
  2055. if (ha->interrupts_on) {
  2056. vha->flags.init_done = 0;
  2057. ha->isp_ops->disable_intrs(ha);
  2058. }
  2059. qla2x00_free_irqs(vha);
  2060. qla2x00_free_fw_dump(ha);
  2061. }
  2062. static void
  2063. qla2x00_remove_one(struct pci_dev *pdev)
  2064. {
  2065. scsi_qla_host_t *base_vha, *vha;
  2066. struct qla_hw_data *ha;
  2067. unsigned long flags;
  2068. base_vha = pci_get_drvdata(pdev);
  2069. ha = base_vha->hw;
  2070. spin_lock_irqsave(&ha->vport_slock, flags);
  2071. list_for_each_entry(vha, &ha->vp_list, list) {
  2072. atomic_inc(&vha->vref_count);
  2073. if (vha && vha->fc_vport) {
  2074. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2075. fc_vport_terminate(vha->fc_vport);
  2076. spin_lock_irqsave(&ha->vport_slock, flags);
  2077. }
  2078. atomic_dec(&vha->vref_count);
  2079. }
  2080. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2081. set_bit(UNLOADING, &base_vha->dpc_flags);
  2082. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2083. qla2x00_dfs_remove(base_vha);
  2084. qla84xx_put_chip(base_vha);
  2085. /* Disable timer */
  2086. if (base_vha->timer_active)
  2087. qla2x00_stop_timer(base_vha);
  2088. base_vha->flags.online = 0;
  2089. /* Flush the work queue and remove it */
  2090. if (ha->wq) {
  2091. flush_workqueue(ha->wq);
  2092. destroy_workqueue(ha->wq);
  2093. ha->wq = NULL;
  2094. }
  2095. /* Kill the kernel thread for this host */
  2096. if (ha->dpc_thread) {
  2097. struct task_struct *t = ha->dpc_thread;
  2098. /*
  2099. * qla2xxx_wake_dpc checks for ->dpc_thread
  2100. * so we need to zero it out.
  2101. */
  2102. ha->dpc_thread = NULL;
  2103. kthread_stop(t);
  2104. }
  2105. qla2x00_free_sysfs_attr(base_vha);
  2106. fc_remove_host(base_vha->host);
  2107. scsi_remove_host(base_vha->host);
  2108. qla2x00_free_device(base_vha);
  2109. scsi_host_put(base_vha->host);
  2110. if (IS_QLA82XX(ha)) {
  2111. qla82xx_idc_lock(ha);
  2112. qla82xx_clear_drv_active(ha);
  2113. qla82xx_idc_unlock(ha);
  2114. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2115. if (!ql2xdbwr)
  2116. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2117. } else {
  2118. if (ha->iobase)
  2119. iounmap(ha->iobase);
  2120. if (ha->mqiobase)
  2121. iounmap(ha->mqiobase);
  2122. }
  2123. pci_release_selected_regions(ha->pdev, ha->bars);
  2124. kfree(ha);
  2125. ha = NULL;
  2126. pci_disable_pcie_error_reporting(pdev);
  2127. pci_disable_device(pdev);
  2128. pci_set_drvdata(pdev, NULL);
  2129. }
  2130. static void
  2131. qla2x00_free_device(scsi_qla_host_t *vha)
  2132. {
  2133. struct qla_hw_data *ha = vha->hw;
  2134. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2135. /* Disable timer */
  2136. if (vha->timer_active)
  2137. qla2x00_stop_timer(vha);
  2138. /* Kill the kernel thread for this host */
  2139. if (ha->dpc_thread) {
  2140. struct task_struct *t = ha->dpc_thread;
  2141. /*
  2142. * qla2xxx_wake_dpc checks for ->dpc_thread
  2143. * so we need to zero it out.
  2144. */
  2145. ha->dpc_thread = NULL;
  2146. kthread_stop(t);
  2147. }
  2148. qla25xx_delete_queues(vha);
  2149. if (ha->flags.fce_enabled)
  2150. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2151. if (ha->eft)
  2152. qla2x00_disable_eft_trace(vha);
  2153. /* Stop currently executing firmware. */
  2154. qla2x00_try_to_stop_firmware(vha);
  2155. vha->flags.online = 0;
  2156. /* turn-off interrupts on the card */
  2157. if (ha->interrupts_on) {
  2158. vha->flags.init_done = 0;
  2159. ha->isp_ops->disable_intrs(ha);
  2160. }
  2161. qla2x00_free_irqs(vha);
  2162. qla2x00_free_fcports(vha);
  2163. qla2x00_mem_free(ha);
  2164. qla2x00_free_queues(ha);
  2165. }
  2166. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2167. {
  2168. fc_port_t *fcport, *tfcport;
  2169. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2170. list_del(&fcport->list);
  2171. kfree(fcport);
  2172. fcport = NULL;
  2173. }
  2174. }
  2175. static inline void
  2176. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2177. int defer)
  2178. {
  2179. struct fc_rport *rport;
  2180. scsi_qla_host_t *base_vha;
  2181. if (!fcport->rport)
  2182. return;
  2183. rport = fcport->rport;
  2184. if (defer) {
  2185. base_vha = pci_get_drvdata(vha->hw->pdev);
  2186. spin_lock_irq(vha->host->host_lock);
  2187. fcport->drport = rport;
  2188. spin_unlock_irq(vha->host->host_lock);
  2189. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2190. qla2xxx_wake_dpc(base_vha);
  2191. } else
  2192. fc_remote_port_delete(rport);
  2193. }
  2194. /*
  2195. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2196. *
  2197. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2198. *
  2199. * Return: None.
  2200. *
  2201. * Context:
  2202. */
  2203. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2204. int do_login, int defer)
  2205. {
  2206. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2207. vha->vp_idx == fcport->vp_idx) {
  2208. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2209. qla2x00_schedule_rport_del(vha, fcport, defer);
  2210. }
  2211. /*
  2212. * We may need to retry the login, so don't change the state of the
  2213. * port but do the retries.
  2214. */
  2215. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2216. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2217. if (!do_login)
  2218. return;
  2219. if (fcport->login_retry == 0) {
  2220. fcport->login_retry = vha->hw->login_retry_count;
  2221. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2222. DEBUG(printk("scsi(%ld): Port login retry: "
  2223. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2224. "id = 0x%04x retry cnt=%d\n",
  2225. vha->host_no,
  2226. fcport->port_name[0],
  2227. fcport->port_name[1],
  2228. fcport->port_name[2],
  2229. fcport->port_name[3],
  2230. fcport->port_name[4],
  2231. fcport->port_name[5],
  2232. fcport->port_name[6],
  2233. fcport->port_name[7],
  2234. fcport->loop_id,
  2235. fcport->login_retry));
  2236. }
  2237. }
  2238. /*
  2239. * qla2x00_mark_all_devices_lost
  2240. * Updates fcport state when device goes offline.
  2241. *
  2242. * Input:
  2243. * ha = adapter block pointer.
  2244. * fcport = port structure pointer.
  2245. *
  2246. * Return:
  2247. * None.
  2248. *
  2249. * Context:
  2250. */
  2251. void
  2252. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2253. {
  2254. fc_port_t *fcport;
  2255. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2256. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2257. continue;
  2258. /*
  2259. * No point in marking the device as lost, if the device is
  2260. * already DEAD.
  2261. */
  2262. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2263. continue;
  2264. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2265. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2266. if (defer)
  2267. qla2x00_schedule_rport_del(vha, fcport, defer);
  2268. else if (vha->vp_idx == fcport->vp_idx)
  2269. qla2x00_schedule_rport_del(vha, fcport, defer);
  2270. }
  2271. }
  2272. }
  2273. /*
  2274. * qla2x00_mem_alloc
  2275. * Allocates adapter memory.
  2276. *
  2277. * Returns:
  2278. * 0 = success.
  2279. * !0 = failure.
  2280. */
  2281. static int
  2282. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2283. struct req_que **req, struct rsp_que **rsp)
  2284. {
  2285. char name[16];
  2286. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2287. &ha->init_cb_dma, GFP_KERNEL);
  2288. if (!ha->init_cb)
  2289. goto fail;
  2290. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2291. &ha->gid_list_dma, GFP_KERNEL);
  2292. if (!ha->gid_list)
  2293. goto fail_free_init_cb;
  2294. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2295. if (!ha->srb_mempool)
  2296. goto fail_free_gid_list;
  2297. if (IS_QLA82XX(ha)) {
  2298. /* Allocate cache for CT6 Ctx. */
  2299. if (!ctx_cachep) {
  2300. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2301. sizeof(struct ct6_dsd), 0,
  2302. SLAB_HWCACHE_ALIGN, NULL);
  2303. if (!ctx_cachep)
  2304. goto fail_free_gid_list;
  2305. }
  2306. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2307. ctx_cachep);
  2308. if (!ha->ctx_mempool)
  2309. goto fail_free_srb_mempool;
  2310. }
  2311. /* Get memory for cached NVRAM */
  2312. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2313. if (!ha->nvram)
  2314. goto fail_free_ctx_mempool;
  2315. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2316. ha->pdev->device);
  2317. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2318. DMA_POOL_SIZE, 8, 0);
  2319. if (!ha->s_dma_pool)
  2320. goto fail_free_nvram;
  2321. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2322. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2323. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2324. if (!ha->dl_dma_pool) {
  2325. qla_printk(KERN_WARNING, ha,
  2326. "Memory Allocation failed - dl_dma_pool\n");
  2327. goto fail_s_dma_pool;
  2328. }
  2329. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2330. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2331. if (!ha->fcp_cmnd_dma_pool) {
  2332. qla_printk(KERN_WARNING, ha,
  2333. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2334. goto fail_dl_dma_pool;
  2335. }
  2336. }
  2337. /* Allocate memory for SNS commands */
  2338. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2339. /* Get consistent memory allocated for SNS commands */
  2340. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2341. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2342. if (!ha->sns_cmd)
  2343. goto fail_dma_pool;
  2344. } else {
  2345. /* Get consistent memory allocated for MS IOCB */
  2346. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2347. &ha->ms_iocb_dma);
  2348. if (!ha->ms_iocb)
  2349. goto fail_dma_pool;
  2350. /* Get consistent memory allocated for CT SNS commands */
  2351. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2352. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2353. if (!ha->ct_sns)
  2354. goto fail_free_ms_iocb;
  2355. }
  2356. /* Allocate memory for request ring */
  2357. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2358. if (!*req) {
  2359. DEBUG(printk("Unable to allocate memory for req\n"));
  2360. goto fail_req;
  2361. }
  2362. (*req)->length = req_len;
  2363. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2364. ((*req)->length + 1) * sizeof(request_t),
  2365. &(*req)->dma, GFP_KERNEL);
  2366. if (!(*req)->ring) {
  2367. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2368. goto fail_req_ring;
  2369. }
  2370. /* Allocate memory for response ring */
  2371. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2372. if (!*rsp) {
  2373. qla_printk(KERN_WARNING, ha,
  2374. "Unable to allocate memory for rsp\n");
  2375. goto fail_rsp;
  2376. }
  2377. (*rsp)->hw = ha;
  2378. (*rsp)->length = rsp_len;
  2379. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2380. ((*rsp)->length + 1) * sizeof(response_t),
  2381. &(*rsp)->dma, GFP_KERNEL);
  2382. if (!(*rsp)->ring) {
  2383. qla_printk(KERN_WARNING, ha,
  2384. "Unable to allocate memory for rsp_ring\n");
  2385. goto fail_rsp_ring;
  2386. }
  2387. (*req)->rsp = *rsp;
  2388. (*rsp)->req = *req;
  2389. /* Allocate memory for NVRAM data for vports */
  2390. if (ha->nvram_npiv_size) {
  2391. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2392. ha->nvram_npiv_size, GFP_KERNEL);
  2393. if (!ha->npiv_info) {
  2394. qla_printk(KERN_WARNING, ha,
  2395. "Unable to allocate memory for npiv info\n");
  2396. goto fail_npiv_info;
  2397. }
  2398. } else
  2399. ha->npiv_info = NULL;
  2400. /* Get consistent memory allocated for EX-INIT-CB. */
  2401. if (IS_QLA8XXX_TYPE(ha)) {
  2402. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2403. &ha->ex_init_cb_dma);
  2404. if (!ha->ex_init_cb)
  2405. goto fail_ex_init_cb;
  2406. }
  2407. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2408. /* Get consistent memory allocated for Async Port-Database. */
  2409. if (!IS_FWI2_CAPABLE(ha)) {
  2410. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2411. &ha->async_pd_dma);
  2412. if (!ha->async_pd)
  2413. goto fail_async_pd;
  2414. }
  2415. INIT_LIST_HEAD(&ha->vp_list);
  2416. return 1;
  2417. fail_async_pd:
  2418. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2419. fail_ex_init_cb:
  2420. kfree(ha->npiv_info);
  2421. fail_npiv_info:
  2422. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2423. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2424. (*rsp)->ring = NULL;
  2425. (*rsp)->dma = 0;
  2426. fail_rsp_ring:
  2427. kfree(*rsp);
  2428. fail_rsp:
  2429. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2430. sizeof(request_t), (*req)->ring, (*req)->dma);
  2431. (*req)->ring = NULL;
  2432. (*req)->dma = 0;
  2433. fail_req_ring:
  2434. kfree(*req);
  2435. fail_req:
  2436. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2437. ha->ct_sns, ha->ct_sns_dma);
  2438. ha->ct_sns = NULL;
  2439. ha->ct_sns_dma = 0;
  2440. fail_free_ms_iocb:
  2441. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2442. ha->ms_iocb = NULL;
  2443. ha->ms_iocb_dma = 0;
  2444. fail_dma_pool:
  2445. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2446. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2447. ha->fcp_cmnd_dma_pool = NULL;
  2448. }
  2449. fail_dl_dma_pool:
  2450. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2451. dma_pool_destroy(ha->dl_dma_pool);
  2452. ha->dl_dma_pool = NULL;
  2453. }
  2454. fail_s_dma_pool:
  2455. dma_pool_destroy(ha->s_dma_pool);
  2456. ha->s_dma_pool = NULL;
  2457. fail_free_nvram:
  2458. kfree(ha->nvram);
  2459. ha->nvram = NULL;
  2460. fail_free_ctx_mempool:
  2461. mempool_destroy(ha->ctx_mempool);
  2462. ha->ctx_mempool = NULL;
  2463. fail_free_srb_mempool:
  2464. mempool_destroy(ha->srb_mempool);
  2465. ha->srb_mempool = NULL;
  2466. fail_free_gid_list:
  2467. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2468. ha->gid_list_dma);
  2469. ha->gid_list = NULL;
  2470. ha->gid_list_dma = 0;
  2471. fail_free_init_cb:
  2472. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2473. ha->init_cb_dma);
  2474. ha->init_cb = NULL;
  2475. ha->init_cb_dma = 0;
  2476. fail:
  2477. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2478. return -ENOMEM;
  2479. }
  2480. /*
  2481. * qla2x00_free_fw_dump
  2482. * Frees fw dump stuff.
  2483. *
  2484. * Input:
  2485. * ha = adapter block pointer.
  2486. */
  2487. static void
  2488. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  2489. {
  2490. if (ha->fce)
  2491. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2492. ha->fce_dma);
  2493. if (ha->fw_dump) {
  2494. if (ha->eft)
  2495. dma_free_coherent(&ha->pdev->dev,
  2496. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2497. vfree(ha->fw_dump);
  2498. }
  2499. ha->fce = NULL;
  2500. ha->fce_dma = 0;
  2501. ha->eft = NULL;
  2502. ha->eft_dma = 0;
  2503. ha->fw_dump = NULL;
  2504. ha->fw_dumped = 0;
  2505. ha->fw_dump_reading = 0;
  2506. }
  2507. /*
  2508. * qla2x00_mem_free
  2509. * Frees all adapter allocated memory.
  2510. *
  2511. * Input:
  2512. * ha = adapter block pointer.
  2513. */
  2514. static void
  2515. qla2x00_mem_free(struct qla_hw_data *ha)
  2516. {
  2517. qla2x00_free_fw_dump(ha);
  2518. if (ha->srb_mempool)
  2519. mempool_destroy(ha->srb_mempool);
  2520. if (ha->dcbx_tlv)
  2521. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2522. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2523. if (ha->xgmac_data)
  2524. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2525. ha->xgmac_data, ha->xgmac_data_dma);
  2526. if (ha->sns_cmd)
  2527. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2528. ha->sns_cmd, ha->sns_cmd_dma);
  2529. if (ha->ct_sns)
  2530. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2531. ha->ct_sns, ha->ct_sns_dma);
  2532. if (ha->sfp_data)
  2533. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2534. if (ha->edc_data)
  2535. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2536. if (ha->ms_iocb)
  2537. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2538. if (ha->ex_init_cb)
  2539. dma_pool_free(ha->s_dma_pool,
  2540. ha->ex_init_cb, ha->ex_init_cb_dma);
  2541. if (ha->async_pd)
  2542. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2543. if (ha->s_dma_pool)
  2544. dma_pool_destroy(ha->s_dma_pool);
  2545. if (ha->gid_list)
  2546. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2547. ha->gid_list_dma);
  2548. if (IS_QLA82XX(ha)) {
  2549. if (!list_empty(&ha->gbl_dsd_list)) {
  2550. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2551. /* clean up allocated prev pool */
  2552. list_for_each_entry_safe(dsd_ptr,
  2553. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2554. dma_pool_free(ha->dl_dma_pool,
  2555. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2556. list_del(&dsd_ptr->list);
  2557. kfree(dsd_ptr);
  2558. }
  2559. }
  2560. }
  2561. if (ha->dl_dma_pool)
  2562. dma_pool_destroy(ha->dl_dma_pool);
  2563. if (ha->fcp_cmnd_dma_pool)
  2564. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2565. if (ha->ctx_mempool)
  2566. mempool_destroy(ha->ctx_mempool);
  2567. if (ha->init_cb)
  2568. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2569. ha->init_cb, ha->init_cb_dma);
  2570. vfree(ha->optrom_buffer);
  2571. kfree(ha->nvram);
  2572. kfree(ha->npiv_info);
  2573. ha->srb_mempool = NULL;
  2574. ha->ctx_mempool = NULL;
  2575. ha->sns_cmd = NULL;
  2576. ha->sns_cmd_dma = 0;
  2577. ha->ct_sns = NULL;
  2578. ha->ct_sns_dma = 0;
  2579. ha->ms_iocb = NULL;
  2580. ha->ms_iocb_dma = 0;
  2581. ha->init_cb = NULL;
  2582. ha->init_cb_dma = 0;
  2583. ha->ex_init_cb = NULL;
  2584. ha->ex_init_cb_dma = 0;
  2585. ha->async_pd = NULL;
  2586. ha->async_pd_dma = 0;
  2587. ha->s_dma_pool = NULL;
  2588. ha->dl_dma_pool = NULL;
  2589. ha->fcp_cmnd_dma_pool = NULL;
  2590. ha->gid_list = NULL;
  2591. ha->gid_list_dma = 0;
  2592. }
  2593. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2594. struct qla_hw_data *ha)
  2595. {
  2596. struct Scsi_Host *host;
  2597. struct scsi_qla_host *vha = NULL;
  2598. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2599. if (host == NULL) {
  2600. printk(KERN_WARNING
  2601. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2602. goto fail;
  2603. }
  2604. /* Clear our data area */
  2605. vha = shost_priv(host);
  2606. memset(vha, 0, sizeof(scsi_qla_host_t));
  2607. vha->host = host;
  2608. vha->host_no = host->host_no;
  2609. vha->hw = ha;
  2610. INIT_LIST_HEAD(&vha->vp_fcports);
  2611. INIT_LIST_HEAD(&vha->work_list);
  2612. INIT_LIST_HEAD(&vha->list);
  2613. spin_lock_init(&vha->work_lock);
  2614. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2615. return vha;
  2616. fail:
  2617. return vha;
  2618. }
  2619. static struct qla_work_evt *
  2620. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2621. {
  2622. struct qla_work_evt *e;
  2623. uint8_t bail;
  2624. QLA_VHA_MARK_BUSY(vha, bail);
  2625. if (bail)
  2626. return NULL;
  2627. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2628. if (!e) {
  2629. QLA_VHA_MARK_NOT_BUSY(vha);
  2630. return NULL;
  2631. }
  2632. INIT_LIST_HEAD(&e->list);
  2633. e->type = type;
  2634. e->flags = QLA_EVT_FLAG_FREE;
  2635. return e;
  2636. }
  2637. static int
  2638. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2639. {
  2640. unsigned long flags;
  2641. spin_lock_irqsave(&vha->work_lock, flags);
  2642. list_add_tail(&e->list, &vha->work_list);
  2643. spin_unlock_irqrestore(&vha->work_lock, flags);
  2644. qla2xxx_wake_dpc(vha);
  2645. return QLA_SUCCESS;
  2646. }
  2647. int
  2648. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2649. u32 data)
  2650. {
  2651. struct qla_work_evt *e;
  2652. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2653. if (!e)
  2654. return QLA_FUNCTION_FAILED;
  2655. e->u.aen.code = code;
  2656. e->u.aen.data = data;
  2657. return qla2x00_post_work(vha, e);
  2658. }
  2659. int
  2660. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2661. {
  2662. struct qla_work_evt *e;
  2663. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2664. if (!e)
  2665. return QLA_FUNCTION_FAILED;
  2666. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2667. return qla2x00_post_work(vha, e);
  2668. }
  2669. #define qla2x00_post_async_work(name, type) \
  2670. int qla2x00_post_async_##name##_work( \
  2671. struct scsi_qla_host *vha, \
  2672. fc_port_t *fcport, uint16_t *data) \
  2673. { \
  2674. struct qla_work_evt *e; \
  2675. \
  2676. e = qla2x00_alloc_work(vha, type); \
  2677. if (!e) \
  2678. return QLA_FUNCTION_FAILED; \
  2679. \
  2680. e->u.logio.fcport = fcport; \
  2681. if (data) { \
  2682. e->u.logio.data[0] = data[0]; \
  2683. e->u.logio.data[1] = data[1]; \
  2684. } \
  2685. return qla2x00_post_work(vha, e); \
  2686. }
  2687. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2688. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2689. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2690. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2691. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2692. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2693. int
  2694. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2695. {
  2696. struct qla_work_evt *e;
  2697. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2698. if (!e)
  2699. return QLA_FUNCTION_FAILED;
  2700. e->u.uevent.code = code;
  2701. return qla2x00_post_work(vha, e);
  2702. }
  2703. static void
  2704. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2705. {
  2706. char event_string[40];
  2707. char *envp[] = { event_string, NULL };
  2708. switch (code) {
  2709. case QLA_UEVENT_CODE_FW_DUMP:
  2710. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2711. vha->host_no);
  2712. break;
  2713. default:
  2714. /* do nothing */
  2715. break;
  2716. }
  2717. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2718. }
  2719. void
  2720. qla2x00_do_work(struct scsi_qla_host *vha)
  2721. {
  2722. struct qla_work_evt *e, *tmp;
  2723. unsigned long flags;
  2724. LIST_HEAD(work);
  2725. spin_lock_irqsave(&vha->work_lock, flags);
  2726. list_splice_init(&vha->work_list, &work);
  2727. spin_unlock_irqrestore(&vha->work_lock, flags);
  2728. list_for_each_entry_safe(e, tmp, &work, list) {
  2729. list_del_init(&e->list);
  2730. switch (e->type) {
  2731. case QLA_EVT_AEN:
  2732. fc_host_post_event(vha->host, fc_get_event_number(),
  2733. e->u.aen.code, e->u.aen.data);
  2734. break;
  2735. case QLA_EVT_IDC_ACK:
  2736. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2737. break;
  2738. case QLA_EVT_ASYNC_LOGIN:
  2739. qla2x00_async_login(vha, e->u.logio.fcport,
  2740. e->u.logio.data);
  2741. break;
  2742. case QLA_EVT_ASYNC_LOGIN_DONE:
  2743. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2744. e->u.logio.data);
  2745. break;
  2746. case QLA_EVT_ASYNC_LOGOUT:
  2747. qla2x00_async_logout(vha, e->u.logio.fcport);
  2748. break;
  2749. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2750. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2751. e->u.logio.data);
  2752. break;
  2753. case QLA_EVT_ASYNC_ADISC:
  2754. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2755. e->u.logio.data);
  2756. break;
  2757. case QLA_EVT_ASYNC_ADISC_DONE:
  2758. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2759. e->u.logio.data);
  2760. break;
  2761. case QLA_EVT_UEVENT:
  2762. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2763. break;
  2764. }
  2765. if (e->flags & QLA_EVT_FLAG_FREE)
  2766. kfree(e);
  2767. /* For each work completed decrement vha ref count */
  2768. QLA_VHA_MARK_NOT_BUSY(vha);
  2769. }
  2770. }
  2771. /* Relogins all the fcports of a vport
  2772. * Context: dpc thread
  2773. */
  2774. void qla2x00_relogin(struct scsi_qla_host *vha)
  2775. {
  2776. fc_port_t *fcport;
  2777. int status;
  2778. uint16_t next_loopid = 0;
  2779. struct qla_hw_data *ha = vha->hw;
  2780. uint16_t data[2];
  2781. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2782. /*
  2783. * If the port is not ONLINE then try to login
  2784. * to it if we haven't run out of retries.
  2785. */
  2786. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2787. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2788. fcport->login_retry--;
  2789. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2790. if (fcport->flags & FCF_FCP2_DEVICE)
  2791. ha->isp_ops->fabric_logout(vha,
  2792. fcport->loop_id,
  2793. fcport->d_id.b.domain,
  2794. fcport->d_id.b.area,
  2795. fcport->d_id.b.al_pa);
  2796. if (IS_ALOGIO_CAPABLE(ha)) {
  2797. fcport->flags |= FCF_ASYNC_SENT;
  2798. data[0] = 0;
  2799. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2800. status = qla2x00_post_async_login_work(
  2801. vha, fcport, data);
  2802. if (status == QLA_SUCCESS)
  2803. continue;
  2804. /* Attempt a retry. */
  2805. status = 1;
  2806. } else
  2807. status = qla2x00_fabric_login(vha,
  2808. fcport, &next_loopid);
  2809. } else
  2810. status = qla2x00_local_device_login(vha,
  2811. fcport);
  2812. if (status == QLA_SUCCESS) {
  2813. fcport->old_loop_id = fcport->loop_id;
  2814. DEBUG(printk("scsi(%ld): port login OK: logged "
  2815. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2816. qla2x00_update_fcport(vha, fcport);
  2817. } else if (status == 1) {
  2818. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2819. /* retry the login again */
  2820. DEBUG(printk("scsi(%ld): Retrying"
  2821. " %d login again loop_id 0x%x\n",
  2822. vha->host_no, fcport->login_retry,
  2823. fcport->loop_id));
  2824. } else {
  2825. fcport->login_retry = 0;
  2826. }
  2827. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2828. fcport->loop_id = FC_NO_LOOP_ID;
  2829. }
  2830. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2831. break;
  2832. }
  2833. }
  2834. /**************************************************************************
  2835. * qla2x00_do_dpc
  2836. * This kernel thread is a task that is schedule by the interrupt handler
  2837. * to perform the background processing for interrupts.
  2838. *
  2839. * Notes:
  2840. * This task always run in the context of a kernel thread. It
  2841. * is kick-off by the driver's detect code and starts up
  2842. * up one per adapter. It immediately goes to sleep and waits for
  2843. * some fibre event. When either the interrupt handler or
  2844. * the timer routine detects a event it will one of the task
  2845. * bits then wake us up.
  2846. **************************************************************************/
  2847. static int
  2848. qla2x00_do_dpc(void *data)
  2849. {
  2850. int rval;
  2851. scsi_qla_host_t *base_vha;
  2852. struct qla_hw_data *ha;
  2853. ha = (struct qla_hw_data *)data;
  2854. base_vha = pci_get_drvdata(ha->pdev);
  2855. set_user_nice(current, -20);
  2856. while (!kthread_should_stop()) {
  2857. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2858. set_current_state(TASK_INTERRUPTIBLE);
  2859. schedule();
  2860. __set_current_state(TASK_RUNNING);
  2861. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2862. /* Initialization not yet finished. Don't do anything yet. */
  2863. if (!base_vha->flags.init_done)
  2864. continue;
  2865. if (ha->flags.eeh_busy) {
  2866. DEBUG17(qla_printk(KERN_WARNING, ha,
  2867. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2868. base_vha->dpc_flags));
  2869. continue;
  2870. }
  2871. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2872. ha->dpc_active = 1;
  2873. if (ha->flags.mbox_busy) {
  2874. ha->dpc_active = 0;
  2875. continue;
  2876. }
  2877. qla2x00_do_work(base_vha);
  2878. if (IS_QLA82XX(ha)) {
  2879. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2880. &base_vha->dpc_flags)) {
  2881. qla82xx_idc_lock(ha);
  2882. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2883. QLA82XX_DEV_FAILED);
  2884. qla82xx_idc_unlock(ha);
  2885. qla_printk(KERN_INFO, ha,
  2886. "HW State: FAILED\n");
  2887. qla82xx_device_state_handler(base_vha);
  2888. continue;
  2889. }
  2890. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2891. &base_vha->dpc_flags)) {
  2892. DEBUG(printk(KERN_INFO
  2893. "scsi(%ld): dpc: sched "
  2894. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2895. base_vha->host_no, ha));
  2896. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2897. &base_vha->dpc_flags))) {
  2898. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2899. /* FCoE-ctx reset failed.
  2900. * Escalate to chip-reset
  2901. */
  2902. set_bit(ISP_ABORT_NEEDED,
  2903. &base_vha->dpc_flags);
  2904. }
  2905. clear_bit(ABORT_ISP_ACTIVE,
  2906. &base_vha->dpc_flags);
  2907. }
  2908. DEBUG(printk("scsi(%ld): dpc:"
  2909. " qla82xx_fcoe_ctx_reset end\n",
  2910. base_vha->host_no));
  2911. }
  2912. }
  2913. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2914. &base_vha->dpc_flags)) {
  2915. DEBUG(printk("scsi(%ld): dpc: sched "
  2916. "qla2x00_abort_isp ha = %p\n",
  2917. base_vha->host_no, ha));
  2918. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2919. &base_vha->dpc_flags))) {
  2920. if (ha->isp_ops->abort_isp(base_vha)) {
  2921. /* failed. retry later */
  2922. set_bit(ISP_ABORT_NEEDED,
  2923. &base_vha->dpc_flags);
  2924. }
  2925. clear_bit(ABORT_ISP_ACTIVE,
  2926. &base_vha->dpc_flags);
  2927. }
  2928. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2929. base_vha->host_no));
  2930. }
  2931. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2932. qla2x00_update_fcports(base_vha);
  2933. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2934. }
  2935. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2936. &base_vha->dpc_flags) &&
  2937. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2938. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2939. base_vha->host_no));
  2940. qla2x00_rst_aen(base_vha);
  2941. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2942. }
  2943. /* Retry each device up to login retry count */
  2944. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2945. &base_vha->dpc_flags)) &&
  2946. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2947. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2948. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2949. base_vha->host_no));
  2950. qla2x00_relogin(base_vha);
  2951. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2952. base_vha->host_no));
  2953. }
  2954. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2955. &base_vha->dpc_flags)) {
  2956. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2957. base_vha->host_no));
  2958. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2959. &base_vha->dpc_flags))) {
  2960. rval = qla2x00_loop_resync(base_vha);
  2961. clear_bit(LOOP_RESYNC_ACTIVE,
  2962. &base_vha->dpc_flags);
  2963. }
  2964. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2965. base_vha->host_no));
  2966. }
  2967. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2968. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  2969. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  2970. qla2xxx_flash_npiv_conf(base_vha);
  2971. }
  2972. if (!ha->interrupts_on)
  2973. ha->isp_ops->enable_intrs(ha);
  2974. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  2975. &base_vha->dpc_flags))
  2976. ha->isp_ops->beacon_blink(base_vha);
  2977. qla2x00_do_dpc_all_vps(base_vha);
  2978. ha->dpc_active = 0;
  2979. } /* End of while(1) */
  2980. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  2981. /*
  2982. * Make sure that nobody tries to wake us up again.
  2983. */
  2984. ha->dpc_active = 0;
  2985. /* Cleanup any residual CTX SRBs. */
  2986. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2987. return 0;
  2988. }
  2989. void
  2990. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  2991. {
  2992. struct qla_hw_data *ha = vha->hw;
  2993. struct task_struct *t = ha->dpc_thread;
  2994. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  2995. wake_up_process(t);
  2996. }
  2997. /*
  2998. * qla2x00_rst_aen
  2999. * Processes asynchronous reset.
  3000. *
  3001. * Input:
  3002. * ha = adapter block pointer.
  3003. */
  3004. static void
  3005. qla2x00_rst_aen(scsi_qla_host_t *vha)
  3006. {
  3007. if (vha->flags.online && !vha->flags.reset_active &&
  3008. !atomic_read(&vha->loop_down_timer) &&
  3009. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  3010. do {
  3011. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3012. /*
  3013. * Issue marker command only when we are going to start
  3014. * the I/O.
  3015. */
  3016. vha->marker_needed = 1;
  3017. } while (!atomic_read(&vha->loop_down_timer) &&
  3018. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  3019. }
  3020. }
  3021. static void
  3022. qla2x00_sp_free_dma(srb_t *sp)
  3023. {
  3024. struct scsi_cmnd *cmd = sp->cmd;
  3025. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3026. if (sp->flags & SRB_DMA_VALID) {
  3027. scsi_dma_unmap(cmd);
  3028. sp->flags &= ~SRB_DMA_VALID;
  3029. }
  3030. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3031. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3032. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3033. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3034. }
  3035. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3036. /* List assured to be having elements */
  3037. qla2x00_clean_dsd_pool(ha, sp);
  3038. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3039. }
  3040. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3041. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3042. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3043. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3044. }
  3045. CMD_SP(cmd) = NULL;
  3046. }
  3047. static void
  3048. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3049. {
  3050. struct scsi_cmnd *cmd = sp->cmd;
  3051. qla2x00_sp_free_dma(sp);
  3052. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3053. struct ct6_dsd *ctx = sp->ctx;
  3054. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3055. ctx->fcp_cmnd_dma);
  3056. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3057. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3058. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3059. mempool_free(sp->ctx, ha->ctx_mempool);
  3060. sp->ctx = NULL;
  3061. }
  3062. mempool_free(sp, ha->srb_mempool);
  3063. cmd->scsi_done(cmd);
  3064. }
  3065. void
  3066. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3067. {
  3068. if (atomic_read(&sp->ref_count) == 0) {
  3069. DEBUG2(qla_printk(KERN_WARNING, ha,
  3070. "SP reference-count to ZERO -- sp=%p\n", sp));
  3071. DEBUG2(BUG());
  3072. return;
  3073. }
  3074. if (!atomic_dec_and_test(&sp->ref_count))
  3075. return;
  3076. qla2x00_sp_final_compl(ha, sp);
  3077. }
  3078. /**************************************************************************
  3079. * qla2x00_timer
  3080. *
  3081. * Description:
  3082. * One second timer
  3083. *
  3084. * Context: Interrupt
  3085. ***************************************************************************/
  3086. void
  3087. qla2x00_timer(scsi_qla_host_t *vha)
  3088. {
  3089. unsigned long cpu_flags = 0;
  3090. int start_dpc = 0;
  3091. int index;
  3092. srb_t *sp;
  3093. uint16_t w;
  3094. struct qla_hw_data *ha = vha->hw;
  3095. struct req_que *req;
  3096. if (ha->flags.eeh_busy) {
  3097. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3098. return;
  3099. }
  3100. if (IS_QLA82XX(ha))
  3101. qla82xx_watchdog(vha);
  3102. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3103. if (!pci_channel_offline(ha->pdev))
  3104. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3105. /* Loop down handler. */
  3106. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3107. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
  3108. && vha->flags.online) {
  3109. if (atomic_read(&vha->loop_down_timer) ==
  3110. vha->loop_down_abort_time) {
  3111. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3112. "queues before time expire\n",
  3113. vha->host_no));
  3114. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3115. atomic_set(&vha->loop_state, LOOP_DEAD);
  3116. /*
  3117. * Schedule an ISP abort to return any FCP2-device
  3118. * commands.
  3119. */
  3120. /* NPIV - scan physical port only */
  3121. if (!vha->vp_idx) {
  3122. spin_lock_irqsave(&ha->hardware_lock,
  3123. cpu_flags);
  3124. req = ha->req_q_map[0];
  3125. for (index = 1;
  3126. index < MAX_OUTSTANDING_COMMANDS;
  3127. index++) {
  3128. fc_port_t *sfcp;
  3129. sp = req->outstanding_cmds[index];
  3130. if (!sp)
  3131. continue;
  3132. if (sp->ctx && !IS_PROT_IO(sp))
  3133. continue;
  3134. sfcp = sp->fcport;
  3135. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3136. continue;
  3137. set_bit(ISP_ABORT_NEEDED,
  3138. &vha->dpc_flags);
  3139. break;
  3140. }
  3141. spin_unlock_irqrestore(&ha->hardware_lock,
  3142. cpu_flags);
  3143. }
  3144. start_dpc++;
  3145. }
  3146. /* if the loop has been down for 4 minutes, reinit adapter */
  3147. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3148. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3149. DEBUG(printk("scsi(%ld): Loop down - "
  3150. "aborting ISP.\n",
  3151. vha->host_no));
  3152. qla_printk(KERN_WARNING, ha,
  3153. "Loop down - aborting ISP.\n");
  3154. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3155. }
  3156. }
  3157. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3158. vha->host_no,
  3159. atomic_read(&vha->loop_down_timer)));
  3160. }
  3161. /* Check if beacon LED needs to be blinked */
  3162. if (ha->beacon_blink_led == 1) {
  3163. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3164. start_dpc++;
  3165. }
  3166. /* Process any deferred work. */
  3167. if (!list_empty(&vha->work_list))
  3168. start_dpc++;
  3169. /* Schedule the DPC routine if needed */
  3170. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3171. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3172. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3173. start_dpc ||
  3174. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3175. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3176. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3177. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3178. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3179. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3180. qla2xxx_wake_dpc(vha);
  3181. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3182. }
  3183. /* Firmware interface routines. */
  3184. #define FW_BLOBS 8
  3185. #define FW_ISP21XX 0
  3186. #define FW_ISP22XX 1
  3187. #define FW_ISP2300 2
  3188. #define FW_ISP2322 3
  3189. #define FW_ISP24XX 4
  3190. #define FW_ISP25XX 5
  3191. #define FW_ISP81XX 6
  3192. #define FW_ISP82XX 7
  3193. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3194. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3195. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3196. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3197. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3198. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3199. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3200. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3201. static DEFINE_MUTEX(qla_fw_lock);
  3202. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3203. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3204. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3205. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3206. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3207. { .name = FW_FILE_ISP24XX, },
  3208. { .name = FW_FILE_ISP25XX, },
  3209. { .name = FW_FILE_ISP81XX, },
  3210. { .name = FW_FILE_ISP82XX, },
  3211. };
  3212. struct fw_blob *
  3213. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3214. {
  3215. struct qla_hw_data *ha = vha->hw;
  3216. struct fw_blob *blob;
  3217. blob = NULL;
  3218. if (IS_QLA2100(ha)) {
  3219. blob = &qla_fw_blobs[FW_ISP21XX];
  3220. } else if (IS_QLA2200(ha)) {
  3221. blob = &qla_fw_blobs[FW_ISP22XX];
  3222. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3223. blob = &qla_fw_blobs[FW_ISP2300];
  3224. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3225. blob = &qla_fw_blobs[FW_ISP2322];
  3226. } else if (IS_QLA24XX_TYPE(ha)) {
  3227. blob = &qla_fw_blobs[FW_ISP24XX];
  3228. } else if (IS_QLA25XX(ha)) {
  3229. blob = &qla_fw_blobs[FW_ISP25XX];
  3230. } else if (IS_QLA81XX(ha)) {
  3231. blob = &qla_fw_blobs[FW_ISP81XX];
  3232. } else if (IS_QLA82XX(ha)) {
  3233. blob = &qla_fw_blobs[FW_ISP82XX];
  3234. }
  3235. mutex_lock(&qla_fw_lock);
  3236. if (blob->fw)
  3237. goto out;
  3238. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3239. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3240. "(%s).\n", vha->host_no, blob->name));
  3241. blob->fw = NULL;
  3242. blob = NULL;
  3243. goto out;
  3244. }
  3245. out:
  3246. mutex_unlock(&qla_fw_lock);
  3247. return blob;
  3248. }
  3249. static void
  3250. qla2x00_release_firmware(void)
  3251. {
  3252. int idx;
  3253. mutex_lock(&qla_fw_lock);
  3254. for (idx = 0; idx < FW_BLOBS; idx++)
  3255. if (qla_fw_blobs[idx].fw)
  3256. release_firmware(qla_fw_blobs[idx].fw);
  3257. mutex_unlock(&qla_fw_lock);
  3258. }
  3259. static pci_ers_result_t
  3260. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3261. {
  3262. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3263. struct qla_hw_data *ha = vha->hw;
  3264. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3265. state));
  3266. switch (state) {
  3267. case pci_channel_io_normal:
  3268. ha->flags.eeh_busy = 0;
  3269. return PCI_ERS_RESULT_CAN_RECOVER;
  3270. case pci_channel_io_frozen:
  3271. ha->flags.eeh_busy = 1;
  3272. /* For ISP82XX complete any pending mailbox cmd */
  3273. if (IS_QLA82XX(ha)) {
  3274. ha->flags.fw_hung = 1;
  3275. if (ha->flags.mbox_busy) {
  3276. ha->flags.mbox_int = 1;
  3277. DEBUG2(qla_printk(KERN_ERR, ha,
  3278. "Due to pci channel io frozen, doing premature "
  3279. "completion of mbx command\n"));
  3280. complete(&ha->mbx_intr_comp);
  3281. }
  3282. }
  3283. qla2x00_free_irqs(vha);
  3284. pci_disable_device(pdev);
  3285. /* Return back all IOs */
  3286. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3287. return PCI_ERS_RESULT_NEED_RESET;
  3288. case pci_channel_io_perm_failure:
  3289. ha->flags.pci_channel_io_perm_failure = 1;
  3290. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3291. return PCI_ERS_RESULT_DISCONNECT;
  3292. }
  3293. return PCI_ERS_RESULT_NEED_RESET;
  3294. }
  3295. static pci_ers_result_t
  3296. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3297. {
  3298. int risc_paused = 0;
  3299. uint32_t stat;
  3300. unsigned long flags;
  3301. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3302. struct qla_hw_data *ha = base_vha->hw;
  3303. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3304. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3305. if (IS_QLA82XX(ha))
  3306. return PCI_ERS_RESULT_RECOVERED;
  3307. spin_lock_irqsave(&ha->hardware_lock, flags);
  3308. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3309. stat = RD_REG_DWORD(&reg->hccr);
  3310. if (stat & HCCR_RISC_PAUSE)
  3311. risc_paused = 1;
  3312. } else if (IS_QLA23XX(ha)) {
  3313. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3314. if (stat & HSR_RISC_PAUSED)
  3315. risc_paused = 1;
  3316. } else if (IS_FWI2_CAPABLE(ha)) {
  3317. stat = RD_REG_DWORD(&reg24->host_status);
  3318. if (stat & HSRX_RISC_PAUSED)
  3319. risc_paused = 1;
  3320. }
  3321. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3322. if (risc_paused) {
  3323. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3324. "Dumping firmware!\n");
  3325. ha->isp_ops->fw_dump(base_vha, 0);
  3326. return PCI_ERS_RESULT_NEED_RESET;
  3327. } else
  3328. return PCI_ERS_RESULT_RECOVERED;
  3329. }
  3330. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3331. {
  3332. uint32_t rval = QLA_FUNCTION_FAILED;
  3333. uint32_t drv_active = 0;
  3334. struct qla_hw_data *ha = base_vha->hw;
  3335. int fn;
  3336. struct pci_dev *other_pdev = NULL;
  3337. DEBUG17(qla_printk(KERN_INFO, ha,
  3338. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3339. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3340. if (base_vha->flags.online) {
  3341. /* Abort all outstanding commands,
  3342. * so as to be requeued later */
  3343. qla2x00_abort_isp_cleanup(base_vha);
  3344. }
  3345. fn = PCI_FUNC(ha->pdev->devfn);
  3346. while (fn > 0) {
  3347. fn--;
  3348. DEBUG17(qla_printk(KERN_INFO, ha,
  3349. "Finding pci device at function = 0x%x\n", fn));
  3350. other_pdev =
  3351. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3352. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3353. fn));
  3354. if (!other_pdev)
  3355. continue;
  3356. if (atomic_read(&other_pdev->enable_cnt)) {
  3357. DEBUG17(qla_printk(KERN_INFO, ha,
  3358. "Found PCI func availabe and enabled at 0x%x\n",
  3359. fn));
  3360. pci_dev_put(other_pdev);
  3361. break;
  3362. }
  3363. pci_dev_put(other_pdev);
  3364. }
  3365. if (!fn) {
  3366. /* Reset owner */
  3367. DEBUG17(qla_printk(KERN_INFO, ha,
  3368. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3369. qla82xx_idc_lock(ha);
  3370. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3371. QLA82XX_DEV_INITIALIZING);
  3372. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3373. QLA82XX_IDC_VERSION);
  3374. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3375. DEBUG17(qla_printk(KERN_INFO, ha,
  3376. "drv_active = 0x%x\n", drv_active));
  3377. qla82xx_idc_unlock(ha);
  3378. /* Reset if device is not already reset
  3379. * drv_active would be 0 if a reset has already been done
  3380. */
  3381. if (drv_active)
  3382. rval = qla82xx_start_firmware(base_vha);
  3383. else
  3384. rval = QLA_SUCCESS;
  3385. qla82xx_idc_lock(ha);
  3386. if (rval != QLA_SUCCESS) {
  3387. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3388. qla82xx_clear_drv_active(ha);
  3389. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3390. QLA82XX_DEV_FAILED);
  3391. } else {
  3392. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3393. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3394. QLA82XX_DEV_READY);
  3395. qla82xx_idc_unlock(ha);
  3396. ha->flags.fw_hung = 0;
  3397. rval = qla82xx_restart_isp(base_vha);
  3398. qla82xx_idc_lock(ha);
  3399. /* Clear driver state register */
  3400. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3401. qla82xx_set_drv_active(base_vha);
  3402. }
  3403. qla82xx_idc_unlock(ha);
  3404. } else {
  3405. DEBUG17(qla_printk(KERN_INFO, ha,
  3406. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3407. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3408. QLA82XX_DEV_READY)) {
  3409. ha->flags.fw_hung = 0;
  3410. rval = qla82xx_restart_isp(base_vha);
  3411. qla82xx_idc_lock(ha);
  3412. qla82xx_set_drv_active(base_vha);
  3413. qla82xx_idc_unlock(ha);
  3414. }
  3415. }
  3416. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3417. return rval;
  3418. }
  3419. static pci_ers_result_t
  3420. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3421. {
  3422. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3423. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3424. struct qla_hw_data *ha = base_vha->hw;
  3425. struct rsp_que *rsp;
  3426. int rc, retries = 10;
  3427. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3428. /* Workaround: qla2xxx driver which access hardware earlier
  3429. * needs error state to be pci_channel_io_online.
  3430. * Otherwise mailbox command timesout.
  3431. */
  3432. pdev->error_state = pci_channel_io_normal;
  3433. pci_restore_state(pdev);
  3434. /* pci_restore_state() clears the saved_state flag of the device
  3435. * save restored state which resets saved_state flag
  3436. */
  3437. pci_save_state(pdev);
  3438. if (ha->mem_only)
  3439. rc = pci_enable_device_mem(pdev);
  3440. else
  3441. rc = pci_enable_device(pdev);
  3442. if (rc) {
  3443. qla_printk(KERN_WARNING, ha,
  3444. "Can't re-enable PCI device after reset.\n");
  3445. goto exit_slot_reset;
  3446. }
  3447. rsp = ha->rsp_q_map[0];
  3448. if (qla2x00_request_irqs(ha, rsp))
  3449. goto exit_slot_reset;
  3450. if (ha->isp_ops->pci_config(base_vha))
  3451. goto exit_slot_reset;
  3452. if (IS_QLA82XX(ha)) {
  3453. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3454. ret = PCI_ERS_RESULT_RECOVERED;
  3455. goto exit_slot_reset;
  3456. } else
  3457. goto exit_slot_reset;
  3458. }
  3459. while (ha->flags.mbox_busy && retries--)
  3460. msleep(1000);
  3461. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3462. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3463. ret = PCI_ERS_RESULT_RECOVERED;
  3464. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3465. exit_slot_reset:
  3466. DEBUG17(qla_printk(KERN_WARNING, ha,
  3467. "slot_reset-return:ret=%x\n", ret));
  3468. return ret;
  3469. }
  3470. static void
  3471. qla2xxx_pci_resume(struct pci_dev *pdev)
  3472. {
  3473. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3474. struct qla_hw_data *ha = base_vha->hw;
  3475. int ret;
  3476. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3477. ret = qla2x00_wait_for_hba_online(base_vha);
  3478. if (ret != QLA_SUCCESS) {
  3479. qla_printk(KERN_ERR, ha,
  3480. "the device failed to resume I/O "
  3481. "from slot/link_reset");
  3482. }
  3483. pci_cleanup_aer_uncorrect_error_status(pdev);
  3484. ha->flags.eeh_busy = 0;
  3485. }
  3486. static struct pci_error_handlers qla2xxx_err_handler = {
  3487. .error_detected = qla2xxx_pci_error_detected,
  3488. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3489. .slot_reset = qla2xxx_pci_slot_reset,
  3490. .resume = qla2xxx_pci_resume,
  3491. };
  3492. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3493. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3494. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3495. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3496. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3497. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3498. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3499. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3500. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3501. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3502. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3503. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3504. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3505. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3506. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3507. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3508. { 0 },
  3509. };
  3510. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3511. static struct pci_driver qla2xxx_pci_driver = {
  3512. .name = QLA2XXX_DRIVER_NAME,
  3513. .driver = {
  3514. .owner = THIS_MODULE,
  3515. },
  3516. .id_table = qla2xxx_pci_tbl,
  3517. .probe = qla2x00_probe_one,
  3518. .remove = qla2x00_remove_one,
  3519. .shutdown = qla2x00_shutdown,
  3520. .err_handler = &qla2xxx_err_handler,
  3521. };
  3522. static struct file_operations apidev_fops = {
  3523. .owner = THIS_MODULE,
  3524. .llseek = noop_llseek,
  3525. };
  3526. /**
  3527. * qla2x00_module_init - Module initialization.
  3528. **/
  3529. static int __init
  3530. qla2x00_module_init(void)
  3531. {
  3532. int ret = 0;
  3533. /* Allocate cache for SRBs. */
  3534. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3535. SLAB_HWCACHE_ALIGN, NULL);
  3536. if (srb_cachep == NULL) {
  3537. printk(KERN_ERR
  3538. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3539. return -ENOMEM;
  3540. }
  3541. /* Derive version string. */
  3542. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3543. if (ql2xextended_error_logging)
  3544. strcat(qla2x00_version_str, "-debug");
  3545. qla2xxx_transport_template =
  3546. fc_attach_transport(&qla2xxx_transport_functions);
  3547. if (!qla2xxx_transport_template) {
  3548. kmem_cache_destroy(srb_cachep);
  3549. return -ENODEV;
  3550. }
  3551. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3552. if (apidev_major < 0) {
  3553. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3554. "%s\n", QLA2XXX_APIDEV);
  3555. }
  3556. qla2xxx_transport_vport_template =
  3557. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3558. if (!qla2xxx_transport_vport_template) {
  3559. kmem_cache_destroy(srb_cachep);
  3560. fc_release_transport(qla2xxx_transport_template);
  3561. return -ENODEV;
  3562. }
  3563. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3564. qla2x00_version_str);
  3565. ret = pci_register_driver(&qla2xxx_pci_driver);
  3566. if (ret) {
  3567. kmem_cache_destroy(srb_cachep);
  3568. fc_release_transport(qla2xxx_transport_template);
  3569. fc_release_transport(qla2xxx_transport_vport_template);
  3570. }
  3571. return ret;
  3572. }
  3573. /**
  3574. * qla2x00_module_exit - Module cleanup.
  3575. **/
  3576. static void __exit
  3577. qla2x00_module_exit(void)
  3578. {
  3579. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3580. pci_unregister_driver(&qla2xxx_pci_driver);
  3581. qla2x00_release_firmware();
  3582. kmem_cache_destroy(srb_cachep);
  3583. if (ctx_cachep)
  3584. kmem_cache_destroy(ctx_cachep);
  3585. fc_release_transport(qla2xxx_transport_template);
  3586. fc_release_transport(qla2xxx_transport_vport_template);
  3587. }
  3588. module_init(qla2x00_module_init);
  3589. module_exit(qla2x00_module_exit);
  3590. MODULE_AUTHOR("QLogic Corporation");
  3591. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3592. MODULE_LICENSE("GPL");
  3593. MODULE_VERSION(QLA2XXX_VERSION);
  3594. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3595. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3596. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3597. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3598. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3599. MODULE_FIRMWARE(FW_FILE_ISP25XX);