ath9k.h 21 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef ATH9K_H
  17. #define ATH9K_H
  18. #include <linux/etherdevice.h>
  19. #include <linux/device.h>
  20. #include <linux/leds.h>
  21. #include <linux/completion.h>
  22. #include <linux/pm_qos_params.h>
  23. #include "debug.h"
  24. #include "common.h"
  25. /*
  26. * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  27. * should rely on this file or its contents.
  28. */
  29. struct ath_node;
  30. /* Macro to expand scalars to 64-bit objects */
  31. #define ito64(x) (sizeof(x) == 1) ? \
  32. (((unsigned long long int)(x)) & (0xff)) : \
  33. (sizeof(x) == 2) ? \
  34. (((unsigned long long int)(x)) & 0xffff) : \
  35. ((sizeof(x) == 4) ? \
  36. (((unsigned long long int)(x)) & 0xffffffff) : \
  37. (unsigned long long int)(x))
  38. /* increment with wrap-around */
  39. #define INCR(_l, _sz) do { \
  40. (_l)++; \
  41. (_l) &= ((_sz) - 1); \
  42. } while (0)
  43. /* decrement with wrap-around */
  44. #define DECR(_l, _sz) do { \
  45. (_l)--; \
  46. (_l) &= ((_sz) - 1); \
  47. } while (0)
  48. #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  49. #define TSF_TO_TU(_h,_l) \
  50. ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  51. #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
  52. struct ath_config {
  53. u32 ath_aggr_prot;
  54. u16 txpowlimit;
  55. u8 cabqReadytime;
  56. };
  57. /*************************/
  58. /* Descriptor Management */
  59. /*************************/
  60. #define ATH_TXBUF_RESET(_bf) do { \
  61. (_bf)->bf_stale = false; \
  62. (_bf)->bf_lastbf = NULL; \
  63. (_bf)->bf_next = NULL; \
  64. memset(&((_bf)->bf_state), 0, \
  65. sizeof(struct ath_buf_state)); \
  66. } while (0)
  67. #define ATH_RXBUF_RESET(_bf) do { \
  68. (_bf)->bf_stale = false; \
  69. } while (0)
  70. /**
  71. * enum buffer_type - Buffer type flags
  72. *
  73. * @BUF_HT: Send this buffer using HT capabilities
  74. * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  75. * @BUF_AGGR: Indicates whether the buffer can be aggregated
  76. * (used in aggregation scheduling)
  77. * @BUF_RETRY: Indicates whether the buffer is retried
  78. * @BUF_XRETRY: To denote excessive retries of the buffer
  79. */
  80. enum buffer_type {
  81. BUF_HT = BIT(1),
  82. BUF_AMPDU = BIT(2),
  83. BUF_AGGR = BIT(3),
  84. BUF_RETRY = BIT(4),
  85. BUF_XRETRY = BIT(5),
  86. };
  87. #define bf_nframes bf_state.bfs_nframes
  88. #define bf_al bf_state.bfs_al
  89. #define bf_frmlen bf_state.bfs_frmlen
  90. #define bf_retries bf_state.bfs_retries
  91. #define bf_seqno bf_state.bfs_seqno
  92. #define bf_tidno bf_state.bfs_tidno
  93. #define bf_keyix bf_state.bfs_keyix
  94. #define bf_keytype bf_state.bfs_keytype
  95. #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
  96. #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
  97. #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
  98. #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
  99. #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
  100. #define ATH_TXSTATUS_RING_SIZE 64
  101. struct ath_descdma {
  102. void *dd_desc;
  103. dma_addr_t dd_desc_paddr;
  104. u32 dd_desc_len;
  105. struct ath_buf *dd_bufptr;
  106. };
  107. int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
  108. struct list_head *head, const char *name,
  109. int nbuf, int ndesc, bool is_tx);
  110. void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
  111. struct list_head *head);
  112. /***********/
  113. /* RX / TX */
  114. /***********/
  115. #define ATH_MAX_ANTENNA 3
  116. #define ATH_RXBUF 512
  117. #define ATH_TXBUF 512
  118. #define ATH_TXBUF_RESERVE 5
  119. #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
  120. #define ATH_TXMAXTRY 13
  121. #define ATH_MGT_TXMAXTRY 4
  122. #define TID_TO_WME_AC(_tid) \
  123. ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
  124. (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
  125. (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
  126. WME_AC_VO)
  127. #define ADDBA_EXCHANGE_ATTEMPTS 10
  128. #define ATH_AGGR_DELIM_SZ 4
  129. #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
  130. /* number of delimiters for encryption padding */
  131. #define ATH_AGGR_ENCRYPTDELIM 10
  132. /* minimum h/w qdepth to be sustained to maximize aggregation */
  133. #define ATH_AGGR_MIN_QDEPTH 2
  134. #define ATH_AMPDU_SUBFRAME_DEFAULT 32
  135. #define IEEE80211_SEQ_SEQ_SHIFT 4
  136. #define IEEE80211_SEQ_MAX 4096
  137. #define IEEE80211_WEP_IVLEN 3
  138. #define IEEE80211_WEP_KIDLEN 1
  139. #define IEEE80211_WEP_CRCLEN 4
  140. #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
  141. (IEEE80211_WEP_IVLEN + \
  142. IEEE80211_WEP_KIDLEN + \
  143. IEEE80211_WEP_CRCLEN))
  144. /* return whether a bit at index _n in bitmap _bm is set
  145. * _sz is the size of the bitmap */
  146. #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
  147. ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
  148. /* return block-ack bitmap index given sequence and starting sequence */
  149. #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
  150. /* returns delimiter padding required given the packet length */
  151. #define ATH_AGGR_GET_NDELIM(_len) \
  152. (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
  153. (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
  154. #define BAW_WITHIN(_start, _bawsz, _seqno) \
  155. ((((_seqno) - (_start)) & 4095) < (_bawsz))
  156. #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
  157. #define ATH_TX_COMPLETE_POLL_INT 1000
  158. enum ATH_AGGR_STATUS {
  159. ATH_AGGR_DONE,
  160. ATH_AGGR_BAW_CLOSED,
  161. ATH_AGGR_LIMITED,
  162. };
  163. #define ATH_TXFIFO_DEPTH 8
  164. struct ath_txq {
  165. int axq_class;
  166. u32 axq_qnum;
  167. u32 *axq_link;
  168. struct list_head axq_q;
  169. spinlock_t axq_lock;
  170. u32 axq_depth;
  171. bool stopped;
  172. bool axq_tx_inprogress;
  173. struct list_head axq_acq;
  174. struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
  175. struct list_head txq_fifo_pending;
  176. u8 txq_headidx;
  177. u8 txq_tailidx;
  178. };
  179. struct ath_atx_ac {
  180. int sched;
  181. int qnum;
  182. struct list_head list;
  183. struct list_head tid_q;
  184. };
  185. struct ath_buf_state {
  186. int bfs_nframes;
  187. u16 bfs_al;
  188. u16 bfs_frmlen;
  189. int bfs_seqno;
  190. int bfs_tidno;
  191. int bfs_retries;
  192. u8 bf_type;
  193. u8 bfs_paprd;
  194. unsigned long bfs_paprd_timestamp;
  195. u32 bfs_keyix;
  196. enum ath9k_key_type bfs_keytype;
  197. };
  198. struct ath_buf {
  199. struct list_head list;
  200. struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
  201. an aggregate) */
  202. struct ath_buf *bf_next; /* next subframe in the aggregate */
  203. struct sk_buff *bf_mpdu; /* enclosing frame structure */
  204. void *bf_desc; /* virtual addr of desc */
  205. dma_addr_t bf_daddr; /* physical addr of desc */
  206. dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
  207. bool bf_stale;
  208. bool bf_tx_aborted;
  209. u16 bf_flags;
  210. struct ath_buf_state bf_state;
  211. struct ath_wiphy *aphy;
  212. };
  213. struct ath_atx_tid {
  214. struct list_head list;
  215. struct list_head buf_q;
  216. struct ath_node *an;
  217. struct ath_atx_ac *ac;
  218. unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
  219. u16 seq_start;
  220. u16 seq_next;
  221. u16 baw_size;
  222. int tidno;
  223. int baw_head; /* first un-acked tx buffer */
  224. int baw_tail; /* next unused tx buffer slot */
  225. int sched;
  226. int paused;
  227. u8 state;
  228. };
  229. struct ath_node {
  230. struct ath_common *common;
  231. struct ath_atx_tid tid[WME_NUM_TID];
  232. struct ath_atx_ac ac[WME_NUM_AC];
  233. u16 maxampdu;
  234. u8 mpdudensity;
  235. int last_rssi;
  236. };
  237. #define AGGR_CLEANUP BIT(1)
  238. #define AGGR_ADDBA_COMPLETE BIT(2)
  239. #define AGGR_ADDBA_PROGRESS BIT(3)
  240. struct ath_tx_control {
  241. struct ath_txq *txq;
  242. int if_id;
  243. enum ath9k_internal_frame_type frame_type;
  244. u8 paprd;
  245. };
  246. #define ATH_TX_ERROR 0x01
  247. #define ATH_TX_XRETRY 0x02
  248. #define ATH_TX_BAR 0x04
  249. struct ath_tx {
  250. u16 seq_no;
  251. u32 txqsetup;
  252. int hwq_map[WME_NUM_AC];
  253. spinlock_t txbuflock;
  254. struct list_head txbuf;
  255. struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
  256. struct ath_descdma txdma;
  257. int pending_frames[WME_NUM_AC];
  258. };
  259. struct ath_rx_edma {
  260. struct sk_buff_head rx_fifo;
  261. struct sk_buff_head rx_buffers;
  262. u32 rx_fifo_hwsize;
  263. };
  264. struct ath_rx {
  265. u8 defant;
  266. u8 rxotherant;
  267. u32 *rxlink;
  268. unsigned int rxfilter;
  269. spinlock_t pcu_lock;
  270. spinlock_t rxbuflock;
  271. struct list_head rxbuf;
  272. struct ath_descdma rxdma;
  273. struct ath_buf *rx_bufptr;
  274. struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
  275. };
  276. int ath_startrecv(struct ath_softc *sc);
  277. bool ath_stoprecv(struct ath_softc *sc);
  278. void ath_flushrecv(struct ath_softc *sc);
  279. u32 ath_calcrxfilter(struct ath_softc *sc);
  280. int ath_rx_init(struct ath_softc *sc, int nbufs);
  281. void ath_rx_cleanup(struct ath_softc *sc);
  282. int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
  283. struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
  284. void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
  285. int ath_tx_setup(struct ath_softc *sc, int haltype);
  286. bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
  287. void ath_draintxq(struct ath_softc *sc,
  288. struct ath_txq *txq, bool retry_tx);
  289. void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
  290. void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
  291. void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
  292. int ath_tx_init(struct ath_softc *sc, int nbufs);
  293. void ath_tx_cleanup(struct ath_softc *sc);
  294. int ath_txq_update(struct ath_softc *sc, int qnum,
  295. struct ath9k_tx_queue_info *q);
  296. int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
  297. struct ath_tx_control *txctl);
  298. void ath_tx_tasklet(struct ath_softc *sc);
  299. void ath_tx_edma_tasklet(struct ath_softc *sc);
  300. void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
  301. int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
  302. u16 tid, u16 *ssn);
  303. void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
  304. void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
  305. /********/
  306. /* VIFs */
  307. /********/
  308. struct ath_vif {
  309. int av_bslot;
  310. __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
  311. enum nl80211_iftype av_opmode;
  312. struct ath_buf *av_bcbuf;
  313. struct ath_tx_control av_btxctl;
  314. u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
  315. };
  316. /*******************/
  317. /* Beacon Handling */
  318. /*******************/
  319. /*
  320. * Regardless of the number of beacons we stagger, (i.e. regardless of the
  321. * number of BSSIDs) if a given beacon does not go out even after waiting this
  322. * number of beacon intervals, the game's up.
  323. */
  324. #define BSTUCK_THRESH (9 * ATH_BCBUF)
  325. #define ATH_BCBUF 4
  326. #define ATH_DEFAULT_BINTVAL 100 /* TU */
  327. #define ATH_DEFAULT_BMISS_LIMIT 10
  328. #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
  329. struct ath_beacon_config {
  330. u16 beacon_interval;
  331. u16 listen_interval;
  332. u16 dtim_period;
  333. u16 bmiss_timeout;
  334. u8 dtim_count;
  335. };
  336. struct ath_beacon {
  337. enum {
  338. OK, /* no change needed */
  339. UPDATE, /* update pending */
  340. COMMIT /* beacon sent, commit change */
  341. } updateslot; /* slot time update fsm */
  342. u32 beaconq;
  343. u32 bmisscnt;
  344. u32 ast_be_xmit;
  345. u64 bc_tstamp;
  346. struct ieee80211_vif *bslot[ATH_BCBUF];
  347. struct ath_wiphy *bslot_aphy[ATH_BCBUF];
  348. int slottime;
  349. int slotupdate;
  350. struct ath9k_tx_queue_info beacon_qi;
  351. struct ath_descdma bdma;
  352. struct ath_txq *cabq;
  353. struct list_head bbuf;
  354. };
  355. void ath_beacon_tasklet(unsigned long data);
  356. void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
  357. int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
  358. void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
  359. int ath_beaconq_config(struct ath_softc *sc);
  360. /*******/
  361. /* ANI */
  362. /*******/
  363. #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
  364. #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
  365. #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
  366. #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
  367. #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
  368. #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
  369. #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
  370. #define ATH_PAPRD_TIMEOUT 100 /* msecs */
  371. void ath_hw_check(struct work_struct *work);
  372. void ath_paprd_calibrate(struct work_struct *work);
  373. void ath_ani_calibrate(unsigned long data);
  374. /**********/
  375. /* BTCOEX */
  376. /**********/
  377. struct ath_btcoex {
  378. bool hw_timer_enabled;
  379. spinlock_t btcoex_lock;
  380. struct timer_list period_timer; /* Timer for BT period */
  381. u32 bt_priority_cnt;
  382. unsigned long bt_priority_time;
  383. int bt_stomp_type; /* Types of BT stomping */
  384. u32 btcoex_no_stomp; /* in usec */
  385. u32 btcoex_period; /* in usec */
  386. u32 btscan_no_stomp; /* in usec */
  387. struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
  388. };
  389. int ath_init_btcoex_timer(struct ath_softc *sc);
  390. void ath9k_btcoex_timer_resume(struct ath_softc *sc);
  391. void ath9k_btcoex_timer_pause(struct ath_softc *sc);
  392. /********************/
  393. /* LED Control */
  394. /********************/
  395. #define ATH_LED_PIN_DEF 1
  396. #define ATH_LED_PIN_9287 8
  397. #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
  398. #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
  399. enum ath_led_type {
  400. ATH_LED_RADIO,
  401. ATH_LED_ASSOC,
  402. ATH_LED_TX,
  403. ATH_LED_RX
  404. };
  405. struct ath_led {
  406. struct ath_softc *sc;
  407. struct led_classdev led_cdev;
  408. enum ath_led_type led_type;
  409. char name[32];
  410. bool registered;
  411. };
  412. void ath_init_leds(struct ath_softc *sc);
  413. void ath_deinit_leds(struct ath_softc *sc);
  414. /* Antenna diversity/combining */
  415. #define ATH_ANT_RX_CURRENT_SHIFT 4
  416. #define ATH_ANT_RX_MAIN_SHIFT 2
  417. #define ATH_ANT_RX_MASK 0x3
  418. #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
  419. #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
  420. #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
  421. #define ATH_ANT_DIV_COMB_INIT_COUNT 95
  422. #define ATH_ANT_DIV_COMB_MAX_COUNT 100
  423. #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
  424. #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
  425. #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
  426. #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
  427. #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
  428. #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
  429. #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
  430. enum ath9k_ant_div_comb_lna_conf {
  431. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
  432. ATH_ANT_DIV_COMB_LNA2,
  433. ATH_ANT_DIV_COMB_LNA1,
  434. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
  435. };
  436. struct ath_ant_comb {
  437. u16 count;
  438. u16 total_pkt_count;
  439. bool scan;
  440. bool scan_not_start;
  441. int main_total_rssi;
  442. int alt_total_rssi;
  443. int alt_recv_cnt;
  444. int main_recv_cnt;
  445. int rssi_lna1;
  446. int rssi_lna2;
  447. int rssi_add;
  448. int rssi_sub;
  449. int rssi_first;
  450. int rssi_second;
  451. int rssi_third;
  452. bool alt_good;
  453. int quick_scan_cnt;
  454. int main_conf;
  455. enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
  456. enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
  457. int first_bias;
  458. int second_bias;
  459. bool first_ratio;
  460. bool second_ratio;
  461. unsigned long scan_start_time;
  462. };
  463. /********************/
  464. /* Main driver core */
  465. /********************/
  466. /*
  467. * Default cache line size, in bytes.
  468. * Used when PCI device not fully initialized by bootrom/BIOS
  469. */
  470. #define DEFAULT_CACHELINE 32
  471. #define ATH_REGCLASSIDS_MAX 10
  472. #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
  473. #define ATH_MAX_SW_RETRIES 10
  474. #define ATH_CHAN_MAX 255
  475. #define IEEE80211_WEP_NKID 4 /* number of key ids */
  476. #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
  477. #define ATH_RATE_DUMMY_MARKER 0
  478. #define SC_OP_INVALID BIT(0)
  479. #define SC_OP_BEACONS BIT(1)
  480. #define SC_OP_RXAGGR BIT(2)
  481. #define SC_OP_TXAGGR BIT(3)
  482. #define SC_OP_OFFCHANNEL BIT(4)
  483. #define SC_OP_PREAMBLE_SHORT BIT(5)
  484. #define SC_OP_PROTECT_ENABLE BIT(6)
  485. #define SC_OP_RXFLUSH BIT(7)
  486. #define SC_OP_LED_ASSOCIATED BIT(8)
  487. #define SC_OP_LED_ON BIT(9)
  488. #define SC_OP_TSF_RESET BIT(11)
  489. #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
  490. #define SC_OP_BT_SCAN BIT(13)
  491. #define SC_OP_ANI_RUN BIT(14)
  492. /* Powersave flags */
  493. #define PS_WAIT_FOR_BEACON BIT(0)
  494. #define PS_WAIT_FOR_CAB BIT(1)
  495. #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
  496. #define PS_WAIT_FOR_TX_ACK BIT(3)
  497. #define PS_BEACON_SYNC BIT(4)
  498. struct ath_wiphy;
  499. struct ath_rate_table;
  500. struct ath_softc {
  501. struct ieee80211_hw *hw;
  502. struct device *dev;
  503. spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
  504. struct ath_wiphy *pri_wiphy;
  505. struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
  506. * have NULL entries */
  507. int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
  508. int chan_idx;
  509. int chan_is_ht;
  510. struct ath_wiphy *next_wiphy;
  511. struct work_struct chan_work;
  512. int wiphy_select_failures;
  513. unsigned long wiphy_select_first_fail;
  514. struct delayed_work wiphy_work;
  515. unsigned long wiphy_scheduler_int;
  516. int wiphy_scheduler_index;
  517. struct survey_info *cur_survey;
  518. struct survey_info survey[ATH9K_NUM_CHANNELS];
  519. struct tasklet_struct intr_tq;
  520. struct tasklet_struct bcon_tasklet;
  521. struct ath_hw *sc_ah;
  522. void __iomem *mem;
  523. int irq;
  524. spinlock_t sc_resetlock;
  525. spinlock_t sc_serial_rw;
  526. spinlock_t sc_pm_lock;
  527. struct mutex mutex;
  528. struct work_struct paprd_work;
  529. struct work_struct hw_check_work;
  530. struct completion paprd_complete;
  531. u32 intrstatus;
  532. u32 sc_flags; /* SC_OP_* */
  533. u16 ps_flags; /* PS_* */
  534. u16 curtxpow;
  535. u8 nbcnvifs;
  536. u16 nvifs;
  537. bool ps_enabled;
  538. bool ps_idle;
  539. unsigned long ps_usecount;
  540. struct ath_config config;
  541. struct ath_rx rx;
  542. struct ath_tx tx;
  543. struct ath_beacon beacon;
  544. struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
  545. struct ath_led radio_led;
  546. struct ath_led assoc_led;
  547. struct ath_led tx_led;
  548. struct ath_led rx_led;
  549. struct delayed_work ath_led_blink_work;
  550. int led_on_duration;
  551. int led_off_duration;
  552. int led_on_cnt;
  553. int led_off_cnt;
  554. int beacon_interval;
  555. #ifdef CONFIG_ATH9K_DEBUGFS
  556. struct ath9k_debug debug;
  557. #endif
  558. struct ath_beacon_config cur_beacon_conf;
  559. struct delayed_work tx_complete_work;
  560. struct ath_btcoex btcoex;
  561. struct ath_descdma txsdma;
  562. struct ath_ant_comb ant_comb;
  563. struct pm_qos_request_list pm_qos_req;
  564. };
  565. struct ath_wiphy {
  566. struct ath_softc *sc; /* shared for all virtual wiphys */
  567. struct ieee80211_hw *hw;
  568. struct ath9k_hw_cal_data caldata;
  569. enum ath_wiphy_state {
  570. ATH_WIPHY_INACTIVE,
  571. ATH_WIPHY_ACTIVE,
  572. ATH_WIPHY_PAUSING,
  573. ATH_WIPHY_PAUSED,
  574. ATH_WIPHY_SCAN,
  575. } state;
  576. bool idle;
  577. int chan_idx;
  578. int chan_is_ht;
  579. };
  580. void ath9k_tasklet(unsigned long data);
  581. int ath_reset(struct ath_softc *sc, bool retry_tx);
  582. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
  583. int ath_cabq_update(struct ath_softc *);
  584. static inline void ath_read_cachesize(struct ath_common *common, int *csz)
  585. {
  586. common->bus_ops->read_cachesize(common, csz);
  587. }
  588. extern struct ieee80211_ops ath9k_ops;
  589. extern int modparam_nohwcrypt;
  590. extern int led_blink;
  591. irqreturn_t ath_isr(int irq, void *dev);
  592. int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
  593. const struct ath_bus_ops *bus_ops);
  594. void ath9k_deinit_device(struct ath_softc *sc);
  595. void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
  596. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  597. struct ath9k_channel *ichan);
  598. void ath_update_chainmask(struct ath_softc *sc, int is_ht);
  599. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  600. struct ath9k_channel *hchan);
  601. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
  602. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
  603. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
  604. #ifdef CONFIG_PCI
  605. int ath_pci_init(void);
  606. void ath_pci_exit(void);
  607. #else
  608. static inline int ath_pci_init(void) { return 0; };
  609. static inline void ath_pci_exit(void) {};
  610. #endif
  611. #ifdef CONFIG_ATHEROS_AR71XX
  612. int ath_ahb_init(void);
  613. void ath_ahb_exit(void);
  614. #else
  615. static inline int ath_ahb_init(void) { return 0; };
  616. static inline void ath_ahb_exit(void) {};
  617. #endif
  618. void ath9k_ps_wakeup(struct ath_softc *sc);
  619. void ath9k_ps_restore(struct ath_softc *sc);
  620. void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
  621. int ath9k_wiphy_add(struct ath_softc *sc);
  622. int ath9k_wiphy_del(struct ath_wiphy *aphy);
  623. void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
  624. int ath9k_wiphy_pause(struct ath_wiphy *aphy);
  625. int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
  626. int ath9k_wiphy_select(struct ath_wiphy *aphy);
  627. void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
  628. void ath9k_wiphy_chan_work(struct work_struct *work);
  629. bool ath9k_wiphy_started(struct ath_softc *sc);
  630. void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
  631. struct ath_wiphy *selected);
  632. bool ath9k_wiphy_scanning(struct ath_softc *sc);
  633. void ath9k_wiphy_work(struct work_struct *work);
  634. bool ath9k_all_wiphys_idle(struct ath_softc *sc);
  635. void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
  636. void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
  637. bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
  638. void ath_start_rfkill_poll(struct ath_softc *sc);
  639. extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
  640. #endif /* ATH9K_H */