sdhci-pci.c 23 KB

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  1. /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
  2. *
  3. * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or (at
  8. * your option) any later version.
  9. *
  10. * Thanks to the following companies for their support:
  11. *
  12. * - JMicron (hardware and technical support)
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/highmem.h>
  16. #include <linux/pci.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/slab.h>
  19. #include <linux/device.h>
  20. #include <linux/mmc/host.h>
  21. #include <asm/scatterlist.h>
  22. #include <asm/io.h>
  23. #include "sdhci.h"
  24. /*
  25. * PCI registers
  26. */
  27. #define PCI_SDHCI_IFPIO 0x00
  28. #define PCI_SDHCI_IFDMA 0x01
  29. #define PCI_SDHCI_IFVENDOR 0x02
  30. #define PCI_SLOT_INFO 0x40 /* 8 bits */
  31. #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
  32. #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
  33. #define MAX_SLOTS 8
  34. struct sdhci_pci_chip;
  35. struct sdhci_pci_slot;
  36. struct sdhci_pci_fixes {
  37. unsigned int quirks;
  38. int (*probe)(struct sdhci_pci_chip*);
  39. int (*probe_slot)(struct sdhci_pci_slot*);
  40. void (*remove_slot)(struct sdhci_pci_slot*, int);
  41. int (*suspend)(struct sdhci_pci_chip*,
  42. pm_message_t);
  43. int (*resume)(struct sdhci_pci_chip*);
  44. };
  45. struct sdhci_pci_slot {
  46. struct sdhci_pci_chip *chip;
  47. struct sdhci_host *host;
  48. int pci_bar;
  49. };
  50. struct sdhci_pci_chip {
  51. struct pci_dev *pdev;
  52. unsigned int quirks;
  53. const struct sdhci_pci_fixes *fixes;
  54. int num_slots; /* Slots on controller */
  55. struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
  56. };
  57. /*****************************************************************************\
  58. * *
  59. * Hardware specific quirk handling *
  60. * *
  61. \*****************************************************************************/
  62. static int ricoh_probe(struct sdhci_pci_chip *chip)
  63. {
  64. if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
  65. chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
  66. chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
  67. return 0;
  68. }
  69. static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
  70. {
  71. slot->host->caps =
  72. ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
  73. & SDHCI_TIMEOUT_CLK_MASK) |
  74. ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
  75. & SDHCI_CLOCK_BASE_MASK) |
  76. SDHCI_TIMEOUT_CLK_UNIT |
  77. SDHCI_CAN_VDD_330 |
  78. SDHCI_CAN_DO_SDMA;
  79. return 0;
  80. }
  81. static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
  82. {
  83. /* Apply a delay to allow controller to settle */
  84. /* Otherwise it becomes confused if card state changed
  85. during suspend */
  86. msleep(500);
  87. return 0;
  88. }
  89. static const struct sdhci_pci_fixes sdhci_ricoh = {
  90. .probe = ricoh_probe,
  91. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
  92. SDHCI_QUIRK_FORCE_DMA |
  93. SDHCI_QUIRK_CLOCK_BEFORE_RESET,
  94. };
  95. static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
  96. .probe_slot = ricoh_mmc_probe_slot,
  97. .resume = ricoh_mmc_resume,
  98. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
  99. SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  100. SDHCI_QUIRK_NO_CARD_NO_RESET |
  101. SDHCI_QUIRK_MISSING_CAPS
  102. };
  103. static const struct sdhci_pci_fixes sdhci_ene_712 = {
  104. .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  105. SDHCI_QUIRK_BROKEN_DMA,
  106. };
  107. static const struct sdhci_pci_fixes sdhci_ene_714 = {
  108. .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  109. SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
  110. SDHCI_QUIRK_BROKEN_DMA,
  111. };
  112. static const struct sdhci_pci_fixes sdhci_cafe = {
  113. .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
  114. SDHCI_QUIRK_NO_BUSY_IRQ |
  115. SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
  116. };
  117. /*
  118. * ADMA operation is disabled for Moorestown platform due to
  119. * hardware bugs.
  120. */
  121. static int mrst_hc_probe(struct sdhci_pci_chip *chip)
  122. {
  123. /*
  124. * slots number is fixed here for MRST as SDIO3/5 are never used and
  125. * have hardware bugs.
  126. */
  127. chip->num_slots = 1;
  128. return 0;
  129. }
  130. static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
  131. .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
  132. };
  133. static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
  134. .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
  135. .probe = mrst_hc_probe,
  136. };
  137. static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
  138. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  139. };
  140. static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = {
  141. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  142. };
  143. static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
  144. {
  145. u8 scratch;
  146. int ret;
  147. ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
  148. if (ret)
  149. return ret;
  150. /*
  151. * Turn PMOS on [bit 0], set over current detection to 2.4 V
  152. * [bit 1:2] and enable over current debouncing [bit 6].
  153. */
  154. if (on)
  155. scratch |= 0x47;
  156. else
  157. scratch &= ~0x47;
  158. ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
  159. if (ret)
  160. return ret;
  161. return 0;
  162. }
  163. static int jmicron_probe(struct sdhci_pci_chip *chip)
  164. {
  165. int ret;
  166. if (chip->pdev->revision == 0) {
  167. chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
  168. SDHCI_QUIRK_32BIT_DMA_SIZE |
  169. SDHCI_QUIRK_32BIT_ADMA_SIZE |
  170. SDHCI_QUIRK_RESET_AFTER_REQUEST |
  171. SDHCI_QUIRK_BROKEN_SMALL_PIO;
  172. }
  173. /*
  174. * JMicron chips can have two interfaces to the same hardware
  175. * in order to work around limitations in Microsoft's driver.
  176. * We need to make sure we only bind to one of them.
  177. *
  178. * This code assumes two things:
  179. *
  180. * 1. The PCI code adds subfunctions in order.
  181. *
  182. * 2. The MMC interface has a lower subfunction number
  183. * than the SD interface.
  184. */
  185. if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) {
  186. struct pci_dev *sd_dev;
  187. sd_dev = NULL;
  188. while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
  189. PCI_DEVICE_ID_JMICRON_JMB38X_MMC, sd_dev)) != NULL) {
  190. if ((PCI_SLOT(chip->pdev->devfn) ==
  191. PCI_SLOT(sd_dev->devfn)) &&
  192. (chip->pdev->bus == sd_dev->bus))
  193. break;
  194. }
  195. if (sd_dev) {
  196. pci_dev_put(sd_dev);
  197. dev_info(&chip->pdev->dev, "Refusing to bind to "
  198. "secondary interface.\n");
  199. return -ENODEV;
  200. }
  201. }
  202. /*
  203. * JMicron chips need a bit of a nudge to enable the power
  204. * output pins.
  205. */
  206. ret = jmicron_pmos(chip, 1);
  207. if (ret) {
  208. dev_err(&chip->pdev->dev, "Failure enabling card power\n");
  209. return ret;
  210. }
  211. return 0;
  212. }
  213. static void jmicron_enable_mmc(struct sdhci_host *host, int on)
  214. {
  215. u8 scratch;
  216. scratch = readb(host->ioaddr + 0xC0);
  217. if (on)
  218. scratch |= 0x01;
  219. else
  220. scratch &= ~0x01;
  221. writeb(scratch, host->ioaddr + 0xC0);
  222. }
  223. static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
  224. {
  225. if (slot->chip->pdev->revision == 0) {
  226. u16 version;
  227. version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
  228. version = (version & SDHCI_VENDOR_VER_MASK) >>
  229. SDHCI_VENDOR_VER_SHIFT;
  230. /*
  231. * Older versions of the chip have lots of nasty glitches
  232. * in the ADMA engine. It's best just to avoid it
  233. * completely.
  234. */
  235. if (version < 0xAC)
  236. slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
  237. }
  238. /*
  239. * The secondary interface requires a bit set to get the
  240. * interrupts.
  241. */
  242. if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
  243. jmicron_enable_mmc(slot->host, 1);
  244. return 0;
  245. }
  246. static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
  247. {
  248. if (dead)
  249. return;
  250. if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
  251. jmicron_enable_mmc(slot->host, 0);
  252. }
  253. static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
  254. {
  255. int i;
  256. if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
  257. for (i = 0;i < chip->num_slots;i++)
  258. jmicron_enable_mmc(chip->slots[i]->host, 0);
  259. }
  260. return 0;
  261. }
  262. static int jmicron_resume(struct sdhci_pci_chip *chip)
  263. {
  264. int ret, i;
  265. if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
  266. for (i = 0;i < chip->num_slots;i++)
  267. jmicron_enable_mmc(chip->slots[i]->host, 1);
  268. }
  269. ret = jmicron_pmos(chip, 1);
  270. if (ret) {
  271. dev_err(&chip->pdev->dev, "Failure enabling card power\n");
  272. return ret;
  273. }
  274. return 0;
  275. }
  276. static const struct sdhci_pci_fixes sdhci_jmicron = {
  277. .probe = jmicron_probe,
  278. .probe_slot = jmicron_probe_slot,
  279. .remove_slot = jmicron_remove_slot,
  280. .suspend = jmicron_suspend,
  281. .resume = jmicron_resume,
  282. };
  283. /* SysKonnect CardBus2SDIO extra registers */
  284. #define SYSKT_CTRL 0x200
  285. #define SYSKT_RDFIFO_STAT 0x204
  286. #define SYSKT_WRFIFO_STAT 0x208
  287. #define SYSKT_POWER_DATA 0x20c
  288. #define SYSKT_POWER_330 0xef
  289. #define SYSKT_POWER_300 0xf8
  290. #define SYSKT_POWER_184 0xcc
  291. #define SYSKT_POWER_CMD 0x20d
  292. #define SYSKT_POWER_START (1 << 7)
  293. #define SYSKT_POWER_STATUS 0x20e
  294. #define SYSKT_POWER_STATUS_OK (1 << 0)
  295. #define SYSKT_BOARD_REV 0x210
  296. #define SYSKT_CHIP_REV 0x211
  297. #define SYSKT_CONF_DATA 0x212
  298. #define SYSKT_CONF_DATA_1V8 (1 << 2)
  299. #define SYSKT_CONF_DATA_2V5 (1 << 1)
  300. #define SYSKT_CONF_DATA_3V3 (1 << 0)
  301. static int syskt_probe(struct sdhci_pci_chip *chip)
  302. {
  303. if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  304. chip->pdev->class &= ~0x0000FF;
  305. chip->pdev->class |= PCI_SDHCI_IFDMA;
  306. }
  307. return 0;
  308. }
  309. static int syskt_probe_slot(struct sdhci_pci_slot *slot)
  310. {
  311. int tm, ps;
  312. u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
  313. u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
  314. dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
  315. "board rev %d.%d, chip rev %d.%d\n",
  316. board_rev >> 4, board_rev & 0xf,
  317. chip_rev >> 4, chip_rev & 0xf);
  318. if (chip_rev >= 0x20)
  319. slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
  320. writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
  321. writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
  322. udelay(50);
  323. tm = 10; /* Wait max 1 ms */
  324. do {
  325. ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
  326. if (ps & SYSKT_POWER_STATUS_OK)
  327. break;
  328. udelay(100);
  329. } while (--tm);
  330. if (!tm) {
  331. dev_err(&slot->chip->pdev->dev,
  332. "power regulator never stabilized");
  333. writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
  334. return -ENODEV;
  335. }
  336. return 0;
  337. }
  338. static const struct sdhci_pci_fixes sdhci_syskt = {
  339. .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
  340. .probe = syskt_probe,
  341. .probe_slot = syskt_probe_slot,
  342. };
  343. static int via_probe(struct sdhci_pci_chip *chip)
  344. {
  345. if (chip->pdev->revision == 0x10)
  346. chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
  347. return 0;
  348. }
  349. static const struct sdhci_pci_fixes sdhci_via = {
  350. .probe = via_probe,
  351. };
  352. static const struct pci_device_id pci_ids[] __devinitdata = {
  353. {
  354. .vendor = PCI_VENDOR_ID_RICOH,
  355. .device = PCI_DEVICE_ID_RICOH_R5C822,
  356. .subvendor = PCI_ANY_ID,
  357. .subdevice = PCI_ANY_ID,
  358. .driver_data = (kernel_ulong_t)&sdhci_ricoh,
  359. },
  360. {
  361. .vendor = PCI_VENDOR_ID_RICOH,
  362. .device = 0x843,
  363. .subvendor = PCI_ANY_ID,
  364. .subdevice = PCI_ANY_ID,
  365. .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
  366. },
  367. {
  368. .vendor = PCI_VENDOR_ID_RICOH,
  369. .device = 0xe822,
  370. .subvendor = PCI_ANY_ID,
  371. .subdevice = PCI_ANY_ID,
  372. .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
  373. },
  374. {
  375. .vendor = PCI_VENDOR_ID_ENE,
  376. .device = PCI_DEVICE_ID_ENE_CB712_SD,
  377. .subvendor = PCI_ANY_ID,
  378. .subdevice = PCI_ANY_ID,
  379. .driver_data = (kernel_ulong_t)&sdhci_ene_712,
  380. },
  381. {
  382. .vendor = PCI_VENDOR_ID_ENE,
  383. .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
  384. .subvendor = PCI_ANY_ID,
  385. .subdevice = PCI_ANY_ID,
  386. .driver_data = (kernel_ulong_t)&sdhci_ene_712,
  387. },
  388. {
  389. .vendor = PCI_VENDOR_ID_ENE,
  390. .device = PCI_DEVICE_ID_ENE_CB714_SD,
  391. .subvendor = PCI_ANY_ID,
  392. .subdevice = PCI_ANY_ID,
  393. .driver_data = (kernel_ulong_t)&sdhci_ene_714,
  394. },
  395. {
  396. .vendor = PCI_VENDOR_ID_ENE,
  397. .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
  398. .subvendor = PCI_ANY_ID,
  399. .subdevice = PCI_ANY_ID,
  400. .driver_data = (kernel_ulong_t)&sdhci_ene_714,
  401. },
  402. {
  403. .vendor = PCI_VENDOR_ID_MARVELL,
  404. .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
  405. .subvendor = PCI_ANY_ID,
  406. .subdevice = PCI_ANY_ID,
  407. .driver_data = (kernel_ulong_t)&sdhci_cafe,
  408. },
  409. {
  410. .vendor = PCI_VENDOR_ID_JMICRON,
  411. .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
  412. .subvendor = PCI_ANY_ID,
  413. .subdevice = PCI_ANY_ID,
  414. .driver_data = (kernel_ulong_t)&sdhci_jmicron,
  415. },
  416. {
  417. .vendor = PCI_VENDOR_ID_JMICRON,
  418. .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
  419. .subvendor = PCI_ANY_ID,
  420. .subdevice = PCI_ANY_ID,
  421. .driver_data = (kernel_ulong_t)&sdhci_jmicron,
  422. },
  423. {
  424. .vendor = PCI_VENDOR_ID_SYSKONNECT,
  425. .device = 0x8000,
  426. .subvendor = PCI_ANY_ID,
  427. .subdevice = PCI_ANY_ID,
  428. .driver_data = (kernel_ulong_t)&sdhci_syskt,
  429. },
  430. {
  431. .vendor = PCI_VENDOR_ID_VIA,
  432. .device = 0x95d0,
  433. .subvendor = PCI_ANY_ID,
  434. .subdevice = PCI_ANY_ID,
  435. .driver_data = (kernel_ulong_t)&sdhci_via,
  436. },
  437. {
  438. .vendor = PCI_VENDOR_ID_INTEL,
  439. .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
  440. .subvendor = PCI_ANY_ID,
  441. .subdevice = PCI_ANY_ID,
  442. .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
  443. },
  444. {
  445. .vendor = PCI_VENDOR_ID_INTEL,
  446. .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
  447. .subvendor = PCI_ANY_ID,
  448. .subdevice = PCI_ANY_ID,
  449. .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
  450. },
  451. {
  452. .vendor = PCI_VENDOR_ID_INTEL,
  453. .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
  454. .subvendor = PCI_ANY_ID,
  455. .subdevice = PCI_ANY_ID,
  456. .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
  457. },
  458. {
  459. .vendor = PCI_VENDOR_ID_INTEL,
  460. .device = PCI_DEVICE_ID_INTEL_MFD_SD,
  461. .subvendor = PCI_ANY_ID,
  462. .subdevice = PCI_ANY_ID,
  463. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
  464. },
  465. {
  466. .vendor = PCI_VENDOR_ID_INTEL,
  467. .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
  468. .subvendor = PCI_ANY_ID,
  469. .subdevice = PCI_ANY_ID,
  470. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  471. },
  472. {
  473. .vendor = PCI_VENDOR_ID_INTEL,
  474. .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
  475. .subvendor = PCI_ANY_ID,
  476. .subdevice = PCI_ANY_ID,
  477. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  478. },
  479. {
  480. .vendor = PCI_VENDOR_ID_INTEL,
  481. .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
  482. .subvendor = PCI_ANY_ID,
  483. .subdevice = PCI_ANY_ID,
  484. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  485. },
  486. {
  487. .vendor = PCI_VENDOR_ID_INTEL,
  488. .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
  489. .subvendor = PCI_ANY_ID,
  490. .subdevice = PCI_ANY_ID,
  491. .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
  492. },
  493. { /* Generic SD host controller */
  494. PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  495. },
  496. { /* end: all zeroes */ },
  497. };
  498. MODULE_DEVICE_TABLE(pci, pci_ids);
  499. /*****************************************************************************\
  500. * *
  501. * SDHCI core callbacks *
  502. * *
  503. \*****************************************************************************/
  504. static int sdhci_pci_enable_dma(struct sdhci_host *host)
  505. {
  506. struct sdhci_pci_slot *slot;
  507. struct pci_dev *pdev;
  508. int ret;
  509. slot = sdhci_priv(host);
  510. pdev = slot->chip->pdev;
  511. if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
  512. ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
  513. (host->flags & SDHCI_USE_SDMA)) {
  514. dev_warn(&pdev->dev, "Will use DMA mode even though HW "
  515. "doesn't fully claim to support it.\n");
  516. }
  517. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  518. if (ret)
  519. return ret;
  520. pci_set_master(pdev);
  521. return 0;
  522. }
  523. static struct sdhci_ops sdhci_pci_ops = {
  524. .enable_dma = sdhci_pci_enable_dma,
  525. };
  526. /*****************************************************************************\
  527. * *
  528. * Suspend/resume *
  529. * *
  530. \*****************************************************************************/
  531. #ifdef CONFIG_PM
  532. static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
  533. {
  534. struct sdhci_pci_chip *chip;
  535. struct sdhci_pci_slot *slot;
  536. mmc_pm_flag_t slot_pm_flags;
  537. mmc_pm_flag_t pm_flags = 0;
  538. int i, ret;
  539. chip = pci_get_drvdata(pdev);
  540. if (!chip)
  541. return 0;
  542. for (i = 0;i < chip->num_slots;i++) {
  543. slot = chip->slots[i];
  544. if (!slot)
  545. continue;
  546. ret = sdhci_suspend_host(slot->host, state);
  547. if (ret) {
  548. for (i--;i >= 0;i--)
  549. sdhci_resume_host(chip->slots[i]->host);
  550. return ret;
  551. }
  552. slot_pm_flags = slot->host->mmc->pm_flags;
  553. if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
  554. sdhci_enable_irq_wakeups(slot->host);
  555. pm_flags |= slot_pm_flags;
  556. }
  557. if (chip->fixes && chip->fixes->suspend) {
  558. ret = chip->fixes->suspend(chip, state);
  559. if (ret) {
  560. for (i = chip->num_slots - 1;i >= 0;i--)
  561. sdhci_resume_host(chip->slots[i]->host);
  562. return ret;
  563. }
  564. }
  565. pci_save_state(pdev);
  566. if (pm_flags & MMC_PM_KEEP_POWER) {
  567. if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
  568. pci_pme_active(pdev, true);
  569. pci_enable_wake(pdev, PCI_D3hot, 1);
  570. }
  571. pci_set_power_state(pdev, PCI_D3hot);
  572. } else {
  573. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  574. pci_disable_device(pdev);
  575. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  576. }
  577. return 0;
  578. }
  579. static int sdhci_pci_resume (struct pci_dev *pdev)
  580. {
  581. struct sdhci_pci_chip *chip;
  582. struct sdhci_pci_slot *slot;
  583. int i, ret;
  584. chip = pci_get_drvdata(pdev);
  585. if (!chip)
  586. return 0;
  587. pci_set_power_state(pdev, PCI_D0);
  588. pci_restore_state(pdev);
  589. ret = pci_enable_device(pdev);
  590. if (ret)
  591. return ret;
  592. if (chip->fixes && chip->fixes->resume) {
  593. ret = chip->fixes->resume(chip);
  594. if (ret)
  595. return ret;
  596. }
  597. for (i = 0;i < chip->num_slots;i++) {
  598. slot = chip->slots[i];
  599. if (!slot)
  600. continue;
  601. ret = sdhci_resume_host(slot->host);
  602. if (ret)
  603. return ret;
  604. }
  605. return 0;
  606. }
  607. #else /* CONFIG_PM */
  608. #define sdhci_pci_suspend NULL
  609. #define sdhci_pci_resume NULL
  610. #endif /* CONFIG_PM */
  611. /*****************************************************************************\
  612. * *
  613. * Device probing/removal *
  614. * *
  615. \*****************************************************************************/
  616. static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
  617. struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
  618. {
  619. struct sdhci_pci_slot *slot;
  620. struct sdhci_host *host;
  621. resource_size_t addr;
  622. int ret;
  623. if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
  624. dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
  625. return ERR_PTR(-ENODEV);
  626. }
  627. if (pci_resource_len(pdev, bar) != 0x100) {
  628. dev_err(&pdev->dev, "Invalid iomem size. You may "
  629. "experience problems.\n");
  630. }
  631. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  632. dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
  633. return ERR_PTR(-ENODEV);
  634. }
  635. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  636. dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
  637. return ERR_PTR(-ENODEV);
  638. }
  639. host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
  640. if (IS_ERR(host)) {
  641. dev_err(&pdev->dev, "cannot allocate host\n");
  642. return ERR_CAST(host);
  643. }
  644. slot = sdhci_priv(host);
  645. slot->chip = chip;
  646. slot->host = host;
  647. slot->pci_bar = bar;
  648. host->hw_name = "PCI";
  649. host->ops = &sdhci_pci_ops;
  650. host->quirks = chip->quirks;
  651. host->irq = pdev->irq;
  652. ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
  653. if (ret) {
  654. dev_err(&pdev->dev, "cannot request region\n");
  655. goto free;
  656. }
  657. addr = pci_resource_start(pdev, bar);
  658. host->ioaddr = pci_ioremap_bar(pdev, bar);
  659. if (!host->ioaddr) {
  660. dev_err(&pdev->dev, "failed to remap registers\n");
  661. goto release;
  662. }
  663. if (chip->fixes && chip->fixes->probe_slot) {
  664. ret = chip->fixes->probe_slot(slot);
  665. if (ret)
  666. goto unmap;
  667. }
  668. host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
  669. ret = sdhci_add_host(host);
  670. if (ret)
  671. goto remove;
  672. return slot;
  673. remove:
  674. if (chip->fixes && chip->fixes->remove_slot)
  675. chip->fixes->remove_slot(slot, 0);
  676. unmap:
  677. iounmap(host->ioaddr);
  678. release:
  679. pci_release_region(pdev, bar);
  680. free:
  681. sdhci_free_host(host);
  682. return ERR_PTR(ret);
  683. }
  684. static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
  685. {
  686. int dead;
  687. u32 scratch;
  688. dead = 0;
  689. scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
  690. if (scratch == (u32)-1)
  691. dead = 1;
  692. sdhci_remove_host(slot->host, dead);
  693. if (slot->chip->fixes && slot->chip->fixes->remove_slot)
  694. slot->chip->fixes->remove_slot(slot, dead);
  695. pci_release_region(slot->chip->pdev, slot->pci_bar);
  696. sdhci_free_host(slot->host);
  697. }
  698. static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
  699. const struct pci_device_id *ent)
  700. {
  701. struct sdhci_pci_chip *chip;
  702. struct sdhci_pci_slot *slot;
  703. u8 slots, rev, first_bar;
  704. int ret, i;
  705. BUG_ON(pdev == NULL);
  706. BUG_ON(ent == NULL);
  707. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  708. dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
  709. (int)pdev->vendor, (int)pdev->device, (int)rev);
  710. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  711. if (ret)
  712. return ret;
  713. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  714. dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
  715. if (slots == 0)
  716. return -ENODEV;
  717. BUG_ON(slots > MAX_SLOTS);
  718. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  719. if (ret)
  720. return ret;
  721. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  722. if (first_bar > 5) {
  723. dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
  724. return -ENODEV;
  725. }
  726. ret = pci_enable_device(pdev);
  727. if (ret)
  728. return ret;
  729. chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
  730. if (!chip) {
  731. ret = -ENOMEM;
  732. goto err;
  733. }
  734. chip->pdev = pdev;
  735. chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data;
  736. if (chip->fixes)
  737. chip->quirks = chip->fixes->quirks;
  738. chip->num_slots = slots;
  739. pci_set_drvdata(pdev, chip);
  740. if (chip->fixes && chip->fixes->probe) {
  741. ret = chip->fixes->probe(chip);
  742. if (ret)
  743. goto free;
  744. }
  745. slots = chip->num_slots; /* Quirk may have changed this */
  746. for (i = 0;i < slots;i++) {
  747. slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
  748. if (IS_ERR(slot)) {
  749. for (i--;i >= 0;i--)
  750. sdhci_pci_remove_slot(chip->slots[i]);
  751. ret = PTR_ERR(slot);
  752. goto free;
  753. }
  754. chip->slots[i] = slot;
  755. }
  756. return 0;
  757. free:
  758. pci_set_drvdata(pdev, NULL);
  759. kfree(chip);
  760. err:
  761. pci_disable_device(pdev);
  762. return ret;
  763. }
  764. static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
  765. {
  766. int i;
  767. struct sdhci_pci_chip *chip;
  768. chip = pci_get_drvdata(pdev);
  769. if (chip) {
  770. for (i = 0;i < chip->num_slots; i++)
  771. sdhci_pci_remove_slot(chip->slots[i]);
  772. pci_set_drvdata(pdev, NULL);
  773. kfree(chip);
  774. }
  775. pci_disable_device(pdev);
  776. }
  777. static struct pci_driver sdhci_driver = {
  778. .name = "sdhci-pci",
  779. .id_table = pci_ids,
  780. .probe = sdhci_pci_probe,
  781. .remove = __devexit_p(sdhci_pci_remove),
  782. .suspend = sdhci_pci_suspend,
  783. .resume = sdhci_pci_resume,
  784. };
  785. /*****************************************************************************\
  786. * *
  787. * Driver init/exit *
  788. * *
  789. \*****************************************************************************/
  790. static int __init sdhci_drv_init(void)
  791. {
  792. return pci_register_driver(&sdhci_driver);
  793. }
  794. static void __exit sdhci_drv_exit(void)
  795. {
  796. pci_unregister_driver(&sdhci_driver);
  797. }
  798. module_init(sdhci_drv_init);
  799. module_exit(sdhci_drv_exit);
  800. MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
  801. MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
  802. MODULE_LICENSE("GPL");