pm34xx.c 29 KB

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  1. /*
  2. * OMAP3 Power Management Routines
  3. *
  4. * Copyright (C) 2006-2008 Nokia Corporation
  5. * Tony Lindgren <tony@atomide.com>
  6. * Jouni Hogander
  7. *
  8. * Copyright (C) 2007 Texas Instruments, Inc.
  9. * Rajendra Nayak <rnayak@ti.com>
  10. *
  11. * Copyright (C) 2005 Texas Instruments, Inc.
  12. * Richard Woodruff <r-woodruff2@ti.com>
  13. *
  14. * Based on pm.c for omap1
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/pm.h>
  21. #include <linux/suspend.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/module.h>
  24. #include <linux/list.h>
  25. #include <linux/err.h>
  26. #include <linux/gpio.h>
  27. #include <linux/clk.h>
  28. #include <linux/delay.h>
  29. #include <linux/slab.h>
  30. #include <linux/console.h>
  31. #include <plat/sram.h>
  32. #include <plat/clockdomain.h>
  33. #include <plat/powerdomain.h>
  34. #include <plat/serial.h>
  35. #include <plat/sdrc.h>
  36. #include <plat/prcm.h>
  37. #include <plat/gpmc.h>
  38. #include <plat/dma.h>
  39. #include <asm/tlbflush.h>
  40. #include "cm.h"
  41. #include "cm-regbits-34xx.h"
  42. #include "prm-regbits-34xx.h"
  43. #include "prm.h"
  44. #include "pm.h"
  45. #include "sdrc.h"
  46. #include "control.h"
  47. #ifdef CONFIG_SUSPEND
  48. static suspend_state_t suspend_state = PM_SUSPEND_ON;
  49. static inline bool is_suspending(void)
  50. {
  51. return (suspend_state != PM_SUSPEND_ON);
  52. }
  53. #else
  54. static inline bool is_suspending(void)
  55. {
  56. return false;
  57. }
  58. #endif
  59. /* Scratchpad offsets */
  60. #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
  61. #define OMAP343X_TABLE_VALUE_OFFSET 0xc0
  62. #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
  63. struct power_state {
  64. struct powerdomain *pwrdm;
  65. u32 next_state;
  66. #ifdef CONFIG_SUSPEND
  67. u32 saved_state;
  68. #endif
  69. struct list_head node;
  70. };
  71. static LIST_HEAD(pwrst_list);
  72. static void (*_omap_sram_idle)(u32 *addr, int save_state);
  73. static int (*_omap_save_secure_sram)(u32 *addr);
  74. static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  75. static struct powerdomain *core_pwrdm, *per_pwrdm;
  76. static struct powerdomain *cam_pwrdm;
  77. static inline void omap3_per_save_context(void)
  78. {
  79. omap_gpio_save_context();
  80. }
  81. static inline void omap3_per_restore_context(void)
  82. {
  83. omap_gpio_restore_context();
  84. }
  85. static void omap3_enable_io_chain(void)
  86. {
  87. int timeout = 0;
  88. if (omap_rev() >= OMAP3430_REV_ES3_1) {
  89. prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  90. PM_WKEN);
  91. /* Do a readback to assure write has been done */
  92. prm_read_mod_reg(WKUP_MOD, PM_WKEN);
  93. while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
  94. OMAP3430_ST_IO_CHAIN_MASK)) {
  95. timeout++;
  96. if (timeout > 1000) {
  97. printk(KERN_ERR "Wake up daisy chain "
  98. "activation failed.\n");
  99. return;
  100. }
  101. prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
  102. WKUP_MOD, PM_WKEN);
  103. }
  104. }
  105. }
  106. static void omap3_disable_io_chain(void)
  107. {
  108. if (omap_rev() >= OMAP3430_REV_ES3_1)
  109. prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  110. PM_WKEN);
  111. }
  112. static void omap3_core_save_context(void)
  113. {
  114. u32 control_padconf_off;
  115. /* Save the padconf registers */
  116. control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
  117. control_padconf_off |= START_PADCONF_SAVE;
  118. omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
  119. /* wait for the save to complete */
  120. while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
  121. & PADCONF_SAVE_DONE))
  122. udelay(1);
  123. /*
  124. * Force write last pad into memory, as this can fail in some
  125. * cases according to erratas 1.157, 1.185
  126. */
  127. omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
  128. OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
  129. /* Save the Interrupt controller context */
  130. omap_intc_save_context();
  131. /* Save the GPMC context */
  132. omap3_gpmc_save_context();
  133. /* Save the system control module context, padconf already save above*/
  134. omap3_control_save_context();
  135. omap_dma_global_context_save();
  136. }
  137. static void omap3_core_restore_context(void)
  138. {
  139. /* Restore the control module context, padconf restored by h/w */
  140. omap3_control_restore_context();
  141. /* Restore the GPMC context */
  142. omap3_gpmc_restore_context();
  143. /* Restore the interrupt controller context */
  144. omap_intc_restore_context();
  145. omap_dma_global_context_restore();
  146. }
  147. /*
  148. * FIXME: This function should be called before entering off-mode after
  149. * OMAP3 secure services have been accessed. Currently it is only called
  150. * once during boot sequence, but this works as we are not using secure
  151. * services.
  152. */
  153. static void omap3_save_secure_ram_context(u32 target_mpu_state)
  154. {
  155. u32 ret;
  156. if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
  157. /*
  158. * MPU next state must be set to POWER_ON temporarily,
  159. * otherwise the WFI executed inside the ROM code
  160. * will hang the system.
  161. */
  162. pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
  163. ret = _omap_save_secure_sram((u32 *)
  164. __pa(omap3_secure_ram_storage));
  165. pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
  166. /* Following is for error tracking, it should not happen */
  167. if (ret) {
  168. printk(KERN_ERR "save_secure_sram() returns %08x\n",
  169. ret);
  170. while (1)
  171. ;
  172. }
  173. }
  174. }
  175. /*
  176. * PRCM Interrupt Handler Helper Function
  177. *
  178. * The purpose of this function is to clear any wake-up events latched
  179. * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
  180. * may occur whilst attempting to clear a PM_WKST_x register and thus
  181. * set another bit in this register. A while loop is used to ensure
  182. * that any peripheral wake-up events occurring while attempting to
  183. * clear the PM_WKST_x are detected and cleared.
  184. */
  185. static int prcm_clear_mod_irqs(s16 module, u8 regs)
  186. {
  187. u32 wkst, fclk, iclk, clken;
  188. u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
  189. u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
  190. u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
  191. u16 grpsel_off = (regs == 3) ?
  192. OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
  193. int c = 0;
  194. wkst = prm_read_mod_reg(module, wkst_off);
  195. wkst &= prm_read_mod_reg(module, grpsel_off);
  196. if (wkst) {
  197. iclk = cm_read_mod_reg(module, iclk_off);
  198. fclk = cm_read_mod_reg(module, fclk_off);
  199. while (wkst) {
  200. clken = wkst;
  201. cm_set_mod_reg_bits(clken, module, iclk_off);
  202. /*
  203. * For USBHOST, we don't know whether HOST1 or
  204. * HOST2 woke us up, so enable both f-clocks
  205. */
  206. if (module == OMAP3430ES2_USBHOST_MOD)
  207. clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
  208. cm_set_mod_reg_bits(clken, module, fclk_off);
  209. prm_write_mod_reg(wkst, module, wkst_off);
  210. wkst = prm_read_mod_reg(module, wkst_off);
  211. c++;
  212. }
  213. cm_write_mod_reg(iclk, module, iclk_off);
  214. cm_write_mod_reg(fclk, module, fclk_off);
  215. }
  216. return c;
  217. }
  218. static int _prcm_int_handle_wakeup(void)
  219. {
  220. int c;
  221. c = prcm_clear_mod_irqs(WKUP_MOD, 1);
  222. c += prcm_clear_mod_irqs(CORE_MOD, 1);
  223. c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
  224. if (omap_rev() > OMAP3430_REV_ES1_0) {
  225. c += prcm_clear_mod_irqs(CORE_MOD, 3);
  226. c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
  227. }
  228. return c;
  229. }
  230. /*
  231. * PRCM Interrupt Handler
  232. *
  233. * The PRM_IRQSTATUS_MPU register indicates if there are any pending
  234. * interrupts from the PRCM for the MPU. These bits must be cleared in
  235. * order to clear the PRCM interrupt. The PRCM interrupt handler is
  236. * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
  237. * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
  238. * register indicates that a wake-up event is pending for the MPU and
  239. * this bit can only be cleared if the all the wake-up events latched
  240. * in the various PM_WKST_x registers have been cleared. The interrupt
  241. * handler is implemented using a do-while loop so that if a wake-up
  242. * event occurred during the processing of the prcm interrupt handler
  243. * (setting a bit in the corresponding PM_WKST_x register and thus
  244. * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
  245. * this would be handled.
  246. */
  247. static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
  248. {
  249. u32 irqenable_mpu, irqstatus_mpu;
  250. int c = 0;
  251. irqenable_mpu = prm_read_mod_reg(OCP_MOD,
  252. OMAP3_PRM_IRQENABLE_MPU_OFFSET);
  253. irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
  254. OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  255. irqstatus_mpu &= irqenable_mpu;
  256. do {
  257. if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
  258. OMAP3430_IO_ST_MASK)) {
  259. c = _prcm_int_handle_wakeup();
  260. /*
  261. * Is the MPU PRCM interrupt handler racing with the
  262. * IVA2 PRCM interrupt handler ?
  263. */
  264. WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
  265. "but no wakeup sources are marked\n");
  266. } else {
  267. /* XXX we need to expand our PRCM interrupt handler */
  268. WARN(1, "prcm: WARNING: PRCM interrupt received, but "
  269. "no code to handle it (%08x)\n", irqstatus_mpu);
  270. }
  271. prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
  272. OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  273. irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
  274. OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  275. irqstatus_mpu &= irqenable_mpu;
  276. } while (irqstatus_mpu);
  277. return IRQ_HANDLED;
  278. }
  279. static void restore_control_register(u32 val)
  280. {
  281. __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
  282. }
  283. /* Function to restore the table entry that was modified for enabling MMU */
  284. static void restore_table_entry(void)
  285. {
  286. void __iomem *scratchpad_address;
  287. u32 previous_value, control_reg_value;
  288. u32 *address;
  289. scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
  290. /* Get address of entry that was modified */
  291. address = (u32 *)__raw_readl(scratchpad_address +
  292. OMAP343X_TABLE_ADDRESS_OFFSET);
  293. /* Get the previous value which needs to be restored */
  294. previous_value = __raw_readl(scratchpad_address +
  295. OMAP343X_TABLE_VALUE_OFFSET);
  296. address = __va(address);
  297. *address = previous_value;
  298. flush_tlb_all();
  299. control_reg_value = __raw_readl(scratchpad_address
  300. + OMAP343X_CONTROL_REG_VALUE_OFFSET);
  301. /* This will enable caches and prediction */
  302. restore_control_register(control_reg_value);
  303. }
  304. void omap_sram_idle(void)
  305. {
  306. /* Variable to tell what needs to be saved and restored
  307. * in omap_sram_idle*/
  308. /* save_state = 0 => Nothing to save and restored */
  309. /* save_state = 1 => Only L1 and logic lost */
  310. /* save_state = 2 => Only L2 lost */
  311. /* save_state = 3 => L1, L2 and logic lost */
  312. int save_state = 0;
  313. int mpu_next_state = PWRDM_POWER_ON;
  314. int per_next_state = PWRDM_POWER_ON;
  315. int core_next_state = PWRDM_POWER_ON;
  316. int core_prev_state, per_prev_state;
  317. u32 sdrc_pwr = 0;
  318. if (!_omap_sram_idle)
  319. return;
  320. pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
  321. pwrdm_clear_all_prev_pwrst(neon_pwrdm);
  322. pwrdm_clear_all_prev_pwrst(core_pwrdm);
  323. pwrdm_clear_all_prev_pwrst(per_pwrdm);
  324. mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
  325. switch (mpu_next_state) {
  326. case PWRDM_POWER_ON:
  327. case PWRDM_POWER_RET:
  328. /* No need to save context */
  329. save_state = 0;
  330. break;
  331. case PWRDM_POWER_OFF:
  332. save_state = 3;
  333. break;
  334. default:
  335. /* Invalid state */
  336. printk(KERN_ERR "Invalid mpu state in sram_idle\n");
  337. return;
  338. }
  339. pwrdm_pre_transition();
  340. /* NEON control */
  341. if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
  342. pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
  343. /* Enable IO-PAD and IO-CHAIN wakeups */
  344. per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
  345. core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
  346. if (omap3_has_io_wakeup() &&
  347. (per_next_state < PWRDM_POWER_ON ||
  348. core_next_state < PWRDM_POWER_ON)) {
  349. prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
  350. omap3_enable_io_chain();
  351. }
  352. /* Block console output in case it is on one of the OMAP UARTs */
  353. if (!is_suspending())
  354. if (per_next_state < PWRDM_POWER_ON ||
  355. core_next_state < PWRDM_POWER_ON)
  356. if (try_acquire_console_sem())
  357. goto console_still_active;
  358. /* PER */
  359. if (per_next_state < PWRDM_POWER_ON) {
  360. omap_uart_prepare_idle(2);
  361. omap_uart_prepare_idle(3);
  362. omap2_gpio_prepare_for_idle(per_next_state);
  363. if (per_next_state == PWRDM_POWER_OFF)
  364. omap3_per_save_context();
  365. }
  366. /* CORE */
  367. if (core_next_state < PWRDM_POWER_ON) {
  368. omap_uart_prepare_idle(0);
  369. omap_uart_prepare_idle(1);
  370. if (core_next_state == PWRDM_POWER_OFF) {
  371. omap3_core_save_context();
  372. omap3_prcm_save_context();
  373. }
  374. }
  375. omap3_intc_prepare_idle();
  376. /*
  377. * On EMU/HS devices ROM code restores a SRDC value
  378. * from scratchpad which has automatic self refresh on timeout
  379. * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
  380. * Hence store/restore the SDRC_POWER register here.
  381. */
  382. if (omap_rev() >= OMAP3430_REV_ES3_0 &&
  383. omap_type() != OMAP2_DEVICE_TYPE_GP &&
  384. core_next_state == PWRDM_POWER_OFF)
  385. sdrc_pwr = sdrc_read_reg(SDRC_POWER);
  386. /*
  387. * omap3_arm_context is the location where ARM registers
  388. * get saved. The restore path then reads from this
  389. * location and restores them back.
  390. */
  391. _omap_sram_idle(omap3_arm_context, save_state);
  392. cpu_init();
  393. /* Restore normal SDRC POWER settings */
  394. if (omap_rev() >= OMAP3430_REV_ES3_0 &&
  395. omap_type() != OMAP2_DEVICE_TYPE_GP &&
  396. core_next_state == PWRDM_POWER_OFF)
  397. sdrc_write_reg(sdrc_pwr, SDRC_POWER);
  398. /* Restore table entry modified during MMU restoration */
  399. if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
  400. restore_table_entry();
  401. /* CORE */
  402. if (core_next_state < PWRDM_POWER_ON) {
  403. core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
  404. if (core_prev_state == PWRDM_POWER_OFF) {
  405. omap3_core_restore_context();
  406. omap3_prcm_restore_context();
  407. omap3_sram_restore_context();
  408. omap2_sms_restore_context();
  409. }
  410. omap_uart_resume_idle(0);
  411. omap_uart_resume_idle(1);
  412. if (core_next_state == PWRDM_POWER_OFF)
  413. prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
  414. OMAP3430_GR_MOD,
  415. OMAP3_PRM_VOLTCTRL_OFFSET);
  416. }
  417. omap3_intc_resume_idle();
  418. /* PER */
  419. if (per_next_state < PWRDM_POWER_ON) {
  420. per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
  421. omap2_gpio_resume_after_idle();
  422. if (per_prev_state == PWRDM_POWER_OFF)
  423. omap3_per_restore_context();
  424. omap_uart_resume_idle(2);
  425. omap_uart_resume_idle(3);
  426. }
  427. if (!is_suspending())
  428. release_console_sem();
  429. console_still_active:
  430. /* Disable IO-PAD and IO-CHAIN wakeup */
  431. if (omap3_has_io_wakeup() &&
  432. (per_next_state < PWRDM_POWER_ON ||
  433. core_next_state < PWRDM_POWER_ON)) {
  434. prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
  435. omap3_disable_io_chain();
  436. }
  437. pwrdm_post_transition();
  438. omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
  439. }
  440. int omap3_can_sleep(void)
  441. {
  442. if (!sleep_while_idle)
  443. return 0;
  444. if (!omap_uart_can_sleep())
  445. return 0;
  446. return 1;
  447. }
  448. static void omap3_pm_idle(void)
  449. {
  450. local_irq_disable();
  451. local_fiq_disable();
  452. if (!omap3_can_sleep())
  453. goto out;
  454. if (omap_irq_pending() || need_resched())
  455. goto out;
  456. omap_sram_idle();
  457. out:
  458. local_fiq_enable();
  459. local_irq_enable();
  460. }
  461. #ifdef CONFIG_SUSPEND
  462. static int omap3_pm_prepare(void)
  463. {
  464. disable_hlt();
  465. return 0;
  466. }
  467. static int omap3_pm_suspend(void)
  468. {
  469. struct power_state *pwrst;
  470. int state, ret = 0;
  471. if (wakeup_timer_seconds || wakeup_timer_milliseconds)
  472. omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
  473. wakeup_timer_milliseconds);
  474. /* Read current next_pwrsts */
  475. list_for_each_entry(pwrst, &pwrst_list, node)
  476. pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
  477. /* Set ones wanted by suspend */
  478. list_for_each_entry(pwrst, &pwrst_list, node) {
  479. if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
  480. goto restore;
  481. if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
  482. goto restore;
  483. }
  484. omap_uart_prepare_suspend();
  485. omap3_intc_suspend();
  486. omap_sram_idle();
  487. restore:
  488. /* Restore next_pwrsts */
  489. list_for_each_entry(pwrst, &pwrst_list, node) {
  490. state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
  491. if (state > pwrst->next_state) {
  492. printk(KERN_INFO "Powerdomain (%s) didn't enter "
  493. "target state %d\n",
  494. pwrst->pwrdm->name, pwrst->next_state);
  495. ret = -1;
  496. }
  497. omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
  498. }
  499. if (ret)
  500. printk(KERN_ERR "Could not enter target state in pm_suspend\n");
  501. else
  502. printk(KERN_INFO "Successfully put all powerdomains "
  503. "to target state\n");
  504. return ret;
  505. }
  506. static int omap3_pm_enter(suspend_state_t unused)
  507. {
  508. int ret = 0;
  509. switch (suspend_state) {
  510. case PM_SUSPEND_STANDBY:
  511. case PM_SUSPEND_MEM:
  512. ret = omap3_pm_suspend();
  513. break;
  514. default:
  515. ret = -EINVAL;
  516. }
  517. return ret;
  518. }
  519. static void omap3_pm_finish(void)
  520. {
  521. enable_hlt();
  522. }
  523. /* Hooks to enable / disable UART interrupts during suspend */
  524. static int omap3_pm_begin(suspend_state_t state)
  525. {
  526. suspend_state = state;
  527. omap_uart_enable_irqs(0);
  528. return 0;
  529. }
  530. static void omap3_pm_end(void)
  531. {
  532. suspend_state = PM_SUSPEND_ON;
  533. omap_uart_enable_irqs(1);
  534. return;
  535. }
  536. static struct platform_suspend_ops omap_pm_ops = {
  537. .begin = omap3_pm_begin,
  538. .end = omap3_pm_end,
  539. .prepare = omap3_pm_prepare,
  540. .enter = omap3_pm_enter,
  541. .finish = omap3_pm_finish,
  542. .valid = suspend_valid_only_mem,
  543. };
  544. #endif /* CONFIG_SUSPEND */
  545. /**
  546. * omap3_iva_idle(): ensure IVA is in idle so it can be put into
  547. * retention
  548. *
  549. * In cases where IVA2 is activated by bootcode, it may prevent
  550. * full-chip retention or off-mode because it is not idle. This
  551. * function forces the IVA2 into idle state so it can go
  552. * into retention/off and thus allow full-chip retention/off.
  553. *
  554. **/
  555. static void __init omap3_iva_idle(void)
  556. {
  557. /* ensure IVA2 clock is disabled */
  558. cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
  559. /* if no clock activity, nothing else to do */
  560. if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
  561. OMAP3430_CLKACTIVITY_IVA2_MASK))
  562. return;
  563. /* Reset IVA2 */
  564. prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
  565. OMAP3430_RST2_IVA2_MASK |
  566. OMAP3430_RST3_IVA2_MASK,
  567. OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
  568. /* Enable IVA2 clock */
  569. cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
  570. OMAP3430_IVA2_MOD, CM_FCLKEN);
  571. /* Set IVA2 boot mode to 'idle' */
  572. omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
  573. OMAP343X_CONTROL_IVA2_BOOTMOD);
  574. /* Un-reset IVA2 */
  575. prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
  576. /* Disable IVA2 clock */
  577. cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
  578. /* Reset IVA2 */
  579. prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
  580. OMAP3430_RST2_IVA2_MASK |
  581. OMAP3430_RST3_IVA2_MASK,
  582. OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
  583. }
  584. static void __init omap3_d2d_idle(void)
  585. {
  586. u16 mask, padconf;
  587. /* In a stand alone OMAP3430 where there is not a stacked
  588. * modem for the D2D Idle Ack and D2D MStandby must be pulled
  589. * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
  590. * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
  591. mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
  592. padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
  593. padconf |= mask;
  594. omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
  595. padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
  596. padconf |= mask;
  597. omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
  598. /* reset modem */
  599. prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
  600. OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
  601. CORE_MOD, OMAP2_RM_RSTCTRL);
  602. prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
  603. }
  604. static void __init prcm_setup_regs(void)
  605. {
  606. u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
  607. OMAP3630_AUTO_UART4_MASK : 0;
  608. u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
  609. OMAP3630_EN_UART4_MASK : 0;
  610. u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
  611. OMAP3630_GRPSEL_UART4_MASK : 0;
  612. /* XXX Reset all wkdeps. This should be done when initializing
  613. * powerdomains */
  614. prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
  615. prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
  616. prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
  617. prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
  618. prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
  619. prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
  620. if (omap_rev() > OMAP3430_REV_ES1_0) {
  621. prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
  622. prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
  623. } else
  624. prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
  625. /*
  626. * Enable interface clock autoidle for all modules.
  627. * Note that in the long run this should be done by clockfw
  628. */
  629. cm_write_mod_reg(
  630. OMAP3430_AUTO_MODEM_MASK |
  631. OMAP3430ES2_AUTO_MMC3_MASK |
  632. OMAP3430ES2_AUTO_ICR_MASK |
  633. OMAP3430_AUTO_AES2_MASK |
  634. OMAP3430_AUTO_SHA12_MASK |
  635. OMAP3430_AUTO_DES2_MASK |
  636. OMAP3430_AUTO_MMC2_MASK |
  637. OMAP3430_AUTO_MMC1_MASK |
  638. OMAP3430_AUTO_MSPRO_MASK |
  639. OMAP3430_AUTO_HDQ_MASK |
  640. OMAP3430_AUTO_MCSPI4_MASK |
  641. OMAP3430_AUTO_MCSPI3_MASK |
  642. OMAP3430_AUTO_MCSPI2_MASK |
  643. OMAP3430_AUTO_MCSPI1_MASK |
  644. OMAP3430_AUTO_I2C3_MASK |
  645. OMAP3430_AUTO_I2C2_MASK |
  646. OMAP3430_AUTO_I2C1_MASK |
  647. OMAP3430_AUTO_UART2_MASK |
  648. OMAP3430_AUTO_UART1_MASK |
  649. OMAP3430_AUTO_GPT11_MASK |
  650. OMAP3430_AUTO_GPT10_MASK |
  651. OMAP3430_AUTO_MCBSP5_MASK |
  652. OMAP3430_AUTO_MCBSP1_MASK |
  653. OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
  654. OMAP3430_AUTO_MAILBOXES_MASK |
  655. OMAP3430_AUTO_OMAPCTRL_MASK |
  656. OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
  657. OMAP3430_AUTO_HSOTGUSB_MASK |
  658. OMAP3430_AUTO_SAD2D_MASK |
  659. OMAP3430_AUTO_SSI_MASK,
  660. CORE_MOD, CM_AUTOIDLE1);
  661. cm_write_mod_reg(
  662. OMAP3430_AUTO_PKA_MASK |
  663. OMAP3430_AUTO_AES1_MASK |
  664. OMAP3430_AUTO_RNG_MASK |
  665. OMAP3430_AUTO_SHA11_MASK |
  666. OMAP3430_AUTO_DES1_MASK,
  667. CORE_MOD, CM_AUTOIDLE2);
  668. if (omap_rev() > OMAP3430_REV_ES1_0) {
  669. cm_write_mod_reg(
  670. OMAP3430_AUTO_MAD2D_MASK |
  671. OMAP3430ES2_AUTO_USBTLL_MASK,
  672. CORE_MOD, CM_AUTOIDLE3);
  673. }
  674. cm_write_mod_reg(
  675. OMAP3430_AUTO_WDT2_MASK |
  676. OMAP3430_AUTO_WDT1_MASK |
  677. OMAP3430_AUTO_GPIO1_MASK |
  678. OMAP3430_AUTO_32KSYNC_MASK |
  679. OMAP3430_AUTO_GPT12_MASK |
  680. OMAP3430_AUTO_GPT1_MASK,
  681. WKUP_MOD, CM_AUTOIDLE);
  682. cm_write_mod_reg(
  683. OMAP3430_AUTO_DSS_MASK,
  684. OMAP3430_DSS_MOD,
  685. CM_AUTOIDLE);
  686. cm_write_mod_reg(
  687. OMAP3430_AUTO_CAM_MASK,
  688. OMAP3430_CAM_MOD,
  689. CM_AUTOIDLE);
  690. cm_write_mod_reg(
  691. omap3630_auto_uart4_mask |
  692. OMAP3430_AUTO_GPIO6_MASK |
  693. OMAP3430_AUTO_GPIO5_MASK |
  694. OMAP3430_AUTO_GPIO4_MASK |
  695. OMAP3430_AUTO_GPIO3_MASK |
  696. OMAP3430_AUTO_GPIO2_MASK |
  697. OMAP3430_AUTO_WDT3_MASK |
  698. OMAP3430_AUTO_UART3_MASK |
  699. OMAP3430_AUTO_GPT9_MASK |
  700. OMAP3430_AUTO_GPT8_MASK |
  701. OMAP3430_AUTO_GPT7_MASK |
  702. OMAP3430_AUTO_GPT6_MASK |
  703. OMAP3430_AUTO_GPT5_MASK |
  704. OMAP3430_AUTO_GPT4_MASK |
  705. OMAP3430_AUTO_GPT3_MASK |
  706. OMAP3430_AUTO_GPT2_MASK |
  707. OMAP3430_AUTO_MCBSP4_MASK |
  708. OMAP3430_AUTO_MCBSP3_MASK |
  709. OMAP3430_AUTO_MCBSP2_MASK,
  710. OMAP3430_PER_MOD,
  711. CM_AUTOIDLE);
  712. if (omap_rev() > OMAP3430_REV_ES1_0) {
  713. cm_write_mod_reg(
  714. OMAP3430ES2_AUTO_USBHOST_MASK,
  715. OMAP3430ES2_USBHOST_MOD,
  716. CM_AUTOIDLE);
  717. }
  718. omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
  719. /*
  720. * Set all plls to autoidle. This is needed until autoidle is
  721. * enabled by clockfw
  722. */
  723. cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
  724. OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
  725. cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
  726. MPU_MOD,
  727. CM_AUTOIDLE2);
  728. cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
  729. (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
  730. PLL_MOD,
  731. CM_AUTOIDLE);
  732. cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
  733. PLL_MOD,
  734. CM_AUTOIDLE2);
  735. /*
  736. * Enable control of expternal oscillator through
  737. * sys_clkreq. In the long run clock framework should
  738. * take care of this.
  739. */
  740. prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
  741. 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
  742. OMAP3430_GR_MOD,
  743. OMAP3_PRM_CLKSRC_CTRL_OFFSET);
  744. /* setup wakup source */
  745. prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
  746. OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
  747. WKUP_MOD, PM_WKEN);
  748. /* No need to write EN_IO, that is always enabled */
  749. prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
  750. OMAP3430_GRPSEL_GPT1_MASK |
  751. OMAP3430_GRPSEL_GPT12_MASK,
  752. WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
  753. /* For some reason IO doesn't generate wakeup event even if
  754. * it is selected to mpu wakeup goup */
  755. prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
  756. OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
  757. /* Enable PM_WKEN to support DSS LPR */
  758. prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
  759. OMAP3430_DSS_MOD, PM_WKEN);
  760. /* Enable wakeups in PER */
  761. prm_write_mod_reg(omap3630_en_uart4_mask |
  762. OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
  763. OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
  764. OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
  765. OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
  766. OMAP3430_EN_MCBSP4_MASK,
  767. OMAP3430_PER_MOD, PM_WKEN);
  768. /* and allow them to wake up MPU */
  769. prm_write_mod_reg(omap3630_grpsel_uart4_mask |
  770. OMAP3430_GRPSEL_GPIO2_MASK |
  771. OMAP3430_GRPSEL_GPIO3_MASK |
  772. OMAP3430_GRPSEL_GPIO4_MASK |
  773. OMAP3430_GRPSEL_GPIO5_MASK |
  774. OMAP3430_GRPSEL_GPIO6_MASK |
  775. OMAP3430_GRPSEL_UART3_MASK |
  776. OMAP3430_GRPSEL_MCBSP2_MASK |
  777. OMAP3430_GRPSEL_MCBSP3_MASK |
  778. OMAP3430_GRPSEL_MCBSP4_MASK,
  779. OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
  780. /* Don't attach IVA interrupts */
  781. prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
  782. prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
  783. prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
  784. prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
  785. /* Clear any pending 'reset' flags */
  786. prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
  787. prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
  788. prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
  789. prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
  790. prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
  791. prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
  792. prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
  793. /* Clear any pending PRCM interrupts */
  794. prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
  795. omap3_iva_idle();
  796. omap3_d2d_idle();
  797. }
  798. void omap3_pm_off_mode_enable(int enable)
  799. {
  800. struct power_state *pwrst;
  801. u32 state;
  802. if (enable)
  803. state = PWRDM_POWER_OFF;
  804. else
  805. state = PWRDM_POWER_RET;
  806. #ifdef CONFIG_CPU_IDLE
  807. omap3_cpuidle_update_states();
  808. #endif
  809. list_for_each_entry(pwrst, &pwrst_list, node) {
  810. pwrst->next_state = state;
  811. omap_set_pwrdm_state(pwrst->pwrdm, state);
  812. }
  813. }
  814. int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
  815. {
  816. struct power_state *pwrst;
  817. list_for_each_entry(pwrst, &pwrst_list, node) {
  818. if (pwrst->pwrdm == pwrdm)
  819. return pwrst->next_state;
  820. }
  821. return -EINVAL;
  822. }
  823. int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
  824. {
  825. struct power_state *pwrst;
  826. list_for_each_entry(pwrst, &pwrst_list, node) {
  827. if (pwrst->pwrdm == pwrdm) {
  828. pwrst->next_state = state;
  829. return 0;
  830. }
  831. }
  832. return -EINVAL;
  833. }
  834. static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  835. {
  836. struct power_state *pwrst;
  837. if (!pwrdm->pwrsts)
  838. return 0;
  839. pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
  840. if (!pwrst)
  841. return -ENOMEM;
  842. pwrst->pwrdm = pwrdm;
  843. pwrst->next_state = PWRDM_POWER_RET;
  844. list_add(&pwrst->node, &pwrst_list);
  845. if (pwrdm_has_hdwr_sar(pwrdm))
  846. pwrdm_enable_hdwr_sar(pwrdm);
  847. return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
  848. }
  849. /*
  850. * Enable hw supervised mode for all clockdomains if it's
  851. * supported. Initiate sleep transition for other clockdomains, if
  852. * they are not used
  853. */
  854. static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
  855. {
  856. if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
  857. omap2_clkdm_allow_idle(clkdm);
  858. else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
  859. atomic_read(&clkdm->usecount) == 0)
  860. omap2_clkdm_sleep(clkdm);
  861. return 0;
  862. }
  863. void omap_push_sram_idle(void)
  864. {
  865. _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
  866. omap34xx_cpu_suspend_sz);
  867. if (omap_type() != OMAP2_DEVICE_TYPE_GP)
  868. _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
  869. save_secure_ram_context_sz);
  870. }
  871. static int __init omap3_pm_init(void)
  872. {
  873. struct power_state *pwrst, *tmp;
  874. struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
  875. int ret;
  876. if (!cpu_is_omap34xx())
  877. return -ENODEV;
  878. printk(KERN_ERR "Power Management for TI OMAP3.\n");
  879. /* XXX prcm_setup_regs needs to be before enabling hw
  880. * supervised mode for powerdomains */
  881. prcm_setup_regs();
  882. ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
  883. (irq_handler_t)prcm_interrupt_handler,
  884. IRQF_DISABLED, "prcm", NULL);
  885. if (ret) {
  886. printk(KERN_ERR "request_irq failed to register for 0x%x\n",
  887. INT_34XX_PRCM_MPU_IRQ);
  888. goto err1;
  889. }
  890. ret = pwrdm_for_each(pwrdms_setup, NULL);
  891. if (ret) {
  892. printk(KERN_ERR "Failed to setup powerdomains\n");
  893. goto err2;
  894. }
  895. (void) clkdm_for_each(clkdms_setup, NULL);
  896. mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
  897. if (mpu_pwrdm == NULL) {
  898. printk(KERN_ERR "Failed to get mpu_pwrdm\n");
  899. goto err2;
  900. }
  901. neon_pwrdm = pwrdm_lookup("neon_pwrdm");
  902. per_pwrdm = pwrdm_lookup("per_pwrdm");
  903. core_pwrdm = pwrdm_lookup("core_pwrdm");
  904. cam_pwrdm = pwrdm_lookup("cam_pwrdm");
  905. neon_clkdm = clkdm_lookup("neon_clkdm");
  906. mpu_clkdm = clkdm_lookup("mpu_clkdm");
  907. per_clkdm = clkdm_lookup("per_clkdm");
  908. core_clkdm = clkdm_lookup("core_clkdm");
  909. omap_push_sram_idle();
  910. #ifdef CONFIG_SUSPEND
  911. suspend_set_ops(&omap_pm_ops);
  912. #endif /* CONFIG_SUSPEND */
  913. pm_idle = omap3_pm_idle;
  914. omap3_idle_init();
  915. clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
  916. if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
  917. omap3_secure_ram_storage =
  918. kmalloc(0x803F, GFP_KERNEL);
  919. if (!omap3_secure_ram_storage)
  920. printk(KERN_ERR "Memory allocation failed when"
  921. "allocating for secure sram context\n");
  922. local_irq_disable();
  923. local_fiq_disable();
  924. omap_dma_global_context_save();
  925. omap3_save_secure_ram_context(PWRDM_POWER_ON);
  926. omap_dma_global_context_restore();
  927. local_irq_enable();
  928. local_fiq_enable();
  929. }
  930. omap3_save_scratchpad_contents();
  931. err1:
  932. return ret;
  933. err2:
  934. free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
  935. list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
  936. list_del(&pwrst->node);
  937. kfree(pwrst);
  938. }
  939. return ret;
  940. }
  941. late_initcall(omap3_pm_init);