head.S 11 KB

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  1. /*
  2. * linux/arch/arm/kernel/head.S
  3. *
  4. * Copyright (C) 1994-2002 Russell King
  5. * Copyright (c) 2003 ARM Limited
  6. * All Rights Reserved
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Kernel startup code for all 32-bit CPUs
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/init.h>
  16. #include <asm/assembler.h>
  17. #include <asm/domain.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/asm-offsets.h>
  20. #include <asm/memory.h>
  21. #include <asm/thread_info.h>
  22. #include <asm/system.h>
  23. #ifdef CONFIG_DEBUG_LL
  24. #include <mach/debug-macro.S>
  25. #endif
  26. #if (PHYS_OFFSET & 0x001fffff)
  27. #error "PHYS_OFFSET must be at an even 2MiB boundary!"
  28. #endif
  29. #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
  30. #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
  31. /*
  32. * swapper_pg_dir is the virtual address of the initial page table.
  33. * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
  34. * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
  35. * the least significant 16 bits to be 0x8000, but we could probably
  36. * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
  37. */
  38. #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  39. #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  40. #endif
  41. .globl swapper_pg_dir
  42. .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
  43. .macro pgtbl, rd
  44. ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
  45. .endm
  46. #ifdef CONFIG_XIP_KERNEL
  47. #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
  48. #define KERNEL_END _edata_loc
  49. #else
  50. #define KERNEL_START KERNEL_RAM_VADDR
  51. #define KERNEL_END _end
  52. #endif
  53. /*
  54. * Kernel startup entry point.
  55. * ---------------------------
  56. *
  57. * This is normally called from the decompressor code. The requirements
  58. * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  59. * r1 = machine nr, r2 = atags pointer.
  60. *
  61. * This code is mostly position independent, so if you link the kernel at
  62. * 0xc0008000, you call this at __pa(0xc0008000).
  63. *
  64. * See linux/arch/arm/tools/mach-types for the complete list of machine
  65. * numbers for r1.
  66. *
  67. * We're trying to keep crap to a minimum; DO NOT add any machine specific
  68. * crap here - that's what the boot loader (or in extreme, well justified
  69. * circumstances, zImage) is for.
  70. */
  71. __HEAD
  72. ENTRY(stext)
  73. setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
  74. @ and irqs disabled
  75. mrc p15, 0, r9, c0, c0 @ get processor id
  76. bl __lookup_processor_type @ r5=procinfo r9=cpuid
  77. movs r10, r5 @ invalid processor (r5=0)?
  78. THUMB( it eq ) @ force fixup-able long branch encoding
  79. beq __error_p @ yes, error 'p'
  80. bl __lookup_machine_type @ r5=machinfo
  81. movs r8, r5 @ invalid machine (r5=0)?
  82. THUMB( it eq ) @ force fixup-able long branch encoding
  83. beq __error_a @ yes, error 'a'
  84. bl __vet_atags
  85. #ifdef CONFIG_SMP_ON_UP
  86. bl __fixup_smp
  87. #endif
  88. bl __create_page_tables
  89. /*
  90. * The following calls CPU specific code in a position independent
  91. * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
  92. * xxx_proc_info structure selected by __lookup_machine_type
  93. * above. On return, the CPU will be ready for the MMU to be
  94. * turned on, and r0 will hold the CPU control register value.
  95. */
  96. ldr r13, =__mmap_switched @ address to jump to after
  97. @ mmu has been enabled
  98. adr lr, BSYM(1f) @ return (PIC) address
  99. ARM( add pc, r10, #PROCINFO_INITFUNC )
  100. THUMB( add r12, r10, #PROCINFO_INITFUNC )
  101. THUMB( mov pc, r12 )
  102. 1: b __enable_mmu
  103. ENDPROC(stext)
  104. .ltorg
  105. /*
  106. * Setup the initial page tables. We only setup the barest
  107. * amount which are required to get the kernel running, which
  108. * generally means mapping in the kernel code.
  109. *
  110. * r8 = machinfo
  111. * r9 = cpuid
  112. * r10 = procinfo
  113. *
  114. * Returns:
  115. * r0, r3, r5-r7 corrupted
  116. * r4 = physical page table address
  117. */
  118. __create_page_tables:
  119. pgtbl r4 @ page table address
  120. /*
  121. * Clear the 16K level 1 swapper page table
  122. */
  123. mov r0, r4
  124. mov r3, #0
  125. add r6, r0, #0x4000
  126. 1: str r3, [r0], #4
  127. str r3, [r0], #4
  128. str r3, [r0], #4
  129. str r3, [r0], #4
  130. teq r0, r6
  131. bne 1b
  132. ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
  133. /*
  134. * Create identity mapping to cater for __enable_mmu.
  135. * This identity mapping will be removed by paging_init().
  136. */
  137. adr r0, __enable_mmu_loc
  138. ldmia r0, {r3, r5, r6}
  139. sub r0, r0, r3 @ virt->phys offset
  140. add r5, r5, r0 @ phys __enable_mmu
  141. add r6, r6, r0 @ phys __enable_mmu_end
  142. mov r5, r5, lsr #20
  143. mov r6, r6, lsr #20
  144. 1: orr r3, r7, r5, lsl #20 @ flags + kernel base
  145. str r3, [r4, r5, lsl #2] @ identity mapping
  146. teq r5, r6
  147. addne r5, r5, #1 @ next section
  148. bne 1b
  149. /*
  150. * Now setup the pagetables for our kernel direct
  151. * mapped region.
  152. */
  153. mov r3, pc
  154. mov r3, r3, lsr #20
  155. orr r3, r7, r3, lsl #20
  156. add r0, r4, #(KERNEL_START & 0xff000000) >> 18
  157. str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
  158. ldr r6, =(KERNEL_END - 1)
  159. add r0, r0, #4
  160. add r6, r4, r6, lsr #18
  161. 1: cmp r0, r6
  162. add r3, r3, #1 << 20
  163. strls r3, [r0], #4
  164. bls 1b
  165. #ifdef CONFIG_XIP_KERNEL
  166. /*
  167. * Map some ram to cover our .data and .bss areas.
  168. */
  169. orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
  170. .if (KERNEL_RAM_PADDR & 0x00f00000)
  171. orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
  172. .endif
  173. add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
  174. str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
  175. ldr r6, =(_end - 1)
  176. add r0, r0, #4
  177. add r6, r4, r6, lsr #18
  178. 1: cmp r0, r6
  179. add r3, r3, #1 << 20
  180. strls r3, [r0], #4
  181. bls 1b
  182. #endif
  183. /*
  184. * Then map first 1MB of ram in case it contains our boot params.
  185. */
  186. add r0, r4, #PAGE_OFFSET >> 18
  187. orr r6, r7, #(PHYS_OFFSET & 0xff000000)
  188. .if (PHYS_OFFSET & 0x00f00000)
  189. orr r6, r6, #(PHYS_OFFSET & 0x00f00000)
  190. .endif
  191. str r6, [r0]
  192. #ifdef CONFIG_DEBUG_LL
  193. #ifndef CONFIG_DEBUG_ICEDCC
  194. /*
  195. * Map in IO space for serial debugging.
  196. * This allows debug messages to be output
  197. * via a serial console before paging_init.
  198. */
  199. addruart r7, r3
  200. mov r3, r3, lsr #20
  201. mov r3, r3, lsl #2
  202. add r0, r4, r3
  203. rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
  204. cmp r3, #0x0800 @ limit to 512MB
  205. movhi r3, #0x0800
  206. add r6, r0, r3
  207. mov r3, r7, lsr #20
  208. ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
  209. orr r3, r7, r3, lsl #20
  210. 1: str r3, [r0], #4
  211. add r3, r3, #1 << 20
  212. teq r0, r6
  213. bne 1b
  214. #else /* CONFIG_DEBUG_ICEDCC */
  215. /* we don't need any serial debugging mappings for ICEDCC */
  216. ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
  217. #endif /* !CONFIG_DEBUG_ICEDCC */
  218. #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
  219. /*
  220. * If we're using the NetWinder or CATS, we also need to map
  221. * in the 16550-type serial port for the debug messages
  222. */
  223. add r0, r4, #0xff000000 >> 18
  224. orr r3, r7, #0x7c000000
  225. str r3, [r0]
  226. #endif
  227. #ifdef CONFIG_ARCH_RPC
  228. /*
  229. * Map in screen at 0x02000000 & SCREEN2_BASE
  230. * Similar reasons here - for debug. This is
  231. * only for Acorn RiscPC architectures.
  232. */
  233. add r0, r4, #0x02000000 >> 18
  234. orr r3, r7, #0x02000000
  235. str r3, [r0]
  236. add r0, r4, #0xd8000000 >> 18
  237. str r3, [r0]
  238. #endif
  239. #endif
  240. mov pc, lr
  241. ENDPROC(__create_page_tables)
  242. .ltorg
  243. .align
  244. __enable_mmu_loc:
  245. .long .
  246. .long __enable_mmu
  247. .long __enable_mmu_end
  248. #if defined(CONFIG_SMP)
  249. __CPUINIT
  250. ENTRY(secondary_startup)
  251. /*
  252. * Common entry point for secondary CPUs.
  253. *
  254. * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
  255. * the processor type - there is no need to check the machine type
  256. * as it has already been validated by the primary processor.
  257. */
  258. setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
  259. mrc p15, 0, r9, c0, c0 @ get processor id
  260. bl __lookup_processor_type
  261. movs r10, r5 @ invalid processor?
  262. moveq r0, #'p' @ yes, error 'p'
  263. THUMB( it eq ) @ force fixup-able long branch encoding
  264. beq __error_p
  265. /*
  266. * Use the page tables supplied from __cpu_up.
  267. */
  268. adr r4, __secondary_data
  269. ldmia r4, {r5, r7, r12} @ address to jump to after
  270. sub r4, r4, r5 @ mmu has been enabled
  271. ldr r4, [r7, r4] @ get secondary_data.pgdir
  272. adr lr, BSYM(__enable_mmu) @ return address
  273. mov r13, r12 @ __secondary_switched address
  274. ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
  275. @ (return control reg)
  276. THUMB( add r12, r10, #PROCINFO_INITFUNC )
  277. THUMB( mov pc, r12 )
  278. ENDPROC(secondary_startup)
  279. /*
  280. * r6 = &secondary_data
  281. */
  282. ENTRY(__secondary_switched)
  283. ldr sp, [r7, #4] @ get secondary_data.stack
  284. mov fp, #0
  285. b secondary_start_kernel
  286. ENDPROC(__secondary_switched)
  287. .align
  288. .type __secondary_data, %object
  289. __secondary_data:
  290. .long .
  291. .long secondary_data
  292. .long __secondary_switched
  293. #endif /* defined(CONFIG_SMP) */
  294. /*
  295. * Setup common bits before finally enabling the MMU. Essentially
  296. * this is just loading the page table pointer and domain access
  297. * registers.
  298. *
  299. * r0 = cp#15 control register
  300. * r1 = machine ID
  301. * r2 = atags pointer
  302. * r4 = page table pointer
  303. * r9 = processor ID
  304. * r13 = *virtual* address to jump to upon completion
  305. */
  306. __enable_mmu:
  307. #ifdef CONFIG_ALIGNMENT_TRAP
  308. orr r0, r0, #CR_A
  309. #else
  310. bic r0, r0, #CR_A
  311. #endif
  312. #ifdef CONFIG_CPU_DCACHE_DISABLE
  313. bic r0, r0, #CR_C
  314. #endif
  315. #ifdef CONFIG_CPU_BPREDICT_DISABLE
  316. bic r0, r0, #CR_Z
  317. #endif
  318. #ifdef CONFIG_CPU_ICACHE_DISABLE
  319. bic r0, r0, #CR_I
  320. #endif
  321. mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
  322. domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
  323. domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
  324. domain_val(DOMAIN_IO, DOMAIN_CLIENT))
  325. mcr p15, 0, r5, c3, c0, 0 @ load domain access register
  326. mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
  327. b __turn_mmu_on
  328. ENDPROC(__enable_mmu)
  329. /*
  330. * Enable the MMU. This completely changes the structure of the visible
  331. * memory space. You will not be able to trace execution through this.
  332. * If you have an enquiry about this, *please* check the linux-arm-kernel
  333. * mailing list archives BEFORE sending another post to the list.
  334. *
  335. * r0 = cp#15 control register
  336. * r1 = machine ID
  337. * r2 = atags pointer
  338. * r9 = processor ID
  339. * r13 = *virtual* address to jump to upon completion
  340. *
  341. * other registers depend on the function called upon completion
  342. */
  343. .align 5
  344. __turn_mmu_on:
  345. mov r0, r0
  346. mcr p15, 0, r0, c1, c0, 0 @ write control reg
  347. mrc p15, 0, r3, c0, c0, 0 @ read id reg
  348. mov r3, r3
  349. mov r3, r13
  350. mov pc, r3
  351. __enable_mmu_end:
  352. ENDPROC(__turn_mmu_on)
  353. #ifdef CONFIG_SMP_ON_UP
  354. __fixup_smp:
  355. mov r7, #0x00070000
  356. orr r6, r7, #0xff000000 @ mask 0xff070000
  357. orr r7, r7, #0x41000000 @ val 0x41070000
  358. and r0, r9, r6
  359. teq r0, r7 @ ARM CPU and ARMv6/v7?
  360. bne __fixup_smp_on_up @ no, assume UP
  361. orr r6, r6, #0x0000ff00
  362. orr r6, r6, #0x000000f0 @ mask 0xff07fff0
  363. orr r7, r7, #0x0000b000
  364. orr r7, r7, #0x00000020 @ val 0x4107b020
  365. and r0, r9, r6
  366. teq r0, r7 @ ARM 11MPCore?
  367. moveq pc, lr @ yes, assume SMP
  368. mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
  369. tst r0, #1 << 31
  370. movne pc, lr @ bit 31 => SMP
  371. __fixup_smp_on_up:
  372. adr r0, 1f
  373. ldmia r0, {r3, r6, r7}
  374. sub r3, r0, r3
  375. add r6, r6, r3
  376. add r7, r7, r3
  377. 2: cmp r6, r7
  378. ldmia r6!, {r0, r4}
  379. strlo r4, [r0, r3]
  380. blo 2b
  381. mov pc, lr
  382. ENDPROC(__fixup_smp)
  383. .align
  384. 1: .word .
  385. .word __smpalt_begin
  386. .word __smpalt_end
  387. .pushsection .data
  388. .globl smp_on_up
  389. smp_on_up:
  390. ALT_SMP(.long 1)
  391. ALT_UP(.long 0)
  392. .popsection
  393. #endif
  394. #include "head-common.S"