sh_mipi_dsi.c 14 KB

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  1. /*
  2. * Renesas SH-mobile MIPI DSI support
  3. *
  4. * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. *
  6. * This is free software; you can redistribute it and/or modify
  7. * it under the terms of version 2 of the GNU General Public License as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/slab.h>
  17. #include <linux/string.h>
  18. #include <linux/types.h>
  19. #include <video/mipi_display.h>
  20. #include <video/sh_mipi_dsi.h>
  21. #include <video/sh_mobile_lcdc.h>
  22. #define SYSCTRL 0x0000
  23. #define SYSCONF 0x0004
  24. #define TIMSET 0x0008
  25. #define RESREQSET0 0x0018
  26. #define RESREQSET1 0x001c
  27. #define HSTTOVSET 0x0020
  28. #define LPRTOVSET 0x0024
  29. #define TATOVSET 0x0028
  30. #define PRTOVSET 0x002c
  31. #define DSICTRL 0x0030
  32. #define DSIINTE 0x0060
  33. #define PHYCTRL 0x0070
  34. /* relative to linkbase */
  35. #define DTCTR 0x0000
  36. #define VMCTR1 0x0020
  37. #define VMCTR2 0x0024
  38. #define VMLEN1 0x0028
  39. #define CMTSRTREQ 0x0070
  40. #define CMTSRTCTR 0x00d0
  41. /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
  42. #define MAX_SH_MIPI_DSI 2
  43. struct sh_mipi {
  44. void __iomem *base;
  45. void __iomem *linkbase;
  46. struct clk *dsit_clk;
  47. struct clk *dsip_clk;
  48. struct device *dev;
  49. void *next_board_data;
  50. void (*next_display_on)(void *board_data, struct fb_info *info);
  51. void (*next_display_off)(void *board_data);
  52. };
  53. static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
  54. /* Protect the above array */
  55. static DEFINE_MUTEX(array_lock);
  56. static struct sh_mipi *sh_mipi_by_handle(int handle)
  57. {
  58. if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
  59. return NULL;
  60. return mipi_dsi[handle];
  61. }
  62. static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
  63. u8 cmd, u8 param)
  64. {
  65. u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
  66. int cnt = 100;
  67. /* transmit a short packet to LCD panel */
  68. iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
  69. iowrite32(1, mipi->linkbase + CMTSRTREQ);
  70. while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
  71. udelay(1);
  72. return cnt ? 0 : -ETIMEDOUT;
  73. }
  74. #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
  75. -EINVAL : (c) - 1)
  76. static int sh_mipi_dcs(int handle, u8 cmd)
  77. {
  78. struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
  79. if (!mipi)
  80. return -ENODEV;
  81. return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
  82. }
  83. static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
  84. {
  85. struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
  86. if (!mipi)
  87. return -ENODEV;
  88. return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
  89. param);
  90. }
  91. static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
  92. {
  93. /*
  94. * enable LCDC data tx, transition to LPS after completion of each HS
  95. * packet
  96. */
  97. iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
  98. }
  99. static void sh_mipi_shutdown(struct platform_device *pdev)
  100. {
  101. struct sh_mipi *mipi = platform_get_drvdata(pdev);
  102. sh_mipi_dsi_enable(mipi, false);
  103. }
  104. static void mipi_display_on(void *arg, struct fb_info *info)
  105. {
  106. struct sh_mipi *mipi = arg;
  107. pm_runtime_get_sync(mipi->dev);
  108. sh_mipi_dsi_enable(mipi, true);
  109. if (mipi->next_display_on)
  110. mipi->next_display_on(mipi->next_board_data, info);
  111. }
  112. static void mipi_display_off(void *arg)
  113. {
  114. struct sh_mipi *mipi = arg;
  115. if (mipi->next_display_off)
  116. mipi->next_display_off(mipi->next_board_data);
  117. sh_mipi_dsi_enable(mipi, false);
  118. pm_runtime_put(mipi->dev);
  119. }
  120. static int __init sh_mipi_setup(struct sh_mipi *mipi,
  121. struct sh_mipi_dsi_info *pdata)
  122. {
  123. void __iomem *base = mipi->base;
  124. struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
  125. u32 pctype, datatype, pixfmt;
  126. u32 linelength;
  127. bool yuv;
  128. /*
  129. * Select data format. MIPI DSI is not hot-pluggable, so, we just use
  130. * the default videomode. If this ever becomes a problem, We'll have to
  131. * move this to mipi_display_on() above and use info->var.xres
  132. */
  133. switch (pdata->data_format) {
  134. case MIPI_RGB888:
  135. pctype = 0;
  136. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  137. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  138. linelength = ch->lcd_cfg[0].xres * 3;
  139. yuv = false;
  140. break;
  141. case MIPI_RGB565:
  142. pctype = 1;
  143. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  144. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  145. linelength = ch->lcd_cfg[0].xres * 2;
  146. yuv = false;
  147. break;
  148. case MIPI_RGB666_LP:
  149. pctype = 2;
  150. datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  151. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  152. linelength = ch->lcd_cfg[0].xres * 3;
  153. yuv = false;
  154. break;
  155. case MIPI_RGB666:
  156. pctype = 3;
  157. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  158. pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
  159. linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
  160. yuv = false;
  161. break;
  162. case MIPI_BGR888:
  163. pctype = 8;
  164. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  165. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  166. linelength = ch->lcd_cfg[0].xres * 3;
  167. yuv = false;
  168. break;
  169. case MIPI_BGR565:
  170. pctype = 9;
  171. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  172. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  173. linelength = ch->lcd_cfg[0].xres * 2;
  174. yuv = false;
  175. break;
  176. case MIPI_BGR666_LP:
  177. pctype = 0xa;
  178. datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  179. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  180. linelength = ch->lcd_cfg[0].xres * 3;
  181. yuv = false;
  182. break;
  183. case MIPI_BGR666:
  184. pctype = 0xb;
  185. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  186. pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
  187. linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
  188. yuv = false;
  189. break;
  190. case MIPI_YUYV:
  191. pctype = 4;
  192. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
  193. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  194. linelength = ch->lcd_cfg[0].xres * 2;
  195. yuv = true;
  196. break;
  197. case MIPI_UYVY:
  198. pctype = 5;
  199. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
  200. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  201. linelength = ch->lcd_cfg[0].xres * 2;
  202. yuv = true;
  203. break;
  204. case MIPI_YUV420_L:
  205. pctype = 6;
  206. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
  207. pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
  208. linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
  209. yuv = true;
  210. break;
  211. case MIPI_YUV420:
  212. pctype = 7;
  213. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
  214. pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
  215. /* Length of U/V line */
  216. linelength = (ch->lcd_cfg[0].xres + 1) / 2;
  217. yuv = true;
  218. break;
  219. default:
  220. return -EINVAL;
  221. }
  222. if ((yuv && ch->interface_type != YUV422) ||
  223. (!yuv && ch->interface_type != RGB24))
  224. return -EINVAL;
  225. /* reset DSI link */
  226. iowrite32(0x00000001, base + SYSCTRL);
  227. /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
  228. udelay(50);
  229. iowrite32(0x00000000, base + SYSCTRL);
  230. /* setup DSI link */
  231. /*
  232. * Default = ULPS enable |
  233. * Contention detection enabled |
  234. * EoT packet transmission enable |
  235. * CRC check enable |
  236. * ECC check enable
  237. * additionally enable first two lanes
  238. */
  239. iowrite32(0x00003703, base + SYSCONF);
  240. /*
  241. * T_wakeup = 0x7000
  242. * T_hs-trail = 3
  243. * T_hs-prepare = 3
  244. * T_clk-trail = 3
  245. * T_clk-prepare = 2
  246. */
  247. iowrite32(0x70003332, base + TIMSET);
  248. /* no responses requested */
  249. iowrite32(0x00000000, base + RESREQSET0);
  250. /* request response to packets of type 0x28 */
  251. iowrite32(0x00000100, base + RESREQSET1);
  252. /* High-speed transmission timeout, default 0xffffffff */
  253. iowrite32(0x0fffffff, base + HSTTOVSET);
  254. /* LP reception timeout, default 0xffffffff */
  255. iowrite32(0x0fffffff, base + LPRTOVSET);
  256. /* Turn-around timeout, default 0xffffffff */
  257. iowrite32(0x0fffffff, base + TATOVSET);
  258. /* Peripheral reset timeout, default 0xffffffff */
  259. iowrite32(0x0fffffff, base + PRTOVSET);
  260. /* Enable timeout counters */
  261. iowrite32(0x00000f00, base + DSICTRL);
  262. /* Interrupts not used, disable all */
  263. iowrite32(0, base + DSIINTE);
  264. /* DSI-Tx bias on */
  265. iowrite32(0x00000001, base + PHYCTRL);
  266. udelay(200);
  267. /* Deassert resets, power on, set multiplier */
  268. iowrite32(0x03070b01, base + PHYCTRL);
  269. /* setup l-bridge */
  270. /*
  271. * Enable transmission of all packets,
  272. * transmit LPS after each HS packet completion
  273. */
  274. iowrite32(0x00000006, mipi->linkbase + DTCTR);
  275. /* VSYNC width = 2 (<< 17) */
  276. iowrite32(0x00040000 | (pctype << 12) | datatype,
  277. mipi->linkbase + VMCTR1);
  278. /*
  279. * Non-burst mode with sync pulses: VSE and HSE are output,
  280. * HSA period allowed, no commands in LP
  281. */
  282. iowrite32(0x00e00000, mipi->linkbase + VMCTR2);
  283. /*
  284. * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
  285. * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
  286. * (unused, since VMCTR2[HSABM] = 0)
  287. */
  288. iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);
  289. msleep(5);
  290. /* setup LCD panel */
  291. /* cf. drivers/video/omap/lcd_mipid.c */
  292. sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
  293. msleep(120);
  294. /*
  295. * [7] - Page Address Mode
  296. * [6] - Column Address Mode
  297. * [5] - Page / Column Address Mode
  298. * [4] - Display Device Line Refresh Order
  299. * [3] - RGB/BGR Order
  300. * [2] - Display Data Latch Data Order
  301. * [1] - Flip Horizontal
  302. * [0] - Flip Vertical
  303. */
  304. sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
  305. /* cf. set_data_lines() */
  306. sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
  307. pixfmt << 4);
  308. sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
  309. return 0;
  310. }
  311. static int __init sh_mipi_probe(struct platform_device *pdev)
  312. {
  313. struct sh_mipi *mipi;
  314. struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
  315. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  316. struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  317. unsigned long rate, f_current;
  318. int idx = pdev->id, ret;
  319. char dsip_clk[] = "dsi.p_clk";
  320. if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
  321. return -ENODEV;
  322. mutex_lock(&array_lock);
  323. if (idx < 0)
  324. for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
  325. ;
  326. if (idx == ARRAY_SIZE(mipi_dsi)) {
  327. ret = -EBUSY;
  328. goto efindslot;
  329. }
  330. mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
  331. if (!mipi) {
  332. ret = -ENOMEM;
  333. goto ealloc;
  334. }
  335. if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
  336. dev_err(&pdev->dev, "MIPI register region already claimed\n");
  337. ret = -EBUSY;
  338. goto ereqreg;
  339. }
  340. mipi->base = ioremap(res->start, resource_size(res));
  341. if (!mipi->base) {
  342. ret = -ENOMEM;
  343. goto emap;
  344. }
  345. if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
  346. dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
  347. ret = -EBUSY;
  348. goto ereqreg2;
  349. }
  350. mipi->linkbase = ioremap(res2->start, resource_size(res2));
  351. if (!mipi->linkbase) {
  352. ret = -ENOMEM;
  353. goto emap2;
  354. }
  355. mipi->dev = &pdev->dev;
  356. mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
  357. if (IS_ERR(mipi->dsit_clk)) {
  358. ret = PTR_ERR(mipi->dsit_clk);
  359. goto eclktget;
  360. }
  361. f_current = clk_get_rate(mipi->dsit_clk);
  362. /* 80MHz required by the datasheet */
  363. rate = clk_round_rate(mipi->dsit_clk, 80000000);
  364. if (rate > 0 && rate != f_current)
  365. ret = clk_set_rate(mipi->dsit_clk, rate);
  366. else
  367. ret = rate;
  368. if (ret < 0)
  369. goto esettrate;
  370. dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
  371. sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
  372. mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
  373. if (IS_ERR(mipi->dsip_clk)) {
  374. ret = PTR_ERR(mipi->dsip_clk);
  375. goto eclkpget;
  376. }
  377. f_current = clk_get_rate(mipi->dsip_clk);
  378. /* Between 10 and 50MHz */
  379. rate = clk_round_rate(mipi->dsip_clk, 24000000);
  380. if (rate > 0 && rate != f_current)
  381. ret = clk_set_rate(mipi->dsip_clk, rate);
  382. else
  383. ret = rate;
  384. if (ret < 0)
  385. goto esetprate;
  386. dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
  387. msleep(10);
  388. ret = clk_enable(mipi->dsit_clk);
  389. if (ret < 0)
  390. goto eclkton;
  391. ret = clk_enable(mipi->dsip_clk);
  392. if (ret < 0)
  393. goto eclkpon;
  394. mipi_dsi[idx] = mipi;
  395. pm_runtime_enable(&pdev->dev);
  396. pm_runtime_resume(&pdev->dev);
  397. ret = sh_mipi_setup(mipi, pdata);
  398. if (ret < 0)
  399. goto emipisetup;
  400. mutex_unlock(&array_lock);
  401. platform_set_drvdata(pdev, mipi);
  402. /* Save original LCDC callbacks */
  403. mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
  404. mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
  405. mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
  406. /* Set up LCDC callbacks */
  407. pdata->lcd_chan->board_cfg.board_data = mipi;
  408. pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
  409. pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
  410. pdata->lcd_chan->board_cfg.owner = THIS_MODULE;
  411. return 0;
  412. emipisetup:
  413. mipi_dsi[idx] = NULL;
  414. pm_runtime_disable(&pdev->dev);
  415. clk_disable(mipi->dsip_clk);
  416. eclkpon:
  417. clk_disable(mipi->dsit_clk);
  418. eclkton:
  419. esetprate:
  420. clk_put(mipi->dsip_clk);
  421. eclkpget:
  422. esettrate:
  423. clk_put(mipi->dsit_clk);
  424. eclktget:
  425. iounmap(mipi->linkbase);
  426. emap2:
  427. release_mem_region(res2->start, resource_size(res2));
  428. ereqreg2:
  429. iounmap(mipi->base);
  430. emap:
  431. release_mem_region(res->start, resource_size(res));
  432. ereqreg:
  433. kfree(mipi);
  434. ealloc:
  435. efindslot:
  436. mutex_unlock(&array_lock);
  437. return ret;
  438. }
  439. static int __exit sh_mipi_remove(struct platform_device *pdev)
  440. {
  441. struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
  442. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  443. struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  444. struct sh_mipi *mipi = platform_get_drvdata(pdev);
  445. int i, ret;
  446. mutex_lock(&array_lock);
  447. for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
  448. ;
  449. if (i == ARRAY_SIZE(mipi_dsi)) {
  450. ret = -EINVAL;
  451. } else {
  452. ret = 0;
  453. mipi_dsi[i] = NULL;
  454. }
  455. mutex_unlock(&array_lock);
  456. if (ret < 0)
  457. return ret;
  458. pdata->lcd_chan->board_cfg.owner = NULL;
  459. pdata->lcd_chan->board_cfg.display_on = NULL;
  460. pdata->lcd_chan->board_cfg.display_off = NULL;
  461. pdata->lcd_chan->board_cfg.board_data = NULL;
  462. pm_runtime_disable(&pdev->dev);
  463. clk_disable(mipi->dsip_clk);
  464. clk_disable(mipi->dsit_clk);
  465. clk_put(mipi->dsit_clk);
  466. clk_put(mipi->dsip_clk);
  467. iounmap(mipi->linkbase);
  468. if (res2)
  469. release_mem_region(res2->start, resource_size(res2));
  470. iounmap(mipi->base);
  471. if (res)
  472. release_mem_region(res->start, resource_size(res));
  473. platform_set_drvdata(pdev, NULL);
  474. kfree(mipi);
  475. return 0;
  476. }
  477. static struct platform_driver sh_mipi_driver = {
  478. .remove = __exit_p(sh_mipi_remove),
  479. .shutdown = sh_mipi_shutdown,
  480. .driver = {
  481. .name = "sh-mipi-dsi",
  482. },
  483. };
  484. static int __init sh_mipi_init(void)
  485. {
  486. return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
  487. }
  488. module_init(sh_mipi_init);
  489. static void __exit sh_mipi_exit(void)
  490. {
  491. platform_driver_unregister(&sh_mipi_driver);
  492. }
  493. module_exit(sh_mipi_exit);
  494. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  495. MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
  496. MODULE_LICENSE("GPL v2");