cx23885-dvb.c 28 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "tda10048.h"
  39. #include "tuner-xc2028.h"
  40. #include "tuner-simple.h"
  41. #include "dib7000p.h"
  42. #include "dibx000_common.h"
  43. #include "zl10353.h"
  44. #include "stv0900.h"
  45. #include "stv0900_reg.h"
  46. #include "stv6110.h"
  47. #include "lnbh24.h"
  48. #include "cx24116.h"
  49. #include "cimax2.h"
  50. #include "lgs8gxx.h"
  51. #include "netup-eeprom.h"
  52. #include "netup-init.h"
  53. #include "lgdt3305.h"
  54. static unsigned int debug;
  55. #define dprintk(level, fmt, arg...)\
  56. do { if (debug >= level)\
  57. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  58. } while (0)
  59. /* ------------------------------------------------------------------ */
  60. static unsigned int alt_tuner;
  61. module_param(alt_tuner, int, 0644);
  62. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  63. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  64. /* ------------------------------------------------------------------ */
  65. static int dvb_buf_setup(struct videobuf_queue *q,
  66. unsigned int *count, unsigned int *size)
  67. {
  68. struct cx23885_tsport *port = q->priv_data;
  69. port->ts_packet_size = 188 * 4;
  70. port->ts_packet_count = 32;
  71. *size = port->ts_packet_size * port->ts_packet_count;
  72. *count = 32;
  73. return 0;
  74. }
  75. static int dvb_buf_prepare(struct videobuf_queue *q,
  76. struct videobuf_buffer *vb, enum v4l2_field field)
  77. {
  78. struct cx23885_tsport *port = q->priv_data;
  79. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  80. }
  81. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  85. }
  86. static void dvb_buf_release(struct videobuf_queue *q,
  87. struct videobuf_buffer *vb)
  88. {
  89. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  90. }
  91. static struct videobuf_queue_ops dvb_qops = {
  92. .buf_setup = dvb_buf_setup,
  93. .buf_prepare = dvb_buf_prepare,
  94. .buf_queue = dvb_buf_queue,
  95. .buf_release = dvb_buf_release,
  96. };
  97. static struct s5h1409_config hauppauge_generic_config = {
  98. .demod_address = 0x32 >> 1,
  99. .output_mode = S5H1409_SERIAL_OUTPUT,
  100. .gpio = S5H1409_GPIO_ON,
  101. .qam_if = 44000,
  102. .inversion = S5H1409_INVERSION_OFF,
  103. .status_mode = S5H1409_DEMODLOCKING,
  104. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  105. };
  106. static struct tda10048_config hauppauge_hvr1200_config = {
  107. .demod_address = 0x10 >> 1,
  108. .output_mode = TDA10048_SERIAL_OUTPUT,
  109. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  110. .inversion = TDA10048_INVERSION_ON,
  111. .dtv6_if_freq_khz = TDA10048_IF_3300,
  112. .dtv7_if_freq_khz = TDA10048_IF_3800,
  113. .dtv8_if_freq_khz = TDA10048_IF_4300,
  114. .clk_freq_khz = TDA10048_CLK_16000,
  115. };
  116. static struct tda10048_config hauppauge_hvr1210_config = {
  117. .demod_address = 0x10 >> 1,
  118. .output_mode = TDA10048_SERIAL_OUTPUT,
  119. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  120. .inversion = TDA10048_INVERSION_ON,
  121. .dtv6_if_freq_khz = TDA10048_IF_3300,
  122. .dtv7_if_freq_khz = TDA10048_IF_3500,
  123. .dtv8_if_freq_khz = TDA10048_IF_4000,
  124. .clk_freq_khz = TDA10048_CLK_16000,
  125. };
  126. static struct s5h1409_config hauppauge_ezqam_config = {
  127. .demod_address = 0x32 >> 1,
  128. .output_mode = S5H1409_SERIAL_OUTPUT,
  129. .gpio = S5H1409_GPIO_OFF,
  130. .qam_if = 4000,
  131. .inversion = S5H1409_INVERSION_ON,
  132. .status_mode = S5H1409_DEMODLOCKING,
  133. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  134. };
  135. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  136. .demod_address = 0x32 >> 1,
  137. .output_mode = S5H1409_SERIAL_OUTPUT,
  138. .gpio = S5H1409_GPIO_OFF,
  139. .qam_if = 44000,
  140. .inversion = S5H1409_INVERSION_OFF,
  141. .status_mode = S5H1409_DEMODLOCKING,
  142. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  143. };
  144. static struct s5h1409_config hauppauge_hvr1500_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .inversion = S5H1409_INVERSION_OFF,
  149. .status_mode = S5H1409_DEMODLOCKING,
  150. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  151. };
  152. static struct mt2131_config hauppauge_generic_tunerconfig = {
  153. 0x61
  154. };
  155. static struct lgdt330x_config fusionhdtv_5_express = {
  156. .demod_address = 0x0e,
  157. .demod_chip = LGDT3303,
  158. .serial_mpeg = 0x40,
  159. };
  160. static struct s5h1409_config hauppauge_hvr1500q_config = {
  161. .demod_address = 0x32 >> 1,
  162. .output_mode = S5H1409_SERIAL_OUTPUT,
  163. .gpio = S5H1409_GPIO_ON,
  164. .qam_if = 44000,
  165. .inversion = S5H1409_INVERSION_OFF,
  166. .status_mode = S5H1409_DEMODLOCKING,
  167. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  168. };
  169. static struct s5h1409_config dvico_s5h1409_config = {
  170. .demod_address = 0x32 >> 1,
  171. .output_mode = S5H1409_SERIAL_OUTPUT,
  172. .gpio = S5H1409_GPIO_ON,
  173. .qam_if = 44000,
  174. .inversion = S5H1409_INVERSION_OFF,
  175. .status_mode = S5H1409_DEMODLOCKING,
  176. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  177. };
  178. static struct s5h1411_config dvico_s5h1411_config = {
  179. .output_mode = S5H1411_SERIAL_OUTPUT,
  180. .gpio = S5H1411_GPIO_ON,
  181. .qam_if = S5H1411_IF_44000,
  182. .vsb_if = S5H1411_IF_44000,
  183. .inversion = S5H1411_INVERSION_OFF,
  184. .status_mode = S5H1411_DEMODLOCKING,
  185. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1411_config hcw_s5h1411_config = {
  188. .output_mode = S5H1411_SERIAL_OUTPUT,
  189. .gpio = S5H1411_GPIO_OFF,
  190. .vsb_if = S5H1411_IF_44000,
  191. .qam_if = S5H1411_IF_4000,
  192. .inversion = S5H1411_INVERSION_ON,
  193. .status_mode = S5H1411_DEMODLOCKING,
  194. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  197. .i2c_address = 0x61,
  198. .if_khz = 5380,
  199. };
  200. static struct xc5000_config dvico_xc5000_tunerconfig = {
  201. .i2c_address = 0x64,
  202. .if_khz = 5380,
  203. };
  204. static struct tda829x_config tda829x_no_probe = {
  205. .probe_tuner = TDA829X_DONT_PROBE,
  206. };
  207. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  208. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  209. .if_lvl = 6, .rfagc_top = 0x37 },
  210. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  211. .if_lvl = 6, .rfagc_top = 0x37 },
  212. };
  213. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  214. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  215. .if_lvl = 1, .rfagc_top = 0x37, },
  216. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  217. .if_lvl = 1, .rfagc_top = 0x37, },
  218. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  219. .if_lvl = 1, .rfagc_top = 0x37, },
  220. };
  221. static struct tda18271_config hauppauge_tda18271_config = {
  222. .std_map = &hauppauge_tda18271_std_map,
  223. .gate = TDA18271_GATE_ANALOG,
  224. };
  225. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  226. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  227. .gate = TDA18271_GATE_ANALOG,
  228. };
  229. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  230. .gate = TDA18271_GATE_DIGITAL,
  231. };
  232. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  233. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  234. .if_lvl = 1, .rfagc_top = 0x58 },
  235. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  236. .if_lvl = 1, .rfagc_top = 0x58 },
  237. };
  238. static struct tda18271_config hauppauge_hvr127x_config = {
  239. .std_map = &hauppauge_hvr127x_std_map,
  240. };
  241. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  242. .i2c_addr = 0x0e,
  243. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  244. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  245. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  246. .deny_i2c_rptr = 1,
  247. .spectral_inversion = 1,
  248. .qam_if_khz = 4000,
  249. .vsb_if_khz = 3250,
  250. };
  251. static struct dibx000_agc_config xc3028_agc_config = {
  252. BAND_VHF | BAND_UHF, /* band_caps */
  253. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  254. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  255. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  256. * P_agc_nb_est=2, P_agc_write=0
  257. */
  258. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  259. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  260. 712, /* inv_gain */
  261. 21, /* time_stabiliz */
  262. 0, /* alpha_level */
  263. 118, /* thlock */
  264. 0, /* wbd_inv */
  265. 2867, /* wbd_ref */
  266. 0, /* wbd_sel */
  267. 2, /* wbd_alpha */
  268. 0, /* agc1_max */
  269. 0, /* agc1_min */
  270. 39718, /* agc2_max */
  271. 9930, /* agc2_min */
  272. 0, /* agc1_pt1 */
  273. 0, /* agc1_pt2 */
  274. 0, /* agc1_pt3 */
  275. 0, /* agc1_slope1 */
  276. 0, /* agc1_slope2 */
  277. 0, /* agc2_pt1 */
  278. 128, /* agc2_pt2 */
  279. 29, /* agc2_slope1 */
  280. 29, /* agc2_slope2 */
  281. 17, /* alpha_mant */
  282. 27, /* alpha_exp */
  283. 23, /* beta_mant */
  284. 51, /* beta_exp */
  285. 1, /* perform_agc_softsplit */
  286. };
  287. /* PLL Configuration for COFDM BW_MHz = 8.000000
  288. * With external clock = 30.000000 */
  289. static struct dibx000_bandwidth_config xc3028_bw_config = {
  290. 60000, /* internal */
  291. 30000, /* sampling */
  292. 1, /* pll_cfg: prediv */
  293. 8, /* pll_cfg: ratio */
  294. 3, /* pll_cfg: range */
  295. 1, /* pll_cfg: reset */
  296. 0, /* pll_cfg: bypass */
  297. 0, /* misc: refdiv */
  298. 0, /* misc: bypclk_div */
  299. 1, /* misc: IO_CLK_en_core */
  300. 1, /* misc: ADClkSrc */
  301. 0, /* misc: modulo */
  302. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  303. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  304. 20452225, /* timf */
  305. 30000000 /* xtal_hz */
  306. };
  307. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  308. .output_mpeg2_in_188_bytes = 1,
  309. .hostbus_diversity = 1,
  310. .tuner_is_baseband = 0,
  311. .update_lna = NULL,
  312. .agc_config_count = 1,
  313. .agc = &xc3028_agc_config,
  314. .bw = &xc3028_bw_config,
  315. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  316. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  317. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  318. .pwm_freq_div = 0,
  319. .agc_control = NULL,
  320. .spur_protect = 0,
  321. .output_mode = OUTMODE_MPEG2_SERIAL,
  322. };
  323. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  324. .demod_address = 0x0f,
  325. .if2 = 45600,
  326. .no_tuner = 1,
  327. .disable_i2c_gate_ctrl = 1,
  328. };
  329. static struct stv0900_reg stv0900_ts_regs[] = {
  330. { R0900_TSGENERAL, 0x00 },
  331. { R0900_P1_TSSPEED, 0x40 },
  332. { R0900_P2_TSSPEED, 0x40 },
  333. { R0900_P1_TSCFGM, 0xc0 },
  334. { R0900_P2_TSCFGM, 0xc0 },
  335. { R0900_P1_TSCFGH, 0xe0 },
  336. { R0900_P2_TSCFGH, 0xe0 },
  337. { R0900_P1_TSCFGL, 0x20 },
  338. { R0900_P2_TSCFGL, 0x20 },
  339. { 0xffff, 0xff }, /* terminate */
  340. };
  341. static struct stv0900_config netup_stv0900_config = {
  342. .demod_address = 0x68,
  343. .xtal = 27000000,
  344. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  345. .diseqc_mode = 2,/* 2/3 PWM */
  346. .ts_config_regs = stv0900_ts_regs,
  347. .tun1_maddress = 0,/* 0x60 */
  348. .tun2_maddress = 3,/* 0x63 */
  349. .tun1_adc = 1,/* 1 Vpp */
  350. .tun2_adc = 1,/* 1 Vpp */
  351. };
  352. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  353. .i2c_address = 0x60,
  354. .mclk = 27000000,
  355. .iq_wiring = 0,
  356. };
  357. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  358. .i2c_address = 0x63,
  359. .mclk = 27000000,
  360. .iq_wiring = 1,
  361. };
  362. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  363. {
  364. struct cx23885_tsport *port = fe->dvb->priv;
  365. struct cx23885_dev *dev = port->dev;
  366. if (voltage == SEC_VOLTAGE_18)
  367. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  368. else if (voltage == SEC_VOLTAGE_13)
  369. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  370. else
  371. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  372. return 0;
  373. }
  374. static struct cx24116_config tbs_cx24116_config = {
  375. .demod_address = 0x05,
  376. };
  377. static struct cx24116_config tevii_cx24116_config = {
  378. .demod_address = 0x55,
  379. };
  380. static struct cx24116_config dvbworld_cx24116_config = {
  381. .demod_address = 0x05,
  382. };
  383. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  384. .prod = LGS8GXX_PROD_LGS8GL5,
  385. .demod_address = 0x19,
  386. .serial_ts = 0,
  387. .ts_clk_pol = 1,
  388. .ts_clk_gated = 1,
  389. .if_clk_freq = 30400, /* 30.4 MHz */
  390. .if_freq = 5380, /* 5.38 MHz */
  391. .if_neg_center = 1,
  392. .ext_adc = 0,
  393. .adc_signed = 0,
  394. .if_neg_edge = 0,
  395. };
  396. static struct xc5000_config mygica_x8506_xc5000_config = {
  397. .i2c_address = 0x61,
  398. .if_khz = 5380,
  399. };
  400. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  401. struct dvb_frontend_parameters *param)
  402. {
  403. struct cx23885_tsport *port = fe->dvb->priv;
  404. struct cx23885_dev *dev = port->dev;
  405. switch (dev->board) {
  406. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  407. switch (param->u.vsb.modulation) {
  408. case VSB_8:
  409. cx23885_gpio_clear(dev, GPIO_5);
  410. break;
  411. case QAM_64:
  412. case QAM_256:
  413. default:
  414. cx23885_gpio_set(dev, GPIO_5);
  415. break;
  416. }
  417. break;
  418. }
  419. return (port->set_frontend_save) ?
  420. port->set_frontend_save(fe, param) : -ENODEV;
  421. }
  422. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  423. .prod = LGS8GXX_PROD_LGS8G75,
  424. .demod_address = 0x19,
  425. .serial_ts = 0,
  426. .ts_clk_pol = 1,
  427. .ts_clk_gated = 1,
  428. .if_clk_freq = 30400, /* 30.4 MHz */
  429. .if_freq = 6500, /* 6.50 MHz */
  430. .if_neg_center = 1,
  431. .ext_adc = 0,
  432. .adc_signed = 1,
  433. .adc_vpp = 2, /* 1.6 Vpp */
  434. .if_neg_edge = 1,
  435. };
  436. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  437. .i2c_address = 0x61,
  438. .if_khz = 6500,
  439. };
  440. static int dvb_register(struct cx23885_tsport *port)
  441. {
  442. struct cx23885_dev *dev = port->dev;
  443. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  444. struct videobuf_dvb_frontend *fe0;
  445. int ret;
  446. /* Get the first frontend */
  447. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  448. if (!fe0)
  449. return -EINVAL;
  450. /* init struct videobuf_dvb */
  451. fe0->dvb.name = dev->name;
  452. /* init frontend */
  453. switch (dev->board) {
  454. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  455. i2c_bus = &dev->i2c_bus[0];
  456. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  457. &hauppauge_generic_config,
  458. &i2c_bus->i2c_adap);
  459. if (fe0->dvb.frontend != NULL) {
  460. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  461. &i2c_bus->i2c_adap,
  462. &hauppauge_generic_tunerconfig, 0);
  463. }
  464. break;
  465. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  466. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  467. i2c_bus = &dev->i2c_bus[0];
  468. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  469. &hauppauge_lgdt3305_config,
  470. &i2c_bus->i2c_adap);
  471. if (fe0->dvb.frontend != NULL) {
  472. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  473. 0x60, &dev->i2c_bus[1].i2c_adap,
  474. &hauppauge_hvr127x_config);
  475. }
  476. /* FIXME: temporary hack */
  477. /* define bridge override to set_frontend */
  478. port->set_frontend_save = fe0->dvb.frontend->ops.set_frontend;
  479. fe0->dvb.frontend->ops.set_frontend = cx23885_dvb_set_frontend;
  480. break;
  481. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  482. i2c_bus = &dev->i2c_bus[0];
  483. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  484. &hcw_s5h1411_config,
  485. &i2c_bus->i2c_adap);
  486. if (fe0->dvb.frontend != NULL) {
  487. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  488. 0x60, &dev->i2c_bus[1].i2c_adap,
  489. &hauppauge_tda18271_config);
  490. }
  491. break;
  492. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  493. i2c_bus = &dev->i2c_bus[0];
  494. switch (alt_tuner) {
  495. case 1:
  496. fe0->dvb.frontend =
  497. dvb_attach(s5h1409_attach,
  498. &hauppauge_ezqam_config,
  499. &i2c_bus->i2c_adap);
  500. if (fe0->dvb.frontend != NULL) {
  501. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  502. &dev->i2c_bus[1].i2c_adap, 0x42,
  503. &tda829x_no_probe);
  504. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  505. 0x60, &dev->i2c_bus[1].i2c_adap,
  506. &hauppauge_tda18271_config);
  507. }
  508. break;
  509. case 0:
  510. default:
  511. fe0->dvb.frontend =
  512. dvb_attach(s5h1409_attach,
  513. &hauppauge_generic_config,
  514. &i2c_bus->i2c_adap);
  515. if (fe0->dvb.frontend != NULL)
  516. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  517. &i2c_bus->i2c_adap,
  518. &hauppauge_generic_tunerconfig, 0);
  519. break;
  520. }
  521. break;
  522. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  523. i2c_bus = &dev->i2c_bus[0];
  524. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  525. &hauppauge_hvr1800lp_config,
  526. &i2c_bus->i2c_adap);
  527. if (fe0->dvb.frontend != NULL) {
  528. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  529. &i2c_bus->i2c_adap,
  530. &hauppauge_generic_tunerconfig, 0);
  531. }
  532. break;
  533. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  534. i2c_bus = &dev->i2c_bus[0];
  535. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  536. &fusionhdtv_5_express,
  537. &i2c_bus->i2c_adap);
  538. if (fe0->dvb.frontend != NULL) {
  539. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  540. &i2c_bus->i2c_adap, 0x61,
  541. TUNER_LG_TDVS_H06XF);
  542. }
  543. break;
  544. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  545. i2c_bus = &dev->i2c_bus[1];
  546. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  547. &hauppauge_hvr1500q_config,
  548. &dev->i2c_bus[0].i2c_adap);
  549. if (fe0->dvb.frontend != NULL)
  550. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  551. &i2c_bus->i2c_adap,
  552. &hauppauge_hvr1500q_tunerconfig);
  553. break;
  554. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  555. i2c_bus = &dev->i2c_bus[1];
  556. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  557. &hauppauge_hvr1500_config,
  558. &dev->i2c_bus[0].i2c_adap);
  559. if (fe0->dvb.frontend != NULL) {
  560. struct dvb_frontend *fe;
  561. struct xc2028_config cfg = {
  562. .i2c_adap = &i2c_bus->i2c_adap,
  563. .i2c_addr = 0x61,
  564. };
  565. static struct xc2028_ctrl ctl = {
  566. .fname = XC2028_DEFAULT_FIRMWARE,
  567. .max_len = 64,
  568. .demod = XC3028_FE_OREN538,
  569. };
  570. fe = dvb_attach(xc2028_attach,
  571. fe0->dvb.frontend, &cfg);
  572. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  573. fe->ops.tuner_ops.set_config(fe, &ctl);
  574. }
  575. break;
  576. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  577. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  578. i2c_bus = &dev->i2c_bus[0];
  579. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  580. &hauppauge_hvr1200_config,
  581. &i2c_bus->i2c_adap);
  582. if (fe0->dvb.frontend != NULL) {
  583. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  584. &dev->i2c_bus[1].i2c_adap, 0x42,
  585. &tda829x_no_probe);
  586. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  587. 0x60, &dev->i2c_bus[1].i2c_adap,
  588. &hauppauge_hvr1200_tuner_config);
  589. }
  590. break;
  591. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  592. i2c_bus = &dev->i2c_bus[0];
  593. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  594. &hauppauge_hvr1210_config,
  595. &i2c_bus->i2c_adap);
  596. if (fe0->dvb.frontend != NULL) {
  597. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  598. 0x60, &dev->i2c_bus[1].i2c_adap,
  599. &hauppauge_hvr1210_tuner_config);
  600. }
  601. break;
  602. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  603. i2c_bus = &dev->i2c_bus[0];
  604. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  605. &i2c_bus->i2c_adap,
  606. 0x12, &hauppauge_hvr1400_dib7000_config);
  607. if (fe0->dvb.frontend != NULL) {
  608. struct dvb_frontend *fe;
  609. struct xc2028_config cfg = {
  610. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  611. .i2c_addr = 0x64,
  612. };
  613. static struct xc2028_ctrl ctl = {
  614. .fname = XC3028L_DEFAULT_FIRMWARE,
  615. .max_len = 64,
  616. .demod = 5000,
  617. /* This is true for all demods with
  618. v36 firmware? */
  619. .type = XC2028_D2633,
  620. };
  621. fe = dvb_attach(xc2028_attach,
  622. fe0->dvb.frontend, &cfg);
  623. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  624. fe->ops.tuner_ops.set_config(fe, &ctl);
  625. }
  626. break;
  627. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  628. i2c_bus = &dev->i2c_bus[port->nr - 1];
  629. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  630. &dvico_s5h1409_config,
  631. &i2c_bus->i2c_adap);
  632. if (fe0->dvb.frontend == NULL)
  633. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  634. &dvico_s5h1411_config,
  635. &i2c_bus->i2c_adap);
  636. if (fe0->dvb.frontend != NULL)
  637. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  638. &i2c_bus->i2c_adap,
  639. &dvico_xc5000_tunerconfig);
  640. break;
  641. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  642. i2c_bus = &dev->i2c_bus[port->nr - 1];
  643. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  644. &dvico_fusionhdtv_xc3028,
  645. &i2c_bus->i2c_adap);
  646. if (fe0->dvb.frontend != NULL) {
  647. struct dvb_frontend *fe;
  648. struct xc2028_config cfg = {
  649. .i2c_adap = &i2c_bus->i2c_adap,
  650. .i2c_addr = 0x61,
  651. };
  652. static struct xc2028_ctrl ctl = {
  653. .fname = XC2028_DEFAULT_FIRMWARE,
  654. .max_len = 64,
  655. .demod = XC3028_FE_ZARLINK456,
  656. };
  657. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  658. &cfg);
  659. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  660. fe->ops.tuner_ops.set_config(fe, &ctl);
  661. }
  662. break;
  663. }
  664. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  665. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  666. i2c_bus = &dev->i2c_bus[0];
  667. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  668. &dvico_fusionhdtv_xc3028,
  669. &i2c_bus->i2c_adap);
  670. if (fe0->dvb.frontend != NULL) {
  671. struct dvb_frontend *fe;
  672. struct xc2028_config cfg = {
  673. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  674. .i2c_addr = 0x61,
  675. };
  676. static struct xc2028_ctrl ctl = {
  677. .fname = XC2028_DEFAULT_FIRMWARE,
  678. .max_len = 64,
  679. .demod = XC3028_FE_ZARLINK456,
  680. };
  681. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  682. &cfg);
  683. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  684. fe->ops.tuner_ops.set_config(fe, &ctl);
  685. }
  686. break;
  687. case CX23885_BOARD_TBS_6920:
  688. i2c_bus = &dev->i2c_bus[0];
  689. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  690. &tbs_cx24116_config,
  691. &i2c_bus->i2c_adap);
  692. if (fe0->dvb.frontend != NULL)
  693. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  694. break;
  695. case CX23885_BOARD_TEVII_S470:
  696. i2c_bus = &dev->i2c_bus[1];
  697. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  698. &tevii_cx24116_config,
  699. &i2c_bus->i2c_adap);
  700. if (fe0->dvb.frontend != NULL)
  701. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  702. break;
  703. case CX23885_BOARD_DVBWORLD_2005:
  704. i2c_bus = &dev->i2c_bus[1];
  705. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  706. &dvbworld_cx24116_config,
  707. &i2c_bus->i2c_adap);
  708. break;
  709. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  710. i2c_bus = &dev->i2c_bus[0];
  711. switch (port->nr) {
  712. /* port B */
  713. case 1:
  714. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  715. &netup_stv0900_config,
  716. &i2c_bus->i2c_adap, 0);
  717. if (fe0->dvb.frontend != NULL) {
  718. if (dvb_attach(stv6110_attach,
  719. fe0->dvb.frontend,
  720. &netup_stv6110_tunerconfig_a,
  721. &i2c_bus->i2c_adap)) {
  722. if (!dvb_attach(lnbh24_attach,
  723. fe0->dvb.frontend,
  724. &i2c_bus->i2c_adap,
  725. LNBH24_PCL,
  726. LNBH24_TTX, 0x09))
  727. printk(KERN_ERR
  728. "No LNBH24 found!\n");
  729. }
  730. }
  731. break;
  732. /* port C */
  733. case 2:
  734. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  735. &netup_stv0900_config,
  736. &i2c_bus->i2c_adap, 1);
  737. if (fe0->dvb.frontend != NULL) {
  738. if (dvb_attach(stv6110_attach,
  739. fe0->dvb.frontend,
  740. &netup_stv6110_tunerconfig_b,
  741. &i2c_bus->i2c_adap)) {
  742. if (!dvb_attach(lnbh24_attach,
  743. fe0->dvb.frontend,
  744. &i2c_bus->i2c_adap,
  745. LNBH24_PCL,
  746. LNBH24_TTX, 0x0a))
  747. printk(KERN_ERR
  748. "No LNBH24 found!\n");
  749. }
  750. }
  751. break;
  752. }
  753. break;
  754. case CX23885_BOARD_MYGICA_X8506:
  755. i2c_bus = &dev->i2c_bus[0];
  756. i2c_bus2 = &dev->i2c_bus[1];
  757. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  758. &mygica_x8506_lgs8gl5_config,
  759. &i2c_bus->i2c_adap);
  760. if (fe0->dvb.frontend != NULL) {
  761. dvb_attach(xc5000_attach,
  762. fe0->dvb.frontend,
  763. &i2c_bus2->i2c_adap,
  764. &mygica_x8506_xc5000_config);
  765. }
  766. break;
  767. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  768. i2c_bus = &dev->i2c_bus[0];
  769. i2c_bus2 = &dev->i2c_bus[1];
  770. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  771. &magicpro_prohdtve2_lgs8g75_config,
  772. &i2c_bus->i2c_adap);
  773. if (fe0->dvb.frontend != NULL) {
  774. dvb_attach(xc5000_attach,
  775. fe0->dvb.frontend,
  776. &i2c_bus2->i2c_adap,
  777. &magicpro_prohdtve2_xc5000_config);
  778. }
  779. break;
  780. default:
  781. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  782. " isn't supported yet\n",
  783. dev->name);
  784. break;
  785. }
  786. if (NULL == fe0->dvb.frontend) {
  787. printk(KERN_ERR "%s: frontend initialization failed\n",
  788. dev->name);
  789. return -1;
  790. }
  791. /* define general-purpose callback pointer */
  792. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  793. /* Put the analog decoder in standby to keep it quiet */
  794. call_all(dev, tuner, s_standby);
  795. if (fe0->dvb.frontend->ops.analog_ops.standby)
  796. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  797. /* register everything */
  798. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  799. &dev->pci->dev, adapter_nr, 0);
  800. /* init CI & MAC */
  801. switch (dev->board) {
  802. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  803. static struct netup_card_info cinfo;
  804. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  805. memcpy(port->frontends.adapter.proposed_mac,
  806. cinfo.port[port->nr - 1].mac, 6);
  807. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  808. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  809. port->nr,
  810. port->frontends.adapter.proposed_mac[0],
  811. port->frontends.adapter.proposed_mac[1],
  812. port->frontends.adapter.proposed_mac[2],
  813. port->frontends.adapter.proposed_mac[3],
  814. port->frontends.adapter.proposed_mac[4],
  815. port->frontends.adapter.proposed_mac[5]);
  816. netup_ci_init(port);
  817. break;
  818. }
  819. }
  820. return ret;
  821. }
  822. int cx23885_dvb_register(struct cx23885_tsport *port)
  823. {
  824. struct videobuf_dvb_frontend *fe0;
  825. struct cx23885_dev *dev = port->dev;
  826. int err, i;
  827. /* Here we need to allocate the correct number of frontends,
  828. * as reflected in the cards struct. The reality is that currrently
  829. * no cx23885 boards support this - yet. But, if we don't modify this
  830. * code then the second frontend would never be allocated (later)
  831. * and fail with error before the attach in dvb_register().
  832. * Without these changes we risk an OOPS later. The changes here
  833. * are for safety, and should provide a good foundation for the
  834. * future addition of any multi-frontend cx23885 based boards.
  835. */
  836. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  837. port->num_frontends);
  838. for (i = 1; i <= port->num_frontends; i++) {
  839. if (videobuf_dvb_alloc_frontend(
  840. &port->frontends, i) == NULL) {
  841. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  842. return -ENOMEM;
  843. }
  844. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  845. if (!fe0)
  846. err = -EINVAL;
  847. dprintk(1, "%s\n", __func__);
  848. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  849. dev->board,
  850. dev->name,
  851. dev->pci_bus,
  852. dev->pci_slot);
  853. err = -ENODEV;
  854. /* dvb stuff */
  855. /* We have to init the queue for each frontend on a port. */
  856. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  857. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  858. &dev->pci->dev, &port->slock,
  859. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  860. sizeof(struct cx23885_buffer), port);
  861. }
  862. err = dvb_register(port);
  863. if (err != 0)
  864. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  865. __func__, err);
  866. return err;
  867. }
  868. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  869. {
  870. struct videobuf_dvb_frontend *fe0;
  871. /* FIXME: in an error condition where the we have
  872. * an expected number of frontends (attach problem)
  873. * then this might not clean up correctly, if 1
  874. * is invalid.
  875. * This comment only applies to future boards IF they
  876. * implement MFE support.
  877. */
  878. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  879. if (fe0->dvb.frontend)
  880. videobuf_dvb_unregister_bus(&port->frontends);
  881. switch (port->dev->board) {
  882. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  883. netup_ci_exit(port);
  884. break;
  885. }
  886. return 0;
  887. }