pm-debug.c 13 KB

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  1. /*
  2. * OMAP Power Management debug routines
  3. *
  4. * Copyright (C) 2005 Texas Instruments, Inc.
  5. * Copyright (C) 2006-2008 Nokia Corporation
  6. *
  7. * Written by:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Tony Lindgren
  10. * Juha Yrjola
  11. * Amit Kucheria <amit.kucheria@nokia.com>
  12. * Igor Stoppa <igor.stoppa@nokia.com>
  13. * Jouni Hogander
  14. *
  15. * Based on pm.c for omap2
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/sched.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/io.h>
  26. #include <linux/module.h>
  27. #include <mach/clock.h>
  28. #include <mach/board.h>
  29. #include <mach/powerdomain.h>
  30. #include <mach/clockdomain.h>
  31. #include "prm.h"
  32. #include "cm.h"
  33. #include "pm.h"
  34. int omap2_pm_debug;
  35. #define DUMP_PRM_MOD_REG(mod, reg) \
  36. regs[reg_count].name = #mod "." #reg; \
  37. regs[reg_count++].val = prm_read_mod_reg(mod, reg)
  38. #define DUMP_CM_MOD_REG(mod, reg) \
  39. regs[reg_count].name = #mod "." #reg; \
  40. regs[reg_count++].val = cm_read_mod_reg(mod, reg)
  41. #define DUMP_PRM_REG(reg) \
  42. regs[reg_count].name = #reg; \
  43. regs[reg_count++].val = __raw_readl(reg)
  44. #define DUMP_CM_REG(reg) \
  45. regs[reg_count].name = #reg; \
  46. regs[reg_count++].val = __raw_readl(reg)
  47. #define DUMP_INTC_REG(reg, off) \
  48. regs[reg_count].name = #reg; \
  49. regs[reg_count++].val = \
  50. __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
  51. static int __init pm_dbg_init(void);
  52. void omap2_pm_dump(int mode, int resume, unsigned int us)
  53. {
  54. struct reg {
  55. const char *name;
  56. u32 val;
  57. } regs[32];
  58. int reg_count = 0, i;
  59. const char *s1 = NULL, *s2 = NULL;
  60. if (!resume) {
  61. #if 0
  62. /* MPU */
  63. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
  64. DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
  65. DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
  66. DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
  67. DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
  68. #endif
  69. #if 0
  70. /* INTC */
  71. DUMP_INTC_REG(INTC_MIR0, 0x0084);
  72. DUMP_INTC_REG(INTC_MIR1, 0x00a4);
  73. DUMP_INTC_REG(INTC_MIR2, 0x00c4);
  74. #endif
  75. #if 0
  76. DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
  77. if (cpu_is_omap24xx()) {
  78. DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  79. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  80. OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
  81. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  82. OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
  83. }
  84. DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
  85. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
  86. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
  87. DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
  88. DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
  89. DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
  90. DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
  91. #endif
  92. #if 0
  93. /* DSP */
  94. if (cpu_is_omap24xx()) {
  95. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
  96. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
  97. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
  98. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
  99. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
  100. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
  101. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
  102. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
  103. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
  104. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
  105. }
  106. #endif
  107. } else {
  108. DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
  109. if (cpu_is_omap24xx())
  110. DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
  111. DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
  112. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  113. #if 1
  114. DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
  115. DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
  116. DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
  117. #endif
  118. }
  119. switch (mode) {
  120. case 0:
  121. s1 = "full";
  122. s2 = "retention";
  123. break;
  124. case 1:
  125. s1 = "MPU";
  126. s2 = "retention";
  127. break;
  128. case 2:
  129. s1 = "MPU";
  130. s2 = "idle";
  131. break;
  132. }
  133. if (!resume)
  134. #ifdef CONFIG_NO_HZ
  135. printk(KERN_INFO
  136. "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
  137. jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
  138. jiffies));
  139. #else
  140. printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
  141. #endif
  142. else
  143. printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
  144. us / 1000, us % 1000);
  145. for (i = 0; i < reg_count; i++)
  146. printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
  147. }
  148. #ifdef CONFIG_DEBUG_FS
  149. #include <linux/debugfs.h>
  150. #include <linux/seq_file.h>
  151. static void pm_dbg_regset_store(u32 *ptr);
  152. struct dentry *pm_dbg_dir;
  153. static int pm_dbg_init_done;
  154. enum {
  155. DEBUG_FILE_COUNTERS = 0,
  156. DEBUG_FILE_TIMERS,
  157. };
  158. struct pm_module_def {
  159. char name[8]; /* Name of the module */
  160. short type; /* CM or PRM */
  161. unsigned short offset;
  162. int low; /* First register address on this module */
  163. int high; /* Last register address on this module */
  164. };
  165. #define MOD_CM 0
  166. #define MOD_PRM 1
  167. static const struct pm_module_def *pm_dbg_reg_modules;
  168. static const struct pm_module_def omap3_pm_reg_modules[] = {
  169. { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
  170. { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
  171. { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
  172. { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
  173. { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
  174. { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
  175. { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
  176. { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
  177. { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
  178. { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
  179. { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
  180. { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
  181. { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
  182. { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
  183. { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
  184. { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
  185. { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
  186. { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
  187. { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
  188. { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
  189. { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
  190. { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
  191. { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
  192. { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
  193. { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
  194. { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
  195. { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
  196. { "", 0, 0, 0, 0 },
  197. };
  198. #define PM_DBG_MAX_REG_SETS 4
  199. static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
  200. static int pm_dbg_get_regset_size(void)
  201. {
  202. static int regset_size;
  203. if (regset_size == 0) {
  204. int i = 0;
  205. while (pm_dbg_reg_modules[i].name[0] != 0) {
  206. regset_size += pm_dbg_reg_modules[i].high +
  207. 4 - pm_dbg_reg_modules[i].low;
  208. i++;
  209. }
  210. }
  211. return regset_size;
  212. }
  213. static int pm_dbg_show_regs(struct seq_file *s, void *unused)
  214. {
  215. int i, j;
  216. unsigned long val;
  217. int reg_set = (int)s->private;
  218. u32 *ptr;
  219. void *store = NULL;
  220. int regs;
  221. int linefeed;
  222. if (reg_set == 0) {
  223. store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  224. ptr = store;
  225. pm_dbg_regset_store(ptr);
  226. } else {
  227. ptr = pm_dbg_reg_set[reg_set - 1];
  228. }
  229. i = 0;
  230. while (pm_dbg_reg_modules[i].name[0] != 0) {
  231. regs = 0;
  232. linefeed = 0;
  233. if (pm_dbg_reg_modules[i].type == MOD_CM)
  234. seq_printf(s, "MOD: CM_%s (%08x)\n",
  235. pm_dbg_reg_modules[i].name,
  236. (u32)(OMAP3430_CM_BASE +
  237. pm_dbg_reg_modules[i].offset));
  238. else
  239. seq_printf(s, "MOD: PRM_%s (%08x)\n",
  240. pm_dbg_reg_modules[i].name,
  241. (u32)(OMAP3430_PRM_BASE +
  242. pm_dbg_reg_modules[i].offset));
  243. for (j = pm_dbg_reg_modules[i].low;
  244. j <= pm_dbg_reg_modules[i].high; j += 4) {
  245. val = *(ptr++);
  246. if (val != 0) {
  247. regs++;
  248. if (linefeed) {
  249. seq_printf(s, "\n");
  250. linefeed = 0;
  251. }
  252. seq_printf(s, " %02x => %08lx", j, val);
  253. if (regs % 4 == 0)
  254. linefeed = 1;
  255. }
  256. }
  257. seq_printf(s, "\n");
  258. i++;
  259. }
  260. if (store != NULL)
  261. kfree(store);
  262. return 0;
  263. }
  264. static void pm_dbg_regset_store(u32 *ptr)
  265. {
  266. int i, j;
  267. u32 val;
  268. i = 0;
  269. while (pm_dbg_reg_modules[i].name[0] != 0) {
  270. for (j = pm_dbg_reg_modules[i].low;
  271. j <= pm_dbg_reg_modules[i].high; j += 4) {
  272. if (pm_dbg_reg_modules[i].type == MOD_CM)
  273. val = cm_read_mod_reg(
  274. pm_dbg_reg_modules[i].offset, j);
  275. else
  276. val = prm_read_mod_reg(
  277. pm_dbg_reg_modules[i].offset, j);
  278. *(ptr++) = val;
  279. }
  280. i++;
  281. }
  282. }
  283. int pm_dbg_regset_save(int reg_set)
  284. {
  285. if (pm_dbg_reg_set[reg_set-1] == NULL)
  286. return -EINVAL;
  287. pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
  288. return 0;
  289. }
  290. static const char pwrdm_state_names[][4] = {
  291. "OFF",
  292. "RET",
  293. "INA",
  294. "ON"
  295. };
  296. void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
  297. {
  298. s64 t;
  299. if (!pm_dbg_init_done)
  300. return ;
  301. /* Update timer for previous state */
  302. t = sched_clock();
  303. pwrdm->state_timer[prev] += t - pwrdm->timer;
  304. pwrdm->timer = t;
  305. }
  306. static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
  307. {
  308. struct seq_file *s = (struct seq_file *)user;
  309. if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
  310. strcmp(clkdm->name, "wkup_clkdm") == 0 ||
  311. strncmp(clkdm->name, "dpll", 4) == 0)
  312. return 0;
  313. seq_printf(s, "%s->%s (%d)", clkdm->name,
  314. clkdm->pwrdm.ptr->name,
  315. atomic_read(&clkdm->usecount));
  316. seq_printf(s, "\n");
  317. return 0;
  318. }
  319. static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
  320. {
  321. struct seq_file *s = (struct seq_file *)user;
  322. int i;
  323. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  324. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  325. strncmp(pwrdm->name, "dpll", 4) == 0)
  326. return 0;
  327. if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
  328. printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
  329. pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
  330. seq_printf(s, "%s (%s)", pwrdm->name,
  331. pwrdm_state_names[pwrdm->state]);
  332. for (i = 0; i < 4; i++)
  333. seq_printf(s, ",%s:%d", pwrdm_state_names[i],
  334. pwrdm->state_counter[i]);
  335. seq_printf(s, "\n");
  336. return 0;
  337. }
  338. static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
  339. {
  340. struct seq_file *s = (struct seq_file *)user;
  341. int i;
  342. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  343. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  344. strncmp(pwrdm->name, "dpll", 4) == 0)
  345. return 0;
  346. pwrdm_state_switch(pwrdm);
  347. seq_printf(s, "%s (%s)", pwrdm->name,
  348. pwrdm_state_names[pwrdm->state]);
  349. for (i = 0; i < 4; i++)
  350. seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
  351. pwrdm->state_timer[i]);
  352. seq_printf(s, "\n");
  353. return 0;
  354. }
  355. static int pm_dbg_show_counters(struct seq_file *s, void *unused)
  356. {
  357. pwrdm_for_each(pwrdm_dbg_show_counter, s);
  358. clkdm_for_each(clkdm_dbg_show_counter, s);
  359. return 0;
  360. }
  361. static int pm_dbg_show_timers(struct seq_file *s, void *unused)
  362. {
  363. pwrdm_for_each(pwrdm_dbg_show_timer, s);
  364. return 0;
  365. }
  366. static int pm_dbg_open(struct inode *inode, struct file *file)
  367. {
  368. switch ((int)inode->i_private) {
  369. case DEBUG_FILE_COUNTERS:
  370. return single_open(file, pm_dbg_show_counters,
  371. &inode->i_private);
  372. case DEBUG_FILE_TIMERS:
  373. default:
  374. return single_open(file, pm_dbg_show_timers,
  375. &inode->i_private);
  376. };
  377. }
  378. static int pm_dbg_reg_open(struct inode *inode, struct file *file)
  379. {
  380. return single_open(file, pm_dbg_show_regs, inode->i_private);
  381. }
  382. static const struct file_operations debug_fops = {
  383. .open = pm_dbg_open,
  384. .read = seq_read,
  385. .llseek = seq_lseek,
  386. .release = single_release,
  387. };
  388. static const struct file_operations debug_reg_fops = {
  389. .open = pm_dbg_reg_open,
  390. .read = seq_read,
  391. .llseek = seq_lseek,
  392. .release = single_release,
  393. };
  394. int pm_dbg_regset_init(int reg_set)
  395. {
  396. char name[2];
  397. if (!pm_dbg_init_done)
  398. pm_dbg_init();
  399. if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
  400. pm_dbg_reg_set[reg_set-1] != NULL)
  401. return -EINVAL;
  402. pm_dbg_reg_set[reg_set-1] =
  403. kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  404. if (pm_dbg_reg_set[reg_set-1] == NULL)
  405. return -ENOMEM;
  406. if (pm_dbg_dir != NULL) {
  407. sprintf(name, "%d", reg_set);
  408. (void) debugfs_create_file(name, S_IRUGO,
  409. pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
  410. }
  411. return 0;
  412. }
  413. static int pwrdm_suspend_get(void *data, u64 *val)
  414. {
  415. *val = omap3_pm_get_suspend_state((struct powerdomain *)data);
  416. if (*val >= 0)
  417. return 0;
  418. return *val;
  419. }
  420. static int pwrdm_suspend_set(void *data, u64 val)
  421. {
  422. return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
  423. }
  424. DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
  425. pwrdm_suspend_set, "%llu\n");
  426. static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
  427. {
  428. int i;
  429. s64 t;
  430. struct dentry *d;
  431. t = sched_clock();
  432. for (i = 0; i < 4; i++)
  433. pwrdm->state_timer[i] = 0;
  434. pwrdm->timer = t;
  435. if (strncmp(pwrdm->name, "dpll", 4) == 0)
  436. return 0;
  437. d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
  438. (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
  439. (void *)pwrdm, &pwrdm_suspend_fops);
  440. return 0;
  441. }
  442. static int __init pm_dbg_init(void)
  443. {
  444. int i;
  445. struct dentry *d;
  446. char name[2];
  447. if (pm_dbg_init_done)
  448. return 0;
  449. if (cpu_is_omap34xx())
  450. pm_dbg_reg_modules = omap3_pm_reg_modules;
  451. else {
  452. printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
  453. return -ENODEV;
  454. }
  455. d = debugfs_create_dir("pm_debug", NULL);
  456. if (IS_ERR(d))
  457. return PTR_ERR(d);
  458. (void) debugfs_create_file("count", S_IRUGO,
  459. d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
  460. (void) debugfs_create_file("time", S_IRUGO,
  461. d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
  462. pwrdm_for_each_nolock(pwrdms_setup, (void *)d);
  463. pm_dbg_dir = debugfs_create_dir("registers", d);
  464. if (IS_ERR(pm_dbg_dir))
  465. return PTR_ERR(pm_dbg_dir);
  466. (void) debugfs_create_file("current", S_IRUGO,
  467. pm_dbg_dir, (void *)0, &debug_reg_fops);
  468. for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
  469. if (pm_dbg_reg_set[i] != NULL) {
  470. sprintf(name, "%d", i+1);
  471. (void) debugfs_create_file(name, S_IRUGO,
  472. pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
  473. }
  474. pm_dbg_init_done = 1;
  475. return 0;
  476. }
  477. arch_initcall(pm_dbg_init);
  478. #else
  479. void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
  480. #endif