dss_features.c 24 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dss_features.c
  3. *
  4. * Copyright (C) 2010 Texas Instruments
  5. * Author: Archit Taneja <archit@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/err.h>
  22. #include <linux/slab.h>
  23. #include <video/omapdss.h>
  24. #include <plat/cpu.h>
  25. #include "dss.h"
  26. #include "dss_features.h"
  27. /* Defines a generic omap register field */
  28. struct dss_reg_field {
  29. u8 start, end;
  30. };
  31. struct dss_param_range {
  32. int min, max;
  33. };
  34. struct omap_dss_features {
  35. const struct dss_reg_field *reg_fields;
  36. const int num_reg_fields;
  37. const enum dss_feat_id *features;
  38. const int num_features;
  39. const int num_mgrs;
  40. const int num_ovls;
  41. const enum omap_display_type *supported_displays;
  42. const enum omap_color_mode *supported_color_modes;
  43. const enum omap_overlay_caps *overlay_caps;
  44. const char * const *clksrc_names;
  45. const struct dss_param_range *dss_params;
  46. const enum omap_dss_rotation_type supported_rotation_types;
  47. const u32 buffer_size_unit;
  48. const u32 burst_size_unit;
  49. };
  50. /* This struct is assigned to one of the below during initialization */
  51. static const struct omap_dss_features *omap_current_dss_features;
  52. static const struct dss_reg_field omap2_dss_reg_fields[] = {
  53. [FEAT_REG_FIRHINC] = { 11, 0 },
  54. [FEAT_REG_FIRVINC] = { 27, 16 },
  55. [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
  56. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
  57. [FEAT_REG_FIFOSIZE] = { 8, 0 },
  58. [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
  59. [FEAT_REG_VERTICALACCU] = { 25, 16 },
  60. [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
  61. [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
  62. [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
  63. [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
  64. [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
  65. };
  66. static const struct dss_reg_field omap3_dss_reg_fields[] = {
  67. [FEAT_REG_FIRHINC] = { 12, 0 },
  68. [FEAT_REG_FIRVINC] = { 28, 16 },
  69. [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
  70. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
  71. [FEAT_REG_FIFOSIZE] = { 10, 0 },
  72. [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
  73. [FEAT_REG_VERTICALACCU] = { 25, 16 },
  74. [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
  75. [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
  76. [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
  77. [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
  78. [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
  79. };
  80. static const struct dss_reg_field omap4_dss_reg_fields[] = {
  81. [FEAT_REG_FIRHINC] = { 12, 0 },
  82. [FEAT_REG_FIRVINC] = { 28, 16 },
  83. [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
  84. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
  85. [FEAT_REG_FIFOSIZE] = { 15, 0 },
  86. [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
  87. [FEAT_REG_VERTICALACCU] = { 26, 16 },
  88. [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
  89. [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
  90. [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
  91. [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
  92. [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
  93. };
  94. static const struct dss_reg_field omap5_dss_reg_fields[] = {
  95. [FEAT_REG_FIRHINC] = { 12, 0 },
  96. [FEAT_REG_FIRVINC] = { 28, 16 },
  97. [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
  98. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
  99. [FEAT_REG_FIFOSIZE] = { 15, 0 },
  100. [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
  101. [FEAT_REG_VERTICALACCU] = { 26, 16 },
  102. [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
  103. [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
  104. [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
  105. [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
  106. [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
  107. };
  108. static const enum omap_display_type omap2_dss_supported_displays[] = {
  109. /* OMAP_DSS_CHANNEL_LCD */
  110. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
  111. /* OMAP_DSS_CHANNEL_DIGIT */
  112. OMAP_DISPLAY_TYPE_VENC,
  113. };
  114. static const enum omap_display_type omap3430_dss_supported_displays[] = {
  115. /* OMAP_DSS_CHANNEL_LCD */
  116. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  117. OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
  118. /* OMAP_DSS_CHANNEL_DIGIT */
  119. OMAP_DISPLAY_TYPE_VENC,
  120. };
  121. static const enum omap_display_type omap3630_dss_supported_displays[] = {
  122. /* OMAP_DSS_CHANNEL_LCD */
  123. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  124. OMAP_DISPLAY_TYPE_DSI,
  125. /* OMAP_DSS_CHANNEL_DIGIT */
  126. OMAP_DISPLAY_TYPE_VENC,
  127. };
  128. static const enum omap_display_type omap4_dss_supported_displays[] = {
  129. /* OMAP_DSS_CHANNEL_LCD */
  130. OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
  131. /* OMAP_DSS_CHANNEL_DIGIT */
  132. OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
  133. /* OMAP_DSS_CHANNEL_LCD2 */
  134. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  135. OMAP_DISPLAY_TYPE_DSI,
  136. };
  137. static const enum omap_display_type omap5_dss_supported_displays[] = {
  138. /* OMAP_DSS_CHANNEL_LCD */
  139. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  140. OMAP_DISPLAY_TYPE_DSI,
  141. /* OMAP_DSS_CHANNEL_DIGIT */
  142. OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
  143. /* OMAP_DSS_CHANNEL_LCD2 */
  144. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  145. OMAP_DISPLAY_TYPE_DSI,
  146. };
  147. static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
  148. /* OMAP_DSS_GFX */
  149. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  150. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  151. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  152. OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
  153. /* OMAP_DSS_VIDEO1 */
  154. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  155. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  156. OMAP_DSS_COLOR_UYVY,
  157. /* OMAP_DSS_VIDEO2 */
  158. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  159. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  160. OMAP_DSS_COLOR_UYVY,
  161. };
  162. static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
  163. /* OMAP_DSS_GFX */
  164. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  165. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  166. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  167. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  168. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
  169. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
  170. /* OMAP_DSS_VIDEO1 */
  171. OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
  172. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  173. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
  174. /* OMAP_DSS_VIDEO2 */
  175. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  176. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  177. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  178. OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
  179. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
  180. };
  181. static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
  182. /* OMAP_DSS_GFX */
  183. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  184. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  185. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  186. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  187. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
  188. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
  189. OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
  190. OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
  191. /* OMAP_DSS_VIDEO1 */
  192. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
  193. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
  194. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
  195. OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
  196. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
  197. OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
  198. OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
  199. OMAP_DSS_COLOR_RGBX32,
  200. /* OMAP_DSS_VIDEO2 */
  201. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
  202. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
  203. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
  204. OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
  205. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
  206. OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
  207. OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
  208. OMAP_DSS_COLOR_RGBX32,
  209. /* OMAP_DSS_VIDEO3 */
  210. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
  211. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
  212. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
  213. OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
  214. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
  215. OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
  216. OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
  217. OMAP_DSS_COLOR_RGBX32,
  218. };
  219. static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
  220. /* OMAP_DSS_GFX */
  221. 0,
  222. /* OMAP_DSS_VIDEO1 */
  223. OMAP_DSS_OVL_CAP_SCALE,
  224. /* OMAP_DSS_VIDEO2 */
  225. OMAP_DSS_OVL_CAP_SCALE,
  226. };
  227. static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
  228. /* OMAP_DSS_GFX */
  229. OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
  230. /* OMAP_DSS_VIDEO1 */
  231. OMAP_DSS_OVL_CAP_SCALE,
  232. /* OMAP_DSS_VIDEO2 */
  233. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
  234. };
  235. static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
  236. /* OMAP_DSS_GFX */
  237. OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  238. /* OMAP_DSS_VIDEO1 */
  239. OMAP_DSS_OVL_CAP_SCALE,
  240. /* OMAP_DSS_VIDEO2 */
  241. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  242. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  243. };
  244. static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
  245. /* OMAP_DSS_GFX */
  246. OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
  247. OMAP_DSS_OVL_CAP_ZORDER,
  248. /* OMAP_DSS_VIDEO1 */
  249. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  250. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
  251. /* OMAP_DSS_VIDEO2 */
  252. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  253. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
  254. /* OMAP_DSS_VIDEO3 */
  255. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  256. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
  257. };
  258. static const char * const omap2_dss_clk_source_names[] = {
  259. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
  260. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
  261. [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
  262. };
  263. static const char * const omap3_dss_clk_source_names[] = {
  264. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
  265. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
  266. [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
  267. };
  268. static const char * const omap4_dss_clk_source_names[] = {
  269. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
  270. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
  271. [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
  272. [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
  273. [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
  274. };
  275. static const char * const omap5_dss_clk_source_names[] = {
  276. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1",
  277. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2",
  278. [OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK",
  279. [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
  280. [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2",
  281. };
  282. static const struct dss_param_range omap2_dss_param_range[] = {
  283. [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
  284. [FEAT_PARAM_DSS_PCD] = { 2, 255 },
  285. [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
  286. [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
  287. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
  288. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
  289. [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
  290. [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
  291. [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
  292. /*
  293. * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
  294. * scaler cannot scale a image with width more than 768.
  295. */
  296. [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
  297. [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
  298. [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
  299. };
  300. static const struct dss_param_range omap3_dss_param_range[] = {
  301. [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
  302. [FEAT_PARAM_DSS_PCD] = { 1, 255 },
  303. [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
  304. [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
  305. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
  306. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
  307. [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
  308. [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
  309. [FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
  310. [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
  311. [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
  312. [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
  313. [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
  314. };
  315. static const struct dss_param_range omap4_dss_param_range[] = {
  316. [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
  317. [FEAT_PARAM_DSS_PCD] = { 1, 255 },
  318. [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
  319. [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
  320. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
  321. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
  322. [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
  323. [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
  324. [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
  325. [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
  326. [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
  327. [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
  328. [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
  329. };
  330. static const struct dss_param_range omap5_dss_param_range[] = {
  331. [FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
  332. [FEAT_PARAM_DSS_PCD] = { 1, 255 },
  333. [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
  334. [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
  335. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
  336. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
  337. [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
  338. [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
  339. [FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
  340. [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
  341. [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
  342. [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
  343. [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
  344. };
  345. static const enum dss_feat_id omap2_dss_feat_list[] = {
  346. FEAT_LCDENABLEPOL,
  347. FEAT_LCDENABLESIGNAL,
  348. FEAT_PCKFREEENABLE,
  349. FEAT_FUNCGATED,
  350. FEAT_ROWREPEATENABLE,
  351. FEAT_RESIZECONF,
  352. };
  353. static const enum dss_feat_id omap3430_dss_feat_list[] = {
  354. FEAT_LCDENABLEPOL,
  355. FEAT_LCDENABLESIGNAL,
  356. FEAT_PCKFREEENABLE,
  357. FEAT_FUNCGATED,
  358. FEAT_LINEBUFFERSPLIT,
  359. FEAT_ROWREPEATENABLE,
  360. FEAT_RESIZECONF,
  361. FEAT_DSI_PLL_FREQSEL,
  362. FEAT_DSI_REVERSE_TXCLKESC,
  363. FEAT_VENC_REQUIRES_TV_DAC_CLK,
  364. FEAT_CPR,
  365. FEAT_PRELOAD,
  366. FEAT_FIR_COEF_V,
  367. FEAT_ALPHA_FIXED_ZORDER,
  368. FEAT_FIFO_MERGE,
  369. FEAT_OMAP3_DSI_FIFO_BUG,
  370. FEAT_DPI_USES_VDDS_DSI,
  371. };
  372. static const enum dss_feat_id omap3630_dss_feat_list[] = {
  373. FEAT_LCDENABLEPOL,
  374. FEAT_LCDENABLESIGNAL,
  375. FEAT_PCKFREEENABLE,
  376. FEAT_FUNCGATED,
  377. FEAT_LINEBUFFERSPLIT,
  378. FEAT_ROWREPEATENABLE,
  379. FEAT_RESIZECONF,
  380. FEAT_DSI_PLL_PWR_BUG,
  381. FEAT_DSI_PLL_FREQSEL,
  382. FEAT_CPR,
  383. FEAT_PRELOAD,
  384. FEAT_FIR_COEF_V,
  385. FEAT_ALPHA_FIXED_ZORDER,
  386. FEAT_FIFO_MERGE,
  387. FEAT_OMAP3_DSI_FIFO_BUG,
  388. };
  389. static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
  390. FEAT_MGR_LCD2,
  391. FEAT_CORE_CLK_DIV,
  392. FEAT_LCD_CLK_SRC,
  393. FEAT_DSI_DCS_CMD_CONFIG_VC,
  394. FEAT_DSI_VC_OCP_WIDTH,
  395. FEAT_DSI_GNQ,
  396. FEAT_HANDLE_UV_SEPARATE,
  397. FEAT_ATTR2,
  398. FEAT_CPR,
  399. FEAT_PRELOAD,
  400. FEAT_FIR_COEF_V,
  401. FEAT_ALPHA_FREE_ZORDER,
  402. FEAT_FIFO_MERGE,
  403. FEAT_BURST_2D,
  404. };
  405. static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
  406. FEAT_MGR_LCD2,
  407. FEAT_CORE_CLK_DIV,
  408. FEAT_LCD_CLK_SRC,
  409. FEAT_DSI_DCS_CMD_CONFIG_VC,
  410. FEAT_DSI_VC_OCP_WIDTH,
  411. FEAT_DSI_GNQ,
  412. FEAT_HDMI_CTS_SWMODE,
  413. FEAT_HANDLE_UV_SEPARATE,
  414. FEAT_ATTR2,
  415. FEAT_CPR,
  416. FEAT_PRELOAD,
  417. FEAT_FIR_COEF_V,
  418. FEAT_ALPHA_FREE_ZORDER,
  419. FEAT_FIFO_MERGE,
  420. FEAT_BURST_2D,
  421. };
  422. static const enum dss_feat_id omap4_dss_feat_list[] = {
  423. FEAT_MGR_LCD2,
  424. FEAT_CORE_CLK_DIV,
  425. FEAT_LCD_CLK_SRC,
  426. FEAT_DSI_DCS_CMD_CONFIG_VC,
  427. FEAT_DSI_VC_OCP_WIDTH,
  428. FEAT_DSI_GNQ,
  429. FEAT_HDMI_CTS_SWMODE,
  430. FEAT_HDMI_AUDIO_USE_MCLK,
  431. FEAT_HANDLE_UV_SEPARATE,
  432. FEAT_ATTR2,
  433. FEAT_CPR,
  434. FEAT_PRELOAD,
  435. FEAT_FIR_COEF_V,
  436. FEAT_ALPHA_FREE_ZORDER,
  437. FEAT_FIFO_MERGE,
  438. FEAT_BURST_2D,
  439. };
  440. static const enum dss_feat_id omap5_dss_feat_list[] = {
  441. FEAT_MGR_LCD2,
  442. FEAT_CORE_CLK_DIV,
  443. FEAT_LCD_CLK_SRC,
  444. FEAT_DSI_DCS_CMD_CONFIG_VC,
  445. FEAT_DSI_VC_OCP_WIDTH,
  446. FEAT_DSI_GNQ,
  447. FEAT_HDMI_CTS_SWMODE,
  448. FEAT_HDMI_AUDIO_USE_MCLK,
  449. FEAT_HANDLE_UV_SEPARATE,
  450. FEAT_ATTR2,
  451. FEAT_CPR,
  452. FEAT_PRELOAD,
  453. FEAT_FIR_COEF_V,
  454. FEAT_ALPHA_FREE_ZORDER,
  455. FEAT_FIFO_MERGE,
  456. FEAT_BURST_2D,
  457. };
  458. /* OMAP2 DSS Features */
  459. static const struct omap_dss_features omap2_dss_features = {
  460. .reg_fields = omap2_dss_reg_fields,
  461. .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
  462. .features = omap2_dss_feat_list,
  463. .num_features = ARRAY_SIZE(omap2_dss_feat_list),
  464. .num_mgrs = 2,
  465. .num_ovls = 3,
  466. .supported_displays = omap2_dss_supported_displays,
  467. .supported_color_modes = omap2_dss_supported_color_modes,
  468. .overlay_caps = omap2_dss_overlay_caps,
  469. .clksrc_names = omap2_dss_clk_source_names,
  470. .dss_params = omap2_dss_param_range,
  471. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
  472. .buffer_size_unit = 1,
  473. .burst_size_unit = 8,
  474. };
  475. /* OMAP3 DSS Features */
  476. static const struct omap_dss_features omap3430_dss_features = {
  477. .reg_fields = omap3_dss_reg_fields,
  478. .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
  479. .features = omap3430_dss_feat_list,
  480. .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
  481. .num_mgrs = 2,
  482. .num_ovls = 3,
  483. .supported_displays = omap3430_dss_supported_displays,
  484. .supported_color_modes = omap3_dss_supported_color_modes,
  485. .overlay_caps = omap3430_dss_overlay_caps,
  486. .clksrc_names = omap3_dss_clk_source_names,
  487. .dss_params = omap3_dss_param_range,
  488. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
  489. .buffer_size_unit = 1,
  490. .burst_size_unit = 8,
  491. };
  492. static const struct omap_dss_features omap3630_dss_features = {
  493. .reg_fields = omap3_dss_reg_fields,
  494. .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
  495. .features = omap3630_dss_feat_list,
  496. .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
  497. .num_mgrs = 2,
  498. .num_ovls = 3,
  499. .supported_displays = omap3630_dss_supported_displays,
  500. .supported_color_modes = omap3_dss_supported_color_modes,
  501. .overlay_caps = omap3630_dss_overlay_caps,
  502. .clksrc_names = omap3_dss_clk_source_names,
  503. .dss_params = omap3_dss_param_range,
  504. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
  505. .buffer_size_unit = 1,
  506. .burst_size_unit = 8,
  507. };
  508. /* OMAP4 DSS Features */
  509. /* For OMAP4430 ES 1.0 revision */
  510. static const struct omap_dss_features omap4430_es1_0_dss_features = {
  511. .reg_fields = omap4_dss_reg_fields,
  512. .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
  513. .features = omap4430_es1_0_dss_feat_list,
  514. .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
  515. .num_mgrs = 3,
  516. .num_ovls = 4,
  517. .supported_displays = omap4_dss_supported_displays,
  518. .supported_color_modes = omap4_dss_supported_color_modes,
  519. .overlay_caps = omap4_dss_overlay_caps,
  520. .clksrc_names = omap4_dss_clk_source_names,
  521. .dss_params = omap4_dss_param_range,
  522. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
  523. .buffer_size_unit = 16,
  524. .burst_size_unit = 16,
  525. };
  526. /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
  527. static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
  528. .reg_fields = omap4_dss_reg_fields,
  529. .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
  530. .features = omap4430_es2_0_1_2_dss_feat_list,
  531. .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
  532. .num_mgrs = 3,
  533. .num_ovls = 4,
  534. .supported_displays = omap4_dss_supported_displays,
  535. .supported_color_modes = omap4_dss_supported_color_modes,
  536. .overlay_caps = omap4_dss_overlay_caps,
  537. .clksrc_names = omap4_dss_clk_source_names,
  538. .dss_params = omap4_dss_param_range,
  539. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
  540. .buffer_size_unit = 16,
  541. .burst_size_unit = 16,
  542. };
  543. /* For all the other OMAP4 versions */
  544. static const struct omap_dss_features omap4_dss_features = {
  545. .reg_fields = omap4_dss_reg_fields,
  546. .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
  547. .features = omap4_dss_feat_list,
  548. .num_features = ARRAY_SIZE(omap4_dss_feat_list),
  549. .num_mgrs = 3,
  550. .num_ovls = 4,
  551. .supported_displays = omap4_dss_supported_displays,
  552. .supported_color_modes = omap4_dss_supported_color_modes,
  553. .overlay_caps = omap4_dss_overlay_caps,
  554. .clksrc_names = omap4_dss_clk_source_names,
  555. .dss_params = omap4_dss_param_range,
  556. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
  557. .buffer_size_unit = 16,
  558. .burst_size_unit = 16,
  559. };
  560. /* OMAP5 DSS Features */
  561. static const struct omap_dss_features omap5_dss_features = {
  562. .reg_fields = omap5_dss_reg_fields,
  563. .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
  564. .features = omap5_dss_feat_list,
  565. .num_features = ARRAY_SIZE(omap5_dss_feat_list),
  566. .num_mgrs = 3,
  567. .num_ovls = 4,
  568. .supported_displays = omap5_dss_supported_displays,
  569. .supported_color_modes = omap4_dss_supported_color_modes,
  570. .overlay_caps = omap4_dss_overlay_caps,
  571. .clksrc_names = omap5_dss_clk_source_names,
  572. .dss_params = omap5_dss_param_range,
  573. .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
  574. .buffer_size_unit = 16,
  575. .burst_size_unit = 16,
  576. };
  577. #if defined(CONFIG_OMAP4_DSS_HDMI)
  578. /* HDMI OMAP4 Functions*/
  579. static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
  580. .video_configure = ti_hdmi_4xxx_basic_configure,
  581. .phy_enable = ti_hdmi_4xxx_phy_enable,
  582. .phy_disable = ti_hdmi_4xxx_phy_disable,
  583. .read_edid = ti_hdmi_4xxx_read_edid,
  584. .detect = ti_hdmi_4xxx_detect,
  585. .pll_enable = ti_hdmi_4xxx_pll_enable,
  586. .pll_disable = ti_hdmi_4xxx_pll_disable,
  587. .video_enable = ti_hdmi_4xxx_wp_video_start,
  588. .video_disable = ti_hdmi_4xxx_wp_video_stop,
  589. .dump_wrapper = ti_hdmi_4xxx_wp_dump,
  590. .dump_core = ti_hdmi_4xxx_core_dump,
  591. .dump_pll = ti_hdmi_4xxx_pll_dump,
  592. .dump_phy = ti_hdmi_4xxx_phy_dump,
  593. #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
  594. .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
  595. .audio_disable = ti_hdmi_4xxx_wp_audio_disable,
  596. .audio_start = ti_hdmi_4xxx_audio_start,
  597. .audio_stop = ti_hdmi_4xxx_audio_stop,
  598. .audio_config = ti_hdmi_4xxx_audio_config,
  599. #endif
  600. };
  601. void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
  602. {
  603. if (cpu_is_omap44xx())
  604. ip_data->ops = &omap4_hdmi_functions;
  605. }
  606. #endif
  607. /* Functions returning values related to a DSS feature */
  608. int dss_feat_get_num_mgrs(void)
  609. {
  610. return omap_current_dss_features->num_mgrs;
  611. }
  612. int dss_feat_get_num_ovls(void)
  613. {
  614. return omap_current_dss_features->num_ovls;
  615. }
  616. unsigned long dss_feat_get_param_min(enum dss_range_param param)
  617. {
  618. return omap_current_dss_features->dss_params[param].min;
  619. }
  620. unsigned long dss_feat_get_param_max(enum dss_range_param param)
  621. {
  622. return omap_current_dss_features->dss_params[param].max;
  623. }
  624. enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
  625. {
  626. return omap_current_dss_features->supported_displays[channel];
  627. }
  628. enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
  629. {
  630. return omap_current_dss_features->supported_color_modes[plane];
  631. }
  632. enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
  633. {
  634. return omap_current_dss_features->overlay_caps[plane];
  635. }
  636. bool dss_feat_color_mode_supported(enum omap_plane plane,
  637. enum omap_color_mode color_mode)
  638. {
  639. return omap_current_dss_features->supported_color_modes[plane] &
  640. color_mode;
  641. }
  642. const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
  643. {
  644. return omap_current_dss_features->clksrc_names[id];
  645. }
  646. u32 dss_feat_get_buffer_size_unit(void)
  647. {
  648. return omap_current_dss_features->buffer_size_unit;
  649. }
  650. u32 dss_feat_get_burst_size_unit(void)
  651. {
  652. return omap_current_dss_features->burst_size_unit;
  653. }
  654. /* DSS has_feature check */
  655. bool dss_has_feature(enum dss_feat_id id)
  656. {
  657. int i;
  658. const enum dss_feat_id *features = omap_current_dss_features->features;
  659. const int num_features = omap_current_dss_features->num_features;
  660. for (i = 0; i < num_features; i++) {
  661. if (features[i] == id)
  662. return true;
  663. }
  664. return false;
  665. }
  666. void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
  667. {
  668. if (id >= omap_current_dss_features->num_reg_fields)
  669. BUG();
  670. *start = omap_current_dss_features->reg_fields[id].start;
  671. *end = omap_current_dss_features->reg_fields[id].end;
  672. }
  673. bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
  674. {
  675. return omap_current_dss_features->supported_rotation_types & rot_type;
  676. }
  677. void dss_features_init(void)
  678. {
  679. if (cpu_is_omap24xx())
  680. omap_current_dss_features = &omap2_dss_features;
  681. else if (cpu_is_omap3630())
  682. omap_current_dss_features = &omap3630_dss_features;
  683. else if (cpu_is_omap34xx())
  684. omap_current_dss_features = &omap3430_dss_features;
  685. else if (omap_rev() == OMAP4430_REV_ES1_0)
  686. omap_current_dss_features = &omap4430_es1_0_dss_features;
  687. else if (omap_rev() == OMAP4430_REV_ES2_0 ||
  688. omap_rev() == OMAP4430_REV_ES2_1 ||
  689. omap_rev() == OMAP4430_REV_ES2_2)
  690. omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
  691. else if (cpu_is_omap44xx())
  692. omap_current_dss_features = &omap4_dss_features;
  693. else if (soc_is_omap54xx())
  694. omap_current_dss_features = &omap5_dss_features;
  695. else
  696. DSSWARN("Unsupported OMAP version");
  697. }