iwl-rx.c 34 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. unsigned long flags;
  126. u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
  127. u32 reg;
  128. int ret = 0;
  129. spin_lock_irqsave(&q->lock, flags);
  130. if (q->need_update == 0)
  131. goto exit_unlock;
  132. /* If power-saving is in use, make sure device is awake */
  133. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  134. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  135. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  136. iwl_set_bit(priv, CSR_GP_CNTRL,
  137. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  138. goto exit_unlock;
  139. }
  140. q->write_actual = (q->write & ~0x7);
  141. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  142. /* Else device is assumed to be awake */
  143. } else {
  144. /* Device expects a multiple of 8 */
  145. q->write_actual = (q->write & ~0x7);
  146. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  147. }
  148. q->need_update = 0;
  149. exit_unlock:
  150. spin_unlock_irqrestore(&q->lock, flags);
  151. return ret;
  152. }
  153. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  154. /**
  155. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  156. */
  157. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  158. dma_addr_t dma_addr)
  159. {
  160. return cpu_to_le32((u32)(dma_addr >> 8));
  161. }
  162. /**
  163. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  164. *
  165. * If there are slots in the RX queue that need to be restocked,
  166. * and we have free pre-allocated buffers, fill the ranks as much
  167. * as we can, pulling from rx_free.
  168. *
  169. * This moves the 'write' index forward to catch up with 'processed', and
  170. * also updates the memory address in the firmware to reference the new
  171. * target buffer.
  172. */
  173. int iwl_rx_queue_restock(struct iwl_priv *priv)
  174. {
  175. struct iwl_rx_queue *rxq = &priv->rxq;
  176. struct list_head *element;
  177. struct iwl_rx_mem_buffer *rxb;
  178. unsigned long flags;
  179. int write;
  180. int ret = 0;
  181. spin_lock_irqsave(&rxq->lock, flags);
  182. write = rxq->write & ~0x7;
  183. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  184. /* Get next free Rx buffer, remove from free list */
  185. element = rxq->rx_free.next;
  186. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  187. list_del(element);
  188. /* Point to Rx buffer via next RBD in circular buffer */
  189. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr);
  190. rxq->queue[rxq->write] = rxb;
  191. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  192. rxq->free_count--;
  193. }
  194. spin_unlock_irqrestore(&rxq->lock, flags);
  195. /* If the pre-allocated buffer pool is dropping low, schedule to
  196. * refill it */
  197. if (rxq->free_count <= RX_LOW_WATERMARK)
  198. queue_work(priv->workqueue, &priv->rx_replenish);
  199. /* If we've added more space for the firmware to place data, tell it.
  200. * Increment device's write pointer in multiples of 8. */
  201. if (rxq->write_actual != (rxq->write & ~0x7)) {
  202. spin_lock_irqsave(&rxq->lock, flags);
  203. rxq->need_update = 1;
  204. spin_unlock_irqrestore(&rxq->lock, flags);
  205. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  206. }
  207. return ret;
  208. }
  209. EXPORT_SYMBOL(iwl_rx_queue_restock);
  210. /**
  211. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  212. *
  213. * When moving to rx_free an SKB is allocated for the slot.
  214. *
  215. * Also restock the Rx queue via iwl_rx_queue_restock.
  216. * This is called as a scheduled work item (except for during initialization)
  217. */
  218. void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  219. {
  220. struct iwl_rx_queue *rxq = &priv->rxq;
  221. struct list_head *element;
  222. struct iwl_rx_mem_buffer *rxb;
  223. unsigned long flags;
  224. while (1) {
  225. spin_lock_irqsave(&rxq->lock, flags);
  226. if (list_empty(&rxq->rx_used)) {
  227. spin_unlock_irqrestore(&rxq->lock, flags);
  228. return;
  229. }
  230. element = rxq->rx_used.next;
  231. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  232. list_del(element);
  233. spin_unlock_irqrestore(&rxq->lock, flags);
  234. /* Alloc a new receive buffer */
  235. rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256,
  236. priority);
  237. if (!rxb->skb) {
  238. IWL_CRIT(priv, "Can not allocate SKB buffers\n");
  239. /* We don't reschedule replenish work here -- we will
  240. * call the restock method and if it still needs
  241. * more buffers it will schedule replenish */
  242. break;
  243. }
  244. /* Get physical address of RB/SKB */
  245. rxb->real_dma_addr = pci_map_single(
  246. priv->pci_dev,
  247. rxb->skb->data,
  248. priv->hw_params.rx_buf_size + 256,
  249. PCI_DMA_FROMDEVICE);
  250. /* dma address must be no more than 36 bits */
  251. BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36));
  252. /* and also 256 byte aligned! */
  253. rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256);
  254. skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr);
  255. spin_lock_irqsave(&rxq->lock, flags);
  256. list_add_tail(&rxb->list, &rxq->rx_free);
  257. rxq->free_count++;
  258. priv->alloc_rxb_skb++;
  259. spin_unlock_irqrestore(&rxq->lock, flags);
  260. }
  261. }
  262. void iwl_rx_replenish(struct iwl_priv *priv)
  263. {
  264. unsigned long flags;
  265. iwl_rx_allocate(priv, GFP_KERNEL);
  266. spin_lock_irqsave(&priv->lock, flags);
  267. iwl_rx_queue_restock(priv);
  268. spin_unlock_irqrestore(&priv->lock, flags);
  269. }
  270. EXPORT_SYMBOL(iwl_rx_replenish);
  271. void iwl_rx_replenish_now(struct iwl_priv *priv)
  272. {
  273. iwl_rx_allocate(priv, GFP_ATOMIC);
  274. iwl_rx_queue_restock(priv);
  275. }
  276. EXPORT_SYMBOL(iwl_rx_replenish_now);
  277. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  278. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  279. * This free routine walks the list of POOL entries and if SKB is set to
  280. * non NULL it is unmapped and freed
  281. */
  282. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  283. {
  284. int i;
  285. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  286. if (rxq->pool[i].skb != NULL) {
  287. pci_unmap_single(priv->pci_dev,
  288. rxq->pool[i].real_dma_addr,
  289. priv->hw_params.rx_buf_size + 256,
  290. PCI_DMA_FROMDEVICE);
  291. dev_kfree_skb(rxq->pool[i].skb);
  292. }
  293. }
  294. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  295. rxq->dma_addr);
  296. pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
  297. rxq->rb_stts, rxq->rb_stts_dma);
  298. rxq->bd = NULL;
  299. rxq->rb_stts = NULL;
  300. }
  301. EXPORT_SYMBOL(iwl_rx_queue_free);
  302. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  303. {
  304. struct iwl_rx_queue *rxq = &priv->rxq;
  305. struct pci_dev *dev = priv->pci_dev;
  306. int i;
  307. spin_lock_init(&rxq->lock);
  308. INIT_LIST_HEAD(&rxq->rx_free);
  309. INIT_LIST_HEAD(&rxq->rx_used);
  310. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  311. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  312. if (!rxq->bd)
  313. goto err_bd;
  314. rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
  315. &rxq->rb_stts_dma);
  316. if (!rxq->rb_stts)
  317. goto err_rb;
  318. /* Fill the rx_used queue with _all_ of the Rx buffers */
  319. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  320. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  321. /* Set us so that we have processed and used all buffers, but have
  322. * not restocked the Rx queue with fresh buffers */
  323. rxq->read = rxq->write = 0;
  324. rxq->write_actual = 0;
  325. rxq->free_count = 0;
  326. rxq->need_update = 0;
  327. return 0;
  328. err_rb:
  329. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  330. rxq->dma_addr);
  331. err_bd:
  332. return -ENOMEM;
  333. }
  334. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  335. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  336. {
  337. unsigned long flags;
  338. int i;
  339. spin_lock_irqsave(&rxq->lock, flags);
  340. INIT_LIST_HEAD(&rxq->rx_free);
  341. INIT_LIST_HEAD(&rxq->rx_used);
  342. /* Fill the rx_used queue with _all_ of the Rx buffers */
  343. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  344. /* In the reset function, these buffers may have been allocated
  345. * to an SKB, so we need to unmap and free potential storage */
  346. if (rxq->pool[i].skb != NULL) {
  347. pci_unmap_single(priv->pci_dev,
  348. rxq->pool[i].real_dma_addr,
  349. priv->hw_params.rx_buf_size + 256,
  350. PCI_DMA_FROMDEVICE);
  351. priv->alloc_rxb_skb--;
  352. dev_kfree_skb(rxq->pool[i].skb);
  353. rxq->pool[i].skb = NULL;
  354. }
  355. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  356. }
  357. /* Set us so that we have processed and used all buffers, but have
  358. * not restocked the Rx queue with fresh buffers */
  359. rxq->read = rxq->write = 0;
  360. rxq->write_actual = 0;
  361. rxq->free_count = 0;
  362. spin_unlock_irqrestore(&rxq->lock, flags);
  363. }
  364. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  365. {
  366. u32 rb_size;
  367. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  368. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  369. if (!priv->cfg->use_isr_legacy)
  370. rb_timeout = RX_RB_TIMEOUT;
  371. if (priv->cfg->mod_params->amsdu_size_8K)
  372. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  373. else
  374. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  375. /* Stop Rx DMA */
  376. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  377. /* Reset driver's Rx queue write index */
  378. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  379. /* Tell device where to find RBD circular buffer in DRAM */
  380. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  381. (u32)(rxq->dma_addr >> 8));
  382. /* Tell device where in DRAM to update its Rx status */
  383. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  384. rxq->rb_stts_dma >> 4);
  385. /* Enable Rx DMA
  386. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  387. * the credit mechanism in 5000 HW RX FIFO
  388. * Direct rx interrupts to hosts
  389. * Rx buffer size 4 or 8k
  390. * RB timeout 0x10
  391. * 256 RBDs
  392. */
  393. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  394. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  395. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  396. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  397. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  398. rb_size|
  399. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  400. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  401. iwl_write32(priv, CSR_INT_COALESCING, 0x40);
  402. return 0;
  403. }
  404. int iwl_rxq_stop(struct iwl_priv *priv)
  405. {
  406. /* stop Rx DMA */
  407. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  408. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  409. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  410. return 0;
  411. }
  412. EXPORT_SYMBOL(iwl_rxq_stop);
  413. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  414. struct iwl_rx_mem_buffer *rxb)
  415. {
  416. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  417. struct iwl_missed_beacon_notif *missed_beacon;
  418. missed_beacon = &pkt->u.missed_beacon;
  419. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  420. IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  421. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  422. le32_to_cpu(missed_beacon->total_missed_becons),
  423. le32_to_cpu(missed_beacon->num_recvd_beacons),
  424. le32_to_cpu(missed_beacon->num_expected_beacons));
  425. if (!test_bit(STATUS_SCANNING, &priv->status))
  426. iwl_init_sensitivity(priv);
  427. }
  428. }
  429. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  430. /* Calculate noise level, based on measurements during network silence just
  431. * before arriving beacon. This measurement can be done only if we know
  432. * exactly when to expect beacons, therefore only when we're associated. */
  433. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  434. {
  435. struct statistics_rx_non_phy *rx_info
  436. = &(priv->statistics.rx.general);
  437. int num_active_rx = 0;
  438. int total_silence = 0;
  439. int bcn_silence_a =
  440. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  441. int bcn_silence_b =
  442. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  443. int bcn_silence_c =
  444. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  445. if (bcn_silence_a) {
  446. total_silence += bcn_silence_a;
  447. num_active_rx++;
  448. }
  449. if (bcn_silence_b) {
  450. total_silence += bcn_silence_b;
  451. num_active_rx++;
  452. }
  453. if (bcn_silence_c) {
  454. total_silence += bcn_silence_c;
  455. num_active_rx++;
  456. }
  457. /* Average among active antennas */
  458. if (num_active_rx)
  459. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  460. else
  461. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  462. IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n",
  463. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  464. priv->last_rx_noise);
  465. }
  466. #define REG_RECALIB_PERIOD (60)
  467. void iwl_rx_statistics(struct iwl_priv *priv,
  468. struct iwl_rx_mem_buffer *rxb)
  469. {
  470. int change;
  471. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  472. IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
  473. (int)sizeof(priv->statistics), pkt->len);
  474. change = ((priv->statistics.general.temperature !=
  475. pkt->u.stats.general.temperature) ||
  476. ((priv->statistics.flag &
  477. STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
  478. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
  479. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  480. set_bit(STATUS_STATISTICS, &priv->status);
  481. /* Reschedule the statistics timer to occur in
  482. * REG_RECALIB_PERIOD seconds to ensure we get a
  483. * thermal update even if the uCode doesn't give
  484. * us one */
  485. mod_timer(&priv->statistics_periodic, jiffies +
  486. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  487. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  488. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  489. iwl_rx_calc_noise(priv);
  490. queue_work(priv->workqueue, &priv->run_time_calib_work);
  491. }
  492. iwl_leds_background(priv);
  493. if (priv->cfg->ops->lib->temp_ops.temperature && change)
  494. priv->cfg->ops->lib->temp_ops.temperature(priv);
  495. }
  496. EXPORT_SYMBOL(iwl_rx_statistics);
  497. #define PERFECT_RSSI (-20) /* dBm */
  498. #define WORST_RSSI (-95) /* dBm */
  499. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  500. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  501. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  502. * about formulas used below. */
  503. static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
  504. {
  505. int sig_qual;
  506. int degradation = PERFECT_RSSI - rssi_dbm;
  507. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  508. * as indicator; formula is (signal dbm - noise dbm).
  509. * SNR at or above 40 is a great signal (100%).
  510. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  511. * Weakest usable signal is usually 10 - 15 dB SNR. */
  512. if (noise_dbm) {
  513. if (rssi_dbm - noise_dbm >= 40)
  514. return 100;
  515. else if (rssi_dbm < noise_dbm)
  516. return 0;
  517. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  518. /* Else use just the signal level.
  519. * This formula is a least squares fit of data points collected and
  520. * compared with a reference system that had a percentage (%) display
  521. * for signal quality. */
  522. } else
  523. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  524. (15 * RSSI_RANGE + 62 * degradation)) /
  525. (RSSI_RANGE * RSSI_RANGE);
  526. if (sig_qual > 100)
  527. sig_qual = 100;
  528. else if (sig_qual < 1)
  529. sig_qual = 0;
  530. return sig_qual;
  531. }
  532. /* Calc max signal level (dBm) among 3 possible receivers */
  533. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  534. struct iwl_rx_phy_res *rx_resp)
  535. {
  536. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  537. }
  538. #ifdef CONFIG_IWLWIFI_DEBUG
  539. /**
  540. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  541. *
  542. * You may hack this function to show different aspects of received frames,
  543. * including selective frame dumps.
  544. * group100 parameter selects whether to show 1 out of 100 good data frames.
  545. * All beacon and probe response frames are printed.
  546. */
  547. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  548. struct iwl_rx_phy_res *phy_res, u16 length,
  549. struct ieee80211_hdr *header, int group100)
  550. {
  551. u32 to_us;
  552. u32 print_summary = 0;
  553. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  554. u32 hundred = 0;
  555. u32 dataframe = 0;
  556. __le16 fc;
  557. u16 seq_ctl;
  558. u16 channel;
  559. u16 phy_flags;
  560. u32 rate_n_flags;
  561. u32 tsf_low;
  562. int rssi;
  563. if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX)))
  564. return;
  565. /* MAC header */
  566. fc = header->frame_control;
  567. seq_ctl = le16_to_cpu(header->seq_ctrl);
  568. /* metadata */
  569. channel = le16_to_cpu(phy_res->channel);
  570. phy_flags = le16_to_cpu(phy_res->phy_flags);
  571. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  572. /* signal statistics */
  573. rssi = iwl_calc_rssi(priv, phy_res);
  574. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  575. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  576. /* if data frame is to us and all is good,
  577. * (optionally) print summary for only 1 out of every 100 */
  578. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  579. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  580. dataframe = 1;
  581. if (!group100)
  582. print_summary = 1; /* print each frame */
  583. else if (priv->framecnt_to_us < 100) {
  584. priv->framecnt_to_us++;
  585. print_summary = 0;
  586. } else {
  587. priv->framecnt_to_us = 0;
  588. print_summary = 1;
  589. hundred = 1;
  590. }
  591. } else {
  592. /* print summary for all other frames */
  593. print_summary = 1;
  594. }
  595. if (print_summary) {
  596. char *title;
  597. int rate_idx;
  598. u32 bitrate;
  599. if (hundred)
  600. title = "100Frames";
  601. else if (ieee80211_has_retry(fc))
  602. title = "Retry";
  603. else if (ieee80211_is_assoc_resp(fc))
  604. title = "AscRsp";
  605. else if (ieee80211_is_reassoc_resp(fc))
  606. title = "RasRsp";
  607. else if (ieee80211_is_probe_resp(fc)) {
  608. title = "PrbRsp";
  609. print_dump = 1; /* dump frame contents */
  610. } else if (ieee80211_is_beacon(fc)) {
  611. title = "Beacon";
  612. print_dump = 1; /* dump frame contents */
  613. } else if (ieee80211_is_atim(fc))
  614. title = "ATIM";
  615. else if (ieee80211_is_auth(fc))
  616. title = "Auth";
  617. else if (ieee80211_is_deauth(fc))
  618. title = "DeAuth";
  619. else if (ieee80211_is_disassoc(fc))
  620. title = "DisAssoc";
  621. else
  622. title = "Frame";
  623. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  624. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  625. bitrate = 0;
  626. WARN_ON_ONCE(1);
  627. } else {
  628. bitrate = iwl_rates[rate_idx].ieee / 2;
  629. }
  630. /* print frame summary.
  631. * MAC addresses show just the last byte (for brevity),
  632. * but you can hack it to show more, if you'd like to. */
  633. if (dataframe)
  634. IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
  635. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  636. title, le16_to_cpu(fc), header->addr1[5],
  637. length, rssi, channel, bitrate);
  638. else {
  639. /* src/dst addresses assume managed mode */
  640. IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  641. "len=%u, rssi=%d, tim=%lu usec, "
  642. "phy=0x%02x, chnl=%d\n",
  643. title, le16_to_cpu(fc), header->addr1[5],
  644. header->addr3[5], length, rssi,
  645. tsf_low - priv->scan_start_tsf,
  646. phy_flags, channel);
  647. }
  648. }
  649. if (print_dump)
  650. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  651. }
  652. #endif
  653. /*
  654. * returns non-zero if packet should be dropped
  655. */
  656. int iwl_set_decrypted_flag(struct iwl_priv *priv,
  657. struct ieee80211_hdr *hdr,
  658. u32 decrypt_res,
  659. struct ieee80211_rx_status *stats)
  660. {
  661. u16 fc = le16_to_cpu(hdr->frame_control);
  662. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  663. return 0;
  664. if (!(fc & IEEE80211_FCTL_PROTECTED))
  665. return 0;
  666. IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res);
  667. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  668. case RX_RES_STATUS_SEC_TYPE_TKIP:
  669. /* The uCode has got a bad phase 1 Key, pushes the packet.
  670. * Decryption will be done in SW. */
  671. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  672. RX_RES_STATUS_BAD_KEY_TTAK)
  673. break;
  674. case RX_RES_STATUS_SEC_TYPE_WEP:
  675. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  676. RX_RES_STATUS_BAD_ICV_MIC) {
  677. /* bad ICV, the packet is destroyed since the
  678. * decryption is inplace, drop it */
  679. IWL_DEBUG_RX(priv, "Packet destroyed\n");
  680. return -1;
  681. }
  682. case RX_RES_STATUS_SEC_TYPE_CCMP:
  683. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  684. RX_RES_STATUS_DECRYPT_OK) {
  685. IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n");
  686. stats->flag |= RX_FLAG_DECRYPTED;
  687. }
  688. break;
  689. default:
  690. break;
  691. }
  692. return 0;
  693. }
  694. EXPORT_SYMBOL(iwl_set_decrypted_flag);
  695. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  696. {
  697. u32 decrypt_out = 0;
  698. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  699. RX_RES_STATUS_STATION_FOUND)
  700. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  701. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  702. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  703. /* packet was not encrypted */
  704. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  705. RX_RES_STATUS_SEC_TYPE_NONE)
  706. return decrypt_out;
  707. /* packet was encrypted with unknown alg */
  708. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  709. RX_RES_STATUS_SEC_TYPE_ERR)
  710. return decrypt_out;
  711. /* decryption was not done in HW */
  712. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  713. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  714. return decrypt_out;
  715. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  716. case RX_RES_STATUS_SEC_TYPE_CCMP:
  717. /* alg is CCM: check MIC only */
  718. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  719. /* Bad MIC */
  720. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  721. else
  722. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  723. break;
  724. case RX_RES_STATUS_SEC_TYPE_TKIP:
  725. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  726. /* Bad TTAK */
  727. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  728. break;
  729. }
  730. /* fall through if TTAK OK */
  731. default:
  732. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  733. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  734. else
  735. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  736. break;
  737. };
  738. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  739. decrypt_in, decrypt_out);
  740. return decrypt_out;
  741. }
  742. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  743. int include_phy,
  744. struct iwl_rx_mem_buffer *rxb,
  745. struct ieee80211_rx_status *stats)
  746. {
  747. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  748. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  749. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  750. struct ieee80211_hdr *hdr;
  751. u16 len;
  752. __le32 *rx_end;
  753. unsigned int skblen;
  754. u32 ampdu_status;
  755. u32 ampdu_status_legacy;
  756. if (!include_phy && priv->last_phy_res[0])
  757. rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  758. if (!rx_start) {
  759. IWL_ERR(priv, "MPDU frame without a PHY data\n");
  760. return;
  761. }
  762. if (include_phy) {
  763. hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] +
  764. rx_start->cfg_phy_cnt);
  765. len = le16_to_cpu(rx_start->byte_count);
  766. rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] +
  767. sizeof(struct iwl_rx_phy_res) +
  768. rx_start->cfg_phy_cnt + len);
  769. } else {
  770. struct iwl4965_rx_mpdu_res_start *amsdu =
  771. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  772. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  773. sizeof(struct iwl4965_rx_mpdu_res_start));
  774. len = le16_to_cpu(amsdu->byte_count);
  775. rx_start->byte_count = amsdu->byte_count;
  776. rx_end = (__le32 *) (((u8 *) hdr) + len);
  777. }
  778. ampdu_status = le32_to_cpu(*rx_end);
  779. skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32);
  780. if (!include_phy) {
  781. /* New status scheme, need to translate */
  782. ampdu_status_legacy = ampdu_status;
  783. ampdu_status = iwl_translate_rx_status(priv, ampdu_status);
  784. }
  785. /* start from MAC */
  786. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  787. skb_put(rxb->skb, len); /* end where data ends */
  788. /* We only process data packets if the interface is open */
  789. if (unlikely(!priv->is_open)) {
  790. IWL_DEBUG_DROP_LIMIT(priv,
  791. "Dropping packet while interface is not open.\n");
  792. return;
  793. }
  794. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  795. /* in case of HW accelerated crypto and bad decryption, drop */
  796. if (!priv->cfg->mod_params->sw_crypto &&
  797. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  798. return;
  799. iwl_update_stats(priv, false, hdr->frame_control, len);
  800. memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
  801. ieee80211_rx_irqsafe(priv->hw, rxb->skb);
  802. priv->alloc_rxb_skb--;
  803. rxb->skb = NULL;
  804. }
  805. /* This is necessary only for a number of statistics, see the caller. */
  806. static int iwl_is_network_packet(struct iwl_priv *priv,
  807. struct ieee80211_hdr *header)
  808. {
  809. /* Filter incoming packets to determine if they are targeted toward
  810. * this network, discarding packets coming from ourselves */
  811. switch (priv->iw_mode) {
  812. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  813. /* packets to our IBSS update information */
  814. return !compare_ether_addr(header->addr3, priv->bssid);
  815. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  816. /* packets to our IBSS update information */
  817. return !compare_ether_addr(header->addr2, priv->bssid);
  818. default:
  819. return 1;
  820. }
  821. }
  822. /* Called for REPLY_RX (legacy ABG frames), or
  823. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  824. void iwl_rx_reply_rx(struct iwl_priv *priv,
  825. struct iwl_rx_mem_buffer *rxb)
  826. {
  827. struct ieee80211_hdr *header;
  828. struct ieee80211_rx_status rx_status;
  829. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  830. /* Use phy data (Rx signal strength, etc.) contained within
  831. * this rx packet for legacy frames,
  832. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  833. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  834. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  835. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) :
  836. (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  837. __le32 *rx_end;
  838. unsigned int len = 0;
  839. u16 fc;
  840. u8 network_packet;
  841. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  842. rx_status.freq =
  843. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  844. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  845. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  846. rx_status.rate_idx =
  847. iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  848. if (rx_status.band == IEEE80211_BAND_5GHZ)
  849. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  850. rx_status.flag = 0;
  851. /* TSF isn't reliable. In order to allow smooth user experience,
  852. * this W/A doesn't propagate it to the mac80211 */
  853. /*rx_status.flag |= RX_FLAG_TSFT;*/
  854. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  855. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  856. rx_start->cfg_phy_cnt);
  857. return;
  858. }
  859. if (!include_phy) {
  860. if (priv->last_phy_res[0])
  861. rx_start = (struct iwl_rx_phy_res *)
  862. &priv->last_phy_res[1];
  863. else
  864. rx_start = NULL;
  865. }
  866. if (!rx_start) {
  867. IWL_ERR(priv, "MPDU frame without a PHY data\n");
  868. return;
  869. }
  870. if (include_phy) {
  871. header = (struct ieee80211_hdr *)((u8 *) &rx_start[1]
  872. + rx_start->cfg_phy_cnt);
  873. len = le16_to_cpu(rx_start->byte_count);
  874. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  875. sizeof(struct iwl_rx_phy_res) + len);
  876. } else {
  877. struct iwl4965_rx_mpdu_res_start *amsdu =
  878. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  879. header = (void *)(pkt->u.raw +
  880. sizeof(struct iwl4965_rx_mpdu_res_start));
  881. len = le16_to_cpu(amsdu->byte_count);
  882. rx_end = (__le32 *) (pkt->u.raw +
  883. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  884. }
  885. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  886. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  887. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  888. le32_to_cpu(*rx_end));
  889. return;
  890. }
  891. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  892. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  893. rx_status.signal = iwl_calc_rssi(priv, rx_start);
  894. /* Meaningful noise values are available only from beacon statistics,
  895. * which are gathered only when associated, and indicate noise
  896. * only for the associated network channel ...
  897. * Ignore these noise values while scanning (other channels) */
  898. if (iwl_is_associated(priv) &&
  899. !test_bit(STATUS_SCANNING, &priv->status)) {
  900. rx_status.noise = priv->last_rx_noise;
  901. rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
  902. rx_status.noise);
  903. } else {
  904. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  905. rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
  906. }
  907. /* Reset beacon noise level if not associated. */
  908. if (!iwl_is_associated(priv))
  909. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  910. /* Set "1" to report good data frames in groups of 100 */
  911. #ifdef CONFIG_IWLWIFI_DEBUG
  912. if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX))
  913. iwl_dbg_report_frame(priv, rx_start, len, header, 1);
  914. #endif
  915. iwl_dbg_log_rx_data_frame(priv, len, header);
  916. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, qual %d, TSF %llu\n",
  917. rx_status.signal, rx_status.noise, rx_status.qual,
  918. (unsigned long long)rx_status.mactime);
  919. /*
  920. * "antenna number"
  921. *
  922. * It seems that the antenna field in the phy flags value
  923. * is actually a bit field. This is undefined by radiotap,
  924. * it wants an actual antenna number but I always get "7"
  925. * for most legacy frames I receive indicating that the
  926. * same frame was received on all three RX chains.
  927. *
  928. * I think this field should be removed in favor of a
  929. * new 802.11n radiotap field "RX chains" that is defined
  930. * as a bitmask.
  931. */
  932. rx_status.antenna = le16_to_cpu(rx_start->phy_flags &
  933. RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  934. /* set the preamble flag if appropriate */
  935. if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  936. rx_status.flag |= RX_FLAG_SHORTPRE;
  937. network_packet = iwl_is_network_packet(priv, header);
  938. if (network_packet) {
  939. priv->last_rx_rssi = rx_status.signal;
  940. priv->last_beacon_time = priv->ucode_beacon_time;
  941. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  942. }
  943. fc = le16_to_cpu(header->frame_control);
  944. switch (fc & IEEE80211_FCTL_FTYPE) {
  945. case IEEE80211_FTYPE_MGMT:
  946. case IEEE80211_FTYPE_DATA:
  947. if (priv->iw_mode == NL80211_IFTYPE_AP)
  948. iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  949. header->addr2);
  950. /* fall through */
  951. default:
  952. iwl_pass_packet_to_mac80211(priv, include_phy, rxb,
  953. &rx_status);
  954. break;
  955. }
  956. }
  957. EXPORT_SYMBOL(iwl_rx_reply_rx);
  958. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  959. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  960. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  961. struct iwl_rx_mem_buffer *rxb)
  962. {
  963. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  964. priv->last_phy_res[0] = 1;
  965. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  966. sizeof(struct iwl_rx_phy_res));
  967. }
  968. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);