mthca_main.c 32 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  52. int mthca_debug_level = 0;
  53. module_param_named(debug_level, mthca_debug_level, int, 0644);
  54. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  55. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  56. #ifdef CONFIG_PCI_MSI
  57. static int msi_x = 0;
  58. module_param(msi_x, int, 0444);
  59. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  60. static int msi = 0;
  61. module_param(msi, int, 0444);
  62. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  63. #else /* CONFIG_PCI_MSI */
  64. #define msi_x (0)
  65. #define msi (0)
  66. #endif /* CONFIG_PCI_MSI */
  67. static const char mthca_version[] __devinitdata =
  68. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  69. DRV_VERSION " (" DRV_RELDATE ")\n";
  70. static struct mthca_profile default_profile = {
  71. .num_qp = 1 << 16,
  72. .rdb_per_qp = 4,
  73. .num_cq = 1 << 16,
  74. .num_mcg = 1 << 13,
  75. .num_mpt = 1 << 17,
  76. .num_mtt = 1 << 20,
  77. .num_udav = 1 << 15, /* Tavor only */
  78. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  79. .uarc_size = 1 << 18, /* Arbel only */
  80. };
  81. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  82. {
  83. int cap;
  84. u16 val;
  85. /* First try to max out Read Byte Count */
  86. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  87. if (cap) {
  88. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  89. mthca_err(mdev, "Couldn't read PCI-X command register, "
  90. "aborting.\n");
  91. return -ENODEV;
  92. }
  93. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  94. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  95. mthca_err(mdev, "Couldn't write PCI-X command register, "
  96. "aborting.\n");
  97. return -ENODEV;
  98. }
  99. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  100. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  101. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  102. if (cap) {
  103. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  104. mthca_err(mdev, "Couldn't read PCI Express device control "
  105. "register, aborting.\n");
  106. return -ENODEV;
  107. }
  108. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  109. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  110. mthca_err(mdev, "Couldn't write PCI Express device control "
  111. "register, aborting.\n");
  112. return -ENODEV;
  113. }
  114. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  115. mthca_info(mdev, "No PCI Express capability, "
  116. "not setting Max Read Request Size.\n");
  117. return 0;
  118. }
  119. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  120. {
  121. int err;
  122. u8 status;
  123. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  124. if (err) {
  125. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  126. return err;
  127. }
  128. if (status) {
  129. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  130. "aborting.\n", status);
  131. return -EINVAL;
  132. }
  133. if (dev_lim->min_page_sz > PAGE_SIZE) {
  134. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  135. "kernel PAGE_SIZE of %ld, aborting.\n",
  136. dev_lim->min_page_sz, PAGE_SIZE);
  137. return -ENODEV;
  138. }
  139. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  140. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  141. "aborting.\n",
  142. dev_lim->num_ports, MTHCA_MAX_PORTS);
  143. return -ENODEV;
  144. }
  145. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  146. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  147. "PCI resource 2 size of 0x%lx, aborting.\n",
  148. dev_lim->uar_size, pci_resource_len(mdev->pdev, 2));
  149. return -ENODEV;
  150. }
  151. mdev->limits.num_ports = dev_lim->num_ports;
  152. mdev->limits.vl_cap = dev_lim->max_vl;
  153. mdev->limits.mtu_cap = dev_lim->max_mtu;
  154. mdev->limits.gid_table_len = dev_lim->max_gids;
  155. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  156. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  157. mdev->limits.max_sg = dev_lim->max_sg;
  158. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  159. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  160. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  161. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  162. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  163. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  164. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  165. /*
  166. * Subtract 1 from the limit because we need to allocate a
  167. * spare CQE so the HCA HW can tell the difference between an
  168. * empty CQ and a full CQ.
  169. */
  170. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  171. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  172. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  173. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  174. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  175. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  176. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  177. mdev->limits.port_width_cap = dev_lim->max_port_width;
  178. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  179. mdev->limits.flags = dev_lim->flags;
  180. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  181. May be doable since hardware supports it for SRQ.
  182. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  183. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  184. supported by driver. */
  185. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  186. IB_DEVICE_PORT_ACTIVE_EVENT |
  187. IB_DEVICE_SYS_IMAGE_GUID |
  188. IB_DEVICE_RC_RNR_NAK_GEN;
  189. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  190. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  191. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  192. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  193. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  194. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  195. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  196. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  197. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  198. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  199. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  200. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  201. return 0;
  202. }
  203. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  204. {
  205. u8 status;
  206. int err;
  207. struct mthca_dev_lim dev_lim;
  208. struct mthca_profile profile;
  209. struct mthca_init_hca_param init_hca;
  210. err = mthca_SYS_EN(mdev, &status);
  211. if (err) {
  212. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  213. return err;
  214. }
  215. if (status) {
  216. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  217. "aborting.\n", status);
  218. return -EINVAL;
  219. }
  220. err = mthca_QUERY_FW(mdev, &status);
  221. if (err) {
  222. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  223. goto err_disable;
  224. }
  225. if (status) {
  226. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  227. "aborting.\n", status);
  228. err = -EINVAL;
  229. goto err_disable;
  230. }
  231. err = mthca_QUERY_DDR(mdev, &status);
  232. if (err) {
  233. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  234. goto err_disable;
  235. }
  236. if (status) {
  237. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  238. "aborting.\n", status);
  239. err = -EINVAL;
  240. goto err_disable;
  241. }
  242. err = mthca_dev_lim(mdev, &dev_lim);
  243. if (err) {
  244. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  245. goto err_disable;
  246. }
  247. profile = default_profile;
  248. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  249. profile.uarc_size = 0;
  250. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  251. profile.num_srq = dev_lim.max_srqs;
  252. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  253. if (err < 0)
  254. goto err_disable;
  255. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  256. if (err) {
  257. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  258. goto err_disable;
  259. }
  260. if (status) {
  261. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  262. "aborting.\n", status);
  263. err = -EINVAL;
  264. goto err_disable;
  265. }
  266. return 0;
  267. err_disable:
  268. mthca_SYS_DIS(mdev, &status);
  269. return err;
  270. }
  271. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  272. {
  273. u8 status;
  274. int err;
  275. /* FIXME: use HCA-attached memory for FW if present */
  276. mdev->fw.arbel.fw_icm =
  277. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  278. GFP_HIGHUSER | __GFP_NOWARN);
  279. if (!mdev->fw.arbel.fw_icm) {
  280. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  281. return -ENOMEM;
  282. }
  283. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  284. if (err) {
  285. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  286. goto err_free;
  287. }
  288. if (status) {
  289. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  290. err = -EINVAL;
  291. goto err_free;
  292. }
  293. err = mthca_RUN_FW(mdev, &status);
  294. if (err) {
  295. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  296. goto err_unmap_fa;
  297. }
  298. if (status) {
  299. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  300. err = -EINVAL;
  301. goto err_unmap_fa;
  302. }
  303. return 0;
  304. err_unmap_fa:
  305. mthca_UNMAP_FA(mdev, &status);
  306. err_free:
  307. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  308. return err;
  309. }
  310. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  311. struct mthca_dev_lim *dev_lim,
  312. struct mthca_init_hca_param *init_hca,
  313. u64 icm_size)
  314. {
  315. u64 aux_pages;
  316. u8 status;
  317. int err;
  318. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  319. if (err) {
  320. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  321. return err;
  322. }
  323. if (status) {
  324. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  325. "aborting.\n", status);
  326. return -EINVAL;
  327. }
  328. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  329. (unsigned long long) icm_size >> 10,
  330. (unsigned long long) aux_pages << 2);
  331. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  332. GFP_HIGHUSER | __GFP_NOWARN);
  333. if (!mdev->fw.arbel.aux_icm) {
  334. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  335. return -ENOMEM;
  336. }
  337. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  338. if (err) {
  339. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  340. goto err_free_aux;
  341. }
  342. if (status) {
  343. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  344. err = -EINVAL;
  345. goto err_free_aux;
  346. }
  347. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  348. if (err) {
  349. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  350. goto err_unmap_aux;
  351. }
  352. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  353. MTHCA_MTT_SEG_SIZE,
  354. mdev->limits.num_mtt_segs,
  355. mdev->limits.reserved_mtts, 1);
  356. if (!mdev->mr_table.mtt_table) {
  357. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  358. err = -ENOMEM;
  359. goto err_unmap_eq;
  360. }
  361. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  362. dev_lim->mpt_entry_sz,
  363. mdev->limits.num_mpts,
  364. mdev->limits.reserved_mrws, 1);
  365. if (!mdev->mr_table.mpt_table) {
  366. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  367. err = -ENOMEM;
  368. goto err_unmap_mtt;
  369. }
  370. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  371. dev_lim->qpc_entry_sz,
  372. mdev->limits.num_qps,
  373. mdev->limits.reserved_qps, 0);
  374. if (!mdev->qp_table.qp_table) {
  375. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  376. err = -ENOMEM;
  377. goto err_unmap_mpt;
  378. }
  379. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  380. dev_lim->eqpc_entry_sz,
  381. mdev->limits.num_qps,
  382. mdev->limits.reserved_qps, 0);
  383. if (!mdev->qp_table.eqp_table) {
  384. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  385. err = -ENOMEM;
  386. goto err_unmap_qp;
  387. }
  388. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  389. MTHCA_RDB_ENTRY_SIZE,
  390. mdev->limits.num_qps <<
  391. mdev->qp_table.rdb_shift,
  392. 0, 0);
  393. if (!mdev->qp_table.rdb_table) {
  394. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  395. err = -ENOMEM;
  396. goto err_unmap_eqp;
  397. }
  398. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  399. dev_lim->cqc_entry_sz,
  400. mdev->limits.num_cqs,
  401. mdev->limits.reserved_cqs, 0);
  402. if (!mdev->cq_table.table) {
  403. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  404. err = -ENOMEM;
  405. goto err_unmap_rdb;
  406. }
  407. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  408. mdev->srq_table.table =
  409. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  410. dev_lim->srq_entry_sz,
  411. mdev->limits.num_srqs,
  412. mdev->limits.reserved_srqs, 0);
  413. if (!mdev->srq_table.table) {
  414. mthca_err(mdev, "Failed to map SRQ context memory, "
  415. "aborting.\n");
  416. err = -ENOMEM;
  417. goto err_unmap_cq;
  418. }
  419. }
  420. /*
  421. * It's not strictly required, but for simplicity just map the
  422. * whole multicast group table now. The table isn't very big
  423. * and it's a lot easier than trying to track ref counts.
  424. */
  425. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  426. MTHCA_MGM_ENTRY_SIZE,
  427. mdev->limits.num_mgms +
  428. mdev->limits.num_amgms,
  429. mdev->limits.num_mgms +
  430. mdev->limits.num_amgms,
  431. 0);
  432. if (!mdev->mcg_table.table) {
  433. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  434. err = -ENOMEM;
  435. goto err_unmap_srq;
  436. }
  437. return 0;
  438. err_unmap_srq:
  439. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  440. mthca_free_icm_table(mdev, mdev->srq_table.table);
  441. err_unmap_cq:
  442. mthca_free_icm_table(mdev, mdev->cq_table.table);
  443. err_unmap_rdb:
  444. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  445. err_unmap_eqp:
  446. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  447. err_unmap_qp:
  448. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  449. err_unmap_mpt:
  450. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  451. err_unmap_mtt:
  452. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  453. err_unmap_eq:
  454. mthca_unmap_eq_icm(mdev);
  455. err_unmap_aux:
  456. mthca_UNMAP_ICM_AUX(mdev, &status);
  457. err_free_aux:
  458. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  459. return err;
  460. }
  461. static void mthca_free_icms(struct mthca_dev *mdev)
  462. {
  463. u8 status;
  464. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  465. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  466. mthca_free_icm_table(mdev, mdev->srq_table.table);
  467. mthca_free_icm_table(mdev, mdev->cq_table.table);
  468. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  469. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  470. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  471. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  472. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  473. mthca_unmap_eq_icm(mdev);
  474. mthca_UNMAP_ICM_AUX(mdev, &status);
  475. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  476. }
  477. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  478. {
  479. struct mthca_dev_lim dev_lim;
  480. struct mthca_profile profile;
  481. struct mthca_init_hca_param init_hca;
  482. u64 icm_size;
  483. u8 status;
  484. int err;
  485. err = mthca_QUERY_FW(mdev, &status);
  486. if (err) {
  487. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  488. return err;
  489. }
  490. if (status) {
  491. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  492. "aborting.\n", status);
  493. return -EINVAL;
  494. }
  495. err = mthca_ENABLE_LAM(mdev, &status);
  496. if (err) {
  497. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  498. return err;
  499. }
  500. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  501. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  502. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  503. } else if (status) {
  504. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  505. "aborting.\n", status);
  506. return -EINVAL;
  507. }
  508. err = mthca_load_fw(mdev);
  509. if (err) {
  510. mthca_err(mdev, "Failed to start FW, aborting.\n");
  511. goto err_disable;
  512. }
  513. err = mthca_dev_lim(mdev, &dev_lim);
  514. if (err) {
  515. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  516. goto err_stop_fw;
  517. }
  518. profile = default_profile;
  519. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  520. profile.num_udav = 0;
  521. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  522. profile.num_srq = dev_lim.max_srqs;
  523. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  524. if ((int) icm_size < 0) {
  525. err = icm_size;
  526. goto err_stop_fw;
  527. }
  528. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  529. if (err)
  530. goto err_stop_fw;
  531. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  532. if (err) {
  533. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  534. goto err_free_icm;
  535. }
  536. if (status) {
  537. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  538. "aborting.\n", status);
  539. err = -EINVAL;
  540. goto err_free_icm;
  541. }
  542. return 0;
  543. err_free_icm:
  544. mthca_free_icms(mdev);
  545. err_stop_fw:
  546. mthca_UNMAP_FA(mdev, &status);
  547. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  548. err_disable:
  549. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  550. mthca_DISABLE_LAM(mdev, &status);
  551. return err;
  552. }
  553. static void mthca_close_hca(struct mthca_dev *mdev)
  554. {
  555. u8 status;
  556. mthca_CLOSE_HCA(mdev, 0, &status);
  557. if (mthca_is_memfree(mdev)) {
  558. mthca_free_icms(mdev);
  559. mthca_UNMAP_FA(mdev, &status);
  560. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  561. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  562. mthca_DISABLE_LAM(mdev, &status);
  563. } else
  564. mthca_SYS_DIS(mdev, &status);
  565. }
  566. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  567. {
  568. u8 status;
  569. int err;
  570. struct mthca_adapter adapter;
  571. if (mthca_is_memfree(mdev))
  572. err = mthca_init_arbel(mdev);
  573. else
  574. err = mthca_init_tavor(mdev);
  575. if (err)
  576. return err;
  577. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  578. if (err) {
  579. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  580. goto err_close;
  581. }
  582. if (status) {
  583. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  584. "aborting.\n", status);
  585. err = -EINVAL;
  586. goto err_close;
  587. }
  588. mdev->eq_table.inta_pin = adapter.inta_pin;
  589. mdev->rev_id = adapter.revision_id;
  590. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  591. return 0;
  592. err_close:
  593. mthca_close_hca(mdev);
  594. return err;
  595. }
  596. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  597. {
  598. int err;
  599. u8 status;
  600. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  601. err = mthca_init_uar_table(dev);
  602. if (err) {
  603. mthca_err(dev, "Failed to initialize "
  604. "user access region table, aborting.\n");
  605. return err;
  606. }
  607. err = mthca_uar_alloc(dev, &dev->driver_uar);
  608. if (err) {
  609. mthca_err(dev, "Failed to allocate driver access region, "
  610. "aborting.\n");
  611. goto err_uar_table_free;
  612. }
  613. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  614. if (!dev->kar) {
  615. mthca_err(dev, "Couldn't map kernel access region, "
  616. "aborting.\n");
  617. err = -ENOMEM;
  618. goto err_uar_free;
  619. }
  620. err = mthca_init_pd_table(dev);
  621. if (err) {
  622. mthca_err(dev, "Failed to initialize "
  623. "protection domain table, aborting.\n");
  624. goto err_kar_unmap;
  625. }
  626. err = mthca_init_mr_table(dev);
  627. if (err) {
  628. mthca_err(dev, "Failed to initialize "
  629. "memory region table, aborting.\n");
  630. goto err_pd_table_free;
  631. }
  632. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  633. if (err) {
  634. mthca_err(dev, "Failed to create driver PD, "
  635. "aborting.\n");
  636. goto err_mr_table_free;
  637. }
  638. err = mthca_init_eq_table(dev);
  639. if (err) {
  640. mthca_err(dev, "Failed to initialize "
  641. "event queue table, aborting.\n");
  642. goto err_pd_free;
  643. }
  644. err = mthca_cmd_use_events(dev);
  645. if (err) {
  646. mthca_err(dev, "Failed to switch to event-driven "
  647. "firmware commands, aborting.\n");
  648. goto err_eq_table_free;
  649. }
  650. err = mthca_NOP(dev, &status);
  651. if (err || status) {
  652. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  653. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  654. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  655. dev->pdev->irq);
  656. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  657. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  658. else
  659. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  660. goto err_cmd_poll;
  661. }
  662. mthca_dbg(dev, "NOP command IRQ test passed\n");
  663. err = mthca_init_cq_table(dev);
  664. if (err) {
  665. mthca_err(dev, "Failed to initialize "
  666. "completion queue table, aborting.\n");
  667. goto err_cmd_poll;
  668. }
  669. err = mthca_init_srq_table(dev);
  670. if (err) {
  671. mthca_err(dev, "Failed to initialize "
  672. "shared receive queue table, aborting.\n");
  673. goto err_cq_table_free;
  674. }
  675. err = mthca_init_qp_table(dev);
  676. if (err) {
  677. mthca_err(dev, "Failed to initialize "
  678. "queue pair table, aborting.\n");
  679. goto err_srq_table_free;
  680. }
  681. err = mthca_init_av_table(dev);
  682. if (err) {
  683. mthca_err(dev, "Failed to initialize "
  684. "address vector table, aborting.\n");
  685. goto err_qp_table_free;
  686. }
  687. err = mthca_init_mcg_table(dev);
  688. if (err) {
  689. mthca_err(dev, "Failed to initialize "
  690. "multicast group table, aborting.\n");
  691. goto err_av_table_free;
  692. }
  693. return 0;
  694. err_av_table_free:
  695. mthca_cleanup_av_table(dev);
  696. err_qp_table_free:
  697. mthca_cleanup_qp_table(dev);
  698. err_srq_table_free:
  699. mthca_cleanup_srq_table(dev);
  700. err_cq_table_free:
  701. mthca_cleanup_cq_table(dev);
  702. err_cmd_poll:
  703. mthca_cmd_use_polling(dev);
  704. err_eq_table_free:
  705. mthca_cleanup_eq_table(dev);
  706. err_pd_free:
  707. mthca_pd_free(dev, &dev->driver_pd);
  708. err_mr_table_free:
  709. mthca_cleanup_mr_table(dev);
  710. err_pd_table_free:
  711. mthca_cleanup_pd_table(dev);
  712. err_kar_unmap:
  713. iounmap(dev->kar);
  714. err_uar_free:
  715. mthca_uar_free(dev, &dev->driver_uar);
  716. err_uar_table_free:
  717. mthca_cleanup_uar_table(dev);
  718. return err;
  719. }
  720. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  721. int ddr_hidden)
  722. {
  723. int err;
  724. /*
  725. * We can't just use pci_request_regions() because the MSI-X
  726. * table is right in the middle of the first BAR. If we did
  727. * pci_request_region and grab all of the first BAR, then
  728. * setting up MSI-X would fail, since the PCI core wants to do
  729. * request_mem_region on the MSI-X vector table.
  730. *
  731. * So just request what we need right now, and request any
  732. * other regions we need when setting up EQs.
  733. */
  734. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  735. MTHCA_HCR_SIZE, DRV_NAME))
  736. return -EBUSY;
  737. err = pci_request_region(pdev, 2, DRV_NAME);
  738. if (err)
  739. goto err_bar2_failed;
  740. if (!ddr_hidden) {
  741. err = pci_request_region(pdev, 4, DRV_NAME);
  742. if (err)
  743. goto err_bar4_failed;
  744. }
  745. return 0;
  746. err_bar4_failed:
  747. pci_release_region(pdev, 2);
  748. err_bar2_failed:
  749. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  750. MTHCA_HCR_SIZE);
  751. return err;
  752. }
  753. static void mthca_release_regions(struct pci_dev *pdev,
  754. int ddr_hidden)
  755. {
  756. if (!ddr_hidden)
  757. pci_release_region(pdev, 4);
  758. pci_release_region(pdev, 2);
  759. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  760. MTHCA_HCR_SIZE);
  761. }
  762. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  763. {
  764. struct msix_entry entries[3];
  765. int err;
  766. entries[0].entry = 0;
  767. entries[1].entry = 1;
  768. entries[2].entry = 2;
  769. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  770. if (err) {
  771. if (err > 0)
  772. mthca_info(mdev, "Only %d MSI-X vectors available, "
  773. "not using MSI-X\n", err);
  774. return err;
  775. }
  776. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  777. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  778. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  779. return 0;
  780. }
  781. /* Types of supported HCA */
  782. enum {
  783. TAVOR, /* MT23108 */
  784. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  785. ARBEL_NATIVE, /* MT25208 with extended features */
  786. SINAI /* MT25204 */
  787. };
  788. #define MTHCA_FW_VER(major, minor, subminor) \
  789. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  790. static struct {
  791. u64 latest_fw;
  792. u32 flags;
  793. } mthca_hca_table[] = {
  794. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 4, 0),
  795. .flags = 0 },
  796. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 400),
  797. .flags = MTHCA_FLAG_PCIE },
  798. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0),
  799. .flags = MTHCA_FLAG_MEMFREE |
  800. MTHCA_FLAG_PCIE },
  801. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 800),
  802. .flags = MTHCA_FLAG_MEMFREE |
  803. MTHCA_FLAG_PCIE |
  804. MTHCA_FLAG_SINAI_OPT }
  805. };
  806. static int __devinit mthca_init_one(struct pci_dev *pdev,
  807. const struct pci_device_id *id)
  808. {
  809. static int mthca_version_printed = 0;
  810. int ddr_hidden = 0;
  811. int err;
  812. struct mthca_dev *mdev;
  813. if (!mthca_version_printed) {
  814. printk(KERN_INFO "%s", mthca_version);
  815. ++mthca_version_printed;
  816. }
  817. printk(KERN_INFO PFX "Initializing %s\n",
  818. pci_name(pdev));
  819. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  820. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  821. pci_name(pdev), id->driver_data);
  822. return -ENODEV;
  823. }
  824. err = pci_enable_device(pdev);
  825. if (err) {
  826. dev_err(&pdev->dev, "Cannot enable PCI device, "
  827. "aborting.\n");
  828. return err;
  829. }
  830. /*
  831. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  832. * be present)
  833. */
  834. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  835. pci_resource_len(pdev, 0) != 1 << 20) {
  836. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  837. err = -ENODEV;
  838. goto err_disable_pdev;
  839. }
  840. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  841. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  842. err = -ENODEV;
  843. goto err_disable_pdev;
  844. }
  845. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  846. ddr_hidden = 1;
  847. err = mthca_request_regions(pdev, ddr_hidden);
  848. if (err) {
  849. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  850. "aborting.\n");
  851. goto err_disable_pdev;
  852. }
  853. pci_set_master(pdev);
  854. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  855. if (err) {
  856. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  857. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  858. if (err) {
  859. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  860. goto err_free_res;
  861. }
  862. }
  863. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  864. if (err) {
  865. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  866. "consistent PCI DMA mask.\n");
  867. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  868. if (err) {
  869. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  870. "aborting.\n");
  871. goto err_free_res;
  872. }
  873. }
  874. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  875. if (!mdev) {
  876. dev_err(&pdev->dev, "Device struct alloc failed, "
  877. "aborting.\n");
  878. err = -ENOMEM;
  879. goto err_free_res;
  880. }
  881. mdev->pdev = pdev;
  882. mdev->mthca_flags = mthca_hca_table[id->driver_data].flags;
  883. if (ddr_hidden)
  884. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  885. /*
  886. * Now reset the HCA before we touch the PCI capabilities or
  887. * attempt a firmware command, since a boot ROM may have left
  888. * the HCA in an undefined state.
  889. */
  890. err = mthca_reset(mdev);
  891. if (err) {
  892. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  893. goto err_free_dev;
  894. }
  895. if (msi_x && !mthca_enable_msi_x(mdev))
  896. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  897. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  898. !pci_enable_msi(pdev))
  899. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  900. if (mthca_cmd_init(mdev)) {
  901. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  902. goto err_free_dev;
  903. }
  904. err = mthca_tune_pci(mdev);
  905. if (err)
  906. goto err_cmd;
  907. err = mthca_init_hca(mdev);
  908. if (err)
  909. goto err_cmd;
  910. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  911. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  912. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  913. (int) (mdev->fw_ver & 0xffff),
  914. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  915. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  916. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  917. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  918. }
  919. err = mthca_setup_hca(mdev);
  920. if (err)
  921. goto err_close;
  922. err = mthca_register_device(mdev);
  923. if (err)
  924. goto err_cleanup;
  925. err = mthca_create_agents(mdev);
  926. if (err)
  927. goto err_unregister;
  928. pci_set_drvdata(pdev, mdev);
  929. return 0;
  930. err_unregister:
  931. mthca_unregister_device(mdev);
  932. err_cleanup:
  933. mthca_cleanup_mcg_table(mdev);
  934. mthca_cleanup_av_table(mdev);
  935. mthca_cleanup_qp_table(mdev);
  936. mthca_cleanup_srq_table(mdev);
  937. mthca_cleanup_cq_table(mdev);
  938. mthca_cmd_use_polling(mdev);
  939. mthca_cleanup_eq_table(mdev);
  940. mthca_pd_free(mdev, &mdev->driver_pd);
  941. mthca_cleanup_mr_table(mdev);
  942. mthca_cleanup_pd_table(mdev);
  943. mthca_cleanup_uar_table(mdev);
  944. err_close:
  945. mthca_close_hca(mdev);
  946. err_cmd:
  947. mthca_cmd_cleanup(mdev);
  948. err_free_dev:
  949. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  950. pci_disable_msix(pdev);
  951. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  952. pci_disable_msi(pdev);
  953. ib_dealloc_device(&mdev->ib_dev);
  954. err_free_res:
  955. mthca_release_regions(pdev, ddr_hidden);
  956. err_disable_pdev:
  957. pci_disable_device(pdev);
  958. pci_set_drvdata(pdev, NULL);
  959. return err;
  960. }
  961. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  962. {
  963. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  964. u8 status;
  965. int p;
  966. if (mdev) {
  967. mthca_free_agents(mdev);
  968. mthca_unregister_device(mdev);
  969. for (p = 1; p <= mdev->limits.num_ports; ++p)
  970. mthca_CLOSE_IB(mdev, p, &status);
  971. mthca_cleanup_mcg_table(mdev);
  972. mthca_cleanup_av_table(mdev);
  973. mthca_cleanup_qp_table(mdev);
  974. mthca_cleanup_srq_table(mdev);
  975. mthca_cleanup_cq_table(mdev);
  976. mthca_cmd_use_polling(mdev);
  977. mthca_cleanup_eq_table(mdev);
  978. mthca_pd_free(mdev, &mdev->driver_pd);
  979. mthca_cleanup_mr_table(mdev);
  980. mthca_cleanup_pd_table(mdev);
  981. iounmap(mdev->kar);
  982. mthca_uar_free(mdev, &mdev->driver_uar);
  983. mthca_cleanup_uar_table(mdev);
  984. mthca_close_hca(mdev);
  985. mthca_cmd_cleanup(mdev);
  986. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  987. pci_disable_msix(pdev);
  988. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  989. pci_disable_msi(pdev);
  990. ib_dealloc_device(&mdev->ib_dev);
  991. mthca_release_regions(pdev, mdev->mthca_flags &
  992. MTHCA_FLAG_DDR_HIDDEN);
  993. pci_disable_device(pdev);
  994. pci_set_drvdata(pdev, NULL);
  995. }
  996. }
  997. static struct pci_device_id mthca_pci_table[] = {
  998. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  999. .driver_data = TAVOR },
  1000. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1001. .driver_data = TAVOR },
  1002. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1003. .driver_data = ARBEL_COMPAT },
  1004. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1005. .driver_data = ARBEL_COMPAT },
  1006. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1007. .driver_data = ARBEL_NATIVE },
  1008. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1009. .driver_data = ARBEL_NATIVE },
  1010. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1011. .driver_data = SINAI },
  1012. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1013. .driver_data = SINAI },
  1014. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1015. .driver_data = SINAI },
  1016. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1017. .driver_data = SINAI },
  1018. { 0, }
  1019. };
  1020. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1021. static struct pci_driver mthca_driver = {
  1022. .name = DRV_NAME,
  1023. .id_table = mthca_pci_table,
  1024. .probe = mthca_init_one,
  1025. .remove = __devexit_p(mthca_remove_one)
  1026. };
  1027. static int __init mthca_init(void)
  1028. {
  1029. int ret;
  1030. ret = pci_register_driver(&mthca_driver);
  1031. return ret < 0 ? ret : 0;
  1032. }
  1033. static void __exit mthca_cleanup(void)
  1034. {
  1035. pci_unregister_driver(&mthca_driver);
  1036. }
  1037. module_init(mthca_init);
  1038. module_exit(mthca_cleanup);