devices-da8xx.c 6.4 KB

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  1. /*
  2. * DA8XX/OMAP L1XX platform device data
  3. *
  4. * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
  5. * Derived from code that was:
  6. * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/serial_8250.h>
  19. #include <mach/cputype.h>
  20. #include <mach/common.h>
  21. #include <mach/time.h>
  22. #include <mach/da8xx.h>
  23. #include "clock.h"
  24. #define DA8XX_TPCC_BASE 0x01c00000
  25. #define DA8XX_TPTC0_BASE 0x01c08000
  26. #define DA8XX_TPTC1_BASE 0x01c08400
  27. #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  28. #define DA8XX_I2C0_BASE 0x01c22000
  29. #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
  30. #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
  31. #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
  32. #define DA8XX_EMAC_MDIO_BASE 0x01e24000
  33. #define DA8XX_GPIO_BASE 0x01e26000
  34. #define DA8XX_I2C1_BASE 0x01e28000
  35. #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
  36. #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
  37. #define DA8XX_EMAC_RAM_OFFSET 0x0000
  38. #define DA8XX_MDIO_REG_OFFSET 0x4000
  39. #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
  40. static struct plat_serial8250_port da8xx_serial_pdata[] = {
  41. {
  42. .mapbase = DA8XX_UART0_BASE,
  43. .irq = IRQ_DA8XX_UARTINT0,
  44. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  45. UPF_IOREMAP,
  46. .iotype = UPIO_MEM,
  47. .regshift = 2,
  48. },
  49. {
  50. .mapbase = DA8XX_UART1_BASE,
  51. .irq = IRQ_DA8XX_UARTINT1,
  52. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  53. UPF_IOREMAP,
  54. .iotype = UPIO_MEM,
  55. .regshift = 2,
  56. },
  57. {
  58. .mapbase = DA8XX_UART2_BASE,
  59. .irq = IRQ_DA8XX_UARTINT2,
  60. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  61. UPF_IOREMAP,
  62. .iotype = UPIO_MEM,
  63. .regshift = 2,
  64. },
  65. {
  66. .flags = 0,
  67. },
  68. };
  69. struct platform_device da8xx_serial_device = {
  70. .name = "serial8250",
  71. .id = PLAT8250_DEV_PLATFORM,
  72. .dev = {
  73. .platform_data = da8xx_serial_pdata,
  74. },
  75. };
  76. static const s8 da8xx_dma_chan_no_event[] = {
  77. 20, 21,
  78. -1
  79. };
  80. static const s8 da8xx_queue_tc_mapping[][2] = {
  81. /* {event queue no, TC no} */
  82. {0, 0},
  83. {1, 1},
  84. {-1, -1}
  85. };
  86. static const s8 da8xx_queue_priority_mapping[][2] = {
  87. /* {event queue no, Priority} */
  88. {0, 3},
  89. {1, 7},
  90. {-1, -1}
  91. };
  92. static struct edma_soc_info da8xx_edma_info[] = {
  93. {
  94. .n_channel = 32,
  95. .n_region = 4,
  96. .n_slot = 128,
  97. .n_tc = 2,
  98. .n_cc = 1,
  99. .noevent = da8xx_dma_chan_no_event,
  100. .queue_tc_mapping = da8xx_queue_tc_mapping,
  101. .queue_priority_mapping = da8xx_queue_priority_mapping,
  102. },
  103. };
  104. static struct resource da8xx_edma_resources[] = {
  105. {
  106. .name = "edma_cc0",
  107. .start = DA8XX_TPCC_BASE,
  108. .end = DA8XX_TPCC_BASE + SZ_32K - 1,
  109. .flags = IORESOURCE_MEM,
  110. },
  111. {
  112. .name = "edma_tc0",
  113. .start = DA8XX_TPTC0_BASE,
  114. .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
  115. .flags = IORESOURCE_MEM,
  116. },
  117. {
  118. .name = "edma_tc1",
  119. .start = DA8XX_TPTC1_BASE,
  120. .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
  121. .flags = IORESOURCE_MEM,
  122. },
  123. {
  124. .name = "edma0",
  125. .start = IRQ_DA8XX_CCINT0,
  126. .flags = IORESOURCE_IRQ,
  127. },
  128. {
  129. .name = "edma0_err",
  130. .start = IRQ_DA8XX_CCERRINT,
  131. .flags = IORESOURCE_IRQ,
  132. },
  133. };
  134. static struct platform_device da8xx_edma_device = {
  135. .name = "edma",
  136. .id = -1,
  137. .dev = {
  138. .platform_data = da8xx_edma_info,
  139. },
  140. .num_resources = ARRAY_SIZE(da8xx_edma_resources),
  141. .resource = da8xx_edma_resources,
  142. };
  143. int __init da8xx_register_edma(void)
  144. {
  145. return platform_device_register(&da8xx_edma_device);
  146. }
  147. static struct resource da8xx_i2c_resources0[] = {
  148. {
  149. .start = DA8XX_I2C0_BASE,
  150. .end = DA8XX_I2C0_BASE + SZ_4K - 1,
  151. .flags = IORESOURCE_MEM,
  152. },
  153. {
  154. .start = IRQ_DA8XX_I2CINT0,
  155. .end = IRQ_DA8XX_I2CINT0,
  156. .flags = IORESOURCE_IRQ,
  157. },
  158. };
  159. static struct platform_device da8xx_i2c_device0 = {
  160. .name = "i2c_davinci",
  161. .id = 1,
  162. .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
  163. .resource = da8xx_i2c_resources0,
  164. };
  165. static struct resource da8xx_i2c_resources1[] = {
  166. {
  167. .start = DA8XX_I2C1_BASE,
  168. .end = DA8XX_I2C1_BASE + SZ_4K - 1,
  169. .flags = IORESOURCE_MEM,
  170. },
  171. {
  172. .start = IRQ_DA8XX_I2CINT1,
  173. .end = IRQ_DA8XX_I2CINT1,
  174. .flags = IORESOURCE_IRQ,
  175. },
  176. };
  177. static struct platform_device da8xx_i2c_device1 = {
  178. .name = "i2c_davinci",
  179. .id = 2,
  180. .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
  181. .resource = da8xx_i2c_resources1,
  182. };
  183. int __init da8xx_register_i2c(int instance,
  184. struct davinci_i2c_platform_data *pdata)
  185. {
  186. struct platform_device *pdev;
  187. if (instance == 0)
  188. pdev = &da8xx_i2c_device0;
  189. else if (instance == 1)
  190. pdev = &da8xx_i2c_device1;
  191. else
  192. return -EINVAL;
  193. pdev->dev.platform_data = pdata;
  194. return platform_device_register(pdev);
  195. }
  196. static struct resource da8xx_watchdog_resources[] = {
  197. {
  198. .start = DA8XX_WDOG_BASE,
  199. .end = DA8XX_WDOG_BASE + SZ_4K - 1,
  200. .flags = IORESOURCE_MEM,
  201. },
  202. };
  203. struct platform_device davinci_wdt_device = {
  204. .name = "watchdog",
  205. .id = -1,
  206. .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
  207. .resource = da8xx_watchdog_resources,
  208. };
  209. int __init da8xx_register_watchdog(void)
  210. {
  211. return platform_device_register(&davinci_wdt_device);
  212. }
  213. static struct resource da8xx_emac_resources[] = {
  214. {
  215. .start = DA8XX_EMAC_CPPI_PORT_BASE,
  216. .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
  217. .flags = IORESOURCE_MEM,
  218. },
  219. {
  220. .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
  221. .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
  222. .flags = IORESOURCE_IRQ,
  223. },
  224. {
  225. .start = IRQ_DA8XX_C0_RX_PULSE,
  226. .end = IRQ_DA8XX_C0_RX_PULSE,
  227. .flags = IORESOURCE_IRQ,
  228. },
  229. {
  230. .start = IRQ_DA8XX_C0_TX_PULSE,
  231. .end = IRQ_DA8XX_C0_TX_PULSE,
  232. .flags = IORESOURCE_IRQ,
  233. },
  234. {
  235. .start = IRQ_DA8XX_C0_MISC_PULSE,
  236. .end = IRQ_DA8XX_C0_MISC_PULSE,
  237. .flags = IORESOURCE_IRQ,
  238. },
  239. };
  240. struct emac_platform_data da8xx_emac_pdata = {
  241. .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
  242. .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
  243. .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
  244. .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET,
  245. .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
  246. .version = EMAC_VERSION_2,
  247. };
  248. static struct platform_device da8xx_emac_device = {
  249. .name = "davinci_emac",
  250. .id = 1,
  251. .dev = {
  252. .platform_data = &da8xx_emac_pdata,
  253. },
  254. .num_resources = ARRAY_SIZE(da8xx_emac_resources),
  255. .resource = da8xx_emac_resources,
  256. };
  257. int __init da8xx_register_emac(void)
  258. {
  259. return platform_device_register(&da8xx_emac_device);
  260. }