recv.c 51 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "ath9k.h"
  17. #include "ar9003_mac.h"
  18. #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
  19. static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
  20. int mindelta, int main_rssi_avg,
  21. int alt_rssi_avg, int pkt_count)
  22. {
  23. return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  24. (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
  25. (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
  26. }
  27. static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
  28. int curr_main_set, int curr_alt_set,
  29. int alt_rssi_avg, int main_rssi_avg)
  30. {
  31. bool result = false;
  32. switch (div_group) {
  33. case 0:
  34. if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
  35. result = true;
  36. break;
  37. case 1:
  38. case 2:
  39. if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
  40. (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
  41. (alt_rssi_avg >= (main_rssi_avg - 5))) ||
  42. ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
  43. (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
  44. (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
  45. (alt_rssi_avg >= 4))
  46. result = true;
  47. else
  48. result = false;
  49. break;
  50. }
  51. return result;
  52. }
  53. static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
  54. {
  55. return sc->ps_enabled &&
  56. (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
  57. }
  58. /*
  59. * Setup and link descriptors.
  60. *
  61. * 11N: we can no longer afford to self link the last descriptor.
  62. * MAC acknowledges BA status as long as it copies frames to host
  63. * buffer (or rx fifo). This can incorrectly acknowledge packets
  64. * to a sender if last desc is self-linked.
  65. */
  66. static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  67. {
  68. struct ath_hw *ah = sc->sc_ah;
  69. struct ath_common *common = ath9k_hw_common(ah);
  70. struct ath_desc *ds;
  71. struct sk_buff *skb;
  72. ATH_RXBUF_RESET(bf);
  73. ds = bf->bf_desc;
  74. ds->ds_link = 0; /* link to null */
  75. ds->ds_data = bf->bf_buf_addr;
  76. /* virtual addr of the beginning of the buffer. */
  77. skb = bf->bf_mpdu;
  78. BUG_ON(skb == NULL);
  79. ds->ds_vdata = skb->data;
  80. /*
  81. * setup rx descriptors. The rx_bufsize here tells the hardware
  82. * how much data it can DMA to us and that we are prepared
  83. * to process
  84. */
  85. ath9k_hw_setuprxdesc(ah, ds,
  86. common->rx_bufsize,
  87. 0);
  88. if (sc->rx.rxlink == NULL)
  89. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  90. else
  91. *sc->rx.rxlink = bf->bf_daddr;
  92. sc->rx.rxlink = &ds->ds_link;
  93. }
  94. static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  95. {
  96. /* XXX block beacon interrupts */
  97. ath9k_hw_setantenna(sc->sc_ah, antenna);
  98. sc->rx.defant = antenna;
  99. sc->rx.rxotherant = 0;
  100. }
  101. static void ath_opmode_init(struct ath_softc *sc)
  102. {
  103. struct ath_hw *ah = sc->sc_ah;
  104. struct ath_common *common = ath9k_hw_common(ah);
  105. u32 rfilt, mfilt[2];
  106. /* configure rx filter */
  107. rfilt = ath_calcrxfilter(sc);
  108. ath9k_hw_setrxfilter(ah, rfilt);
  109. /* configure bssid mask */
  110. ath_hw_setbssidmask(common);
  111. /* configure operational mode */
  112. ath9k_hw_setopmode(ah);
  113. /* calculate and install multicast filter */
  114. mfilt[0] = mfilt[1] = ~0;
  115. ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
  116. }
  117. static bool ath_rx_edma_buf_link(struct ath_softc *sc,
  118. enum ath9k_rx_qtype qtype)
  119. {
  120. struct ath_hw *ah = sc->sc_ah;
  121. struct ath_rx_edma *rx_edma;
  122. struct sk_buff *skb;
  123. struct ath_buf *bf;
  124. rx_edma = &sc->rx.rx_edma[qtype];
  125. if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
  126. return false;
  127. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  128. list_del_init(&bf->list);
  129. skb = bf->bf_mpdu;
  130. ATH_RXBUF_RESET(bf);
  131. memset(skb->data, 0, ah->caps.rx_status_len);
  132. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  133. ah->caps.rx_status_len, DMA_TO_DEVICE);
  134. SKB_CB_ATHBUF(skb) = bf;
  135. ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
  136. skb_queue_tail(&rx_edma->rx_fifo, skb);
  137. return true;
  138. }
  139. static void ath_rx_addbuffer_edma(struct ath_softc *sc,
  140. enum ath9k_rx_qtype qtype, int size)
  141. {
  142. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  143. u32 nbuf = 0;
  144. if (list_empty(&sc->rx.rxbuf)) {
  145. ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
  146. return;
  147. }
  148. while (!list_empty(&sc->rx.rxbuf)) {
  149. nbuf++;
  150. if (!ath_rx_edma_buf_link(sc, qtype))
  151. break;
  152. if (nbuf >= size)
  153. break;
  154. }
  155. }
  156. static void ath_rx_remove_buffer(struct ath_softc *sc,
  157. enum ath9k_rx_qtype qtype)
  158. {
  159. struct ath_buf *bf;
  160. struct ath_rx_edma *rx_edma;
  161. struct sk_buff *skb;
  162. rx_edma = &sc->rx.rx_edma[qtype];
  163. while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
  164. bf = SKB_CB_ATHBUF(skb);
  165. BUG_ON(!bf);
  166. list_add_tail(&bf->list, &sc->rx.rxbuf);
  167. }
  168. }
  169. static void ath_rx_edma_cleanup(struct ath_softc *sc)
  170. {
  171. struct ath_buf *bf;
  172. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
  173. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
  174. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  175. if (bf->bf_mpdu)
  176. dev_kfree_skb_any(bf->bf_mpdu);
  177. }
  178. INIT_LIST_HEAD(&sc->rx.rxbuf);
  179. kfree(sc->rx.rx_bufptr);
  180. sc->rx.rx_bufptr = NULL;
  181. }
  182. static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
  183. {
  184. skb_queue_head_init(&rx_edma->rx_fifo);
  185. skb_queue_head_init(&rx_edma->rx_buffers);
  186. rx_edma->rx_fifo_hwsize = size;
  187. }
  188. static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
  189. {
  190. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  191. struct ath_hw *ah = sc->sc_ah;
  192. struct sk_buff *skb;
  193. struct ath_buf *bf;
  194. int error = 0, i;
  195. u32 size;
  196. ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
  197. ah->caps.rx_status_len);
  198. ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
  199. ah->caps.rx_lp_qdepth);
  200. ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
  201. ah->caps.rx_hp_qdepth);
  202. size = sizeof(struct ath_buf) * nbufs;
  203. bf = kzalloc(size, GFP_KERNEL);
  204. if (!bf)
  205. return -ENOMEM;
  206. INIT_LIST_HEAD(&sc->rx.rxbuf);
  207. sc->rx.rx_bufptr = bf;
  208. for (i = 0; i < nbufs; i++, bf++) {
  209. skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
  210. if (!skb) {
  211. error = -ENOMEM;
  212. goto rx_init_fail;
  213. }
  214. memset(skb->data, 0, common->rx_bufsize);
  215. bf->bf_mpdu = skb;
  216. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  217. common->rx_bufsize,
  218. DMA_BIDIRECTIONAL);
  219. if (unlikely(dma_mapping_error(sc->dev,
  220. bf->bf_buf_addr))) {
  221. dev_kfree_skb_any(skb);
  222. bf->bf_mpdu = NULL;
  223. bf->bf_buf_addr = 0;
  224. ath_err(common,
  225. "dma_mapping_error() on RX init\n");
  226. error = -ENOMEM;
  227. goto rx_init_fail;
  228. }
  229. list_add_tail(&bf->list, &sc->rx.rxbuf);
  230. }
  231. return 0;
  232. rx_init_fail:
  233. ath_rx_edma_cleanup(sc);
  234. return error;
  235. }
  236. static void ath_edma_start_recv(struct ath_softc *sc)
  237. {
  238. spin_lock_bh(&sc->rx.rxbuflock);
  239. ath9k_hw_rxena(sc->sc_ah);
  240. ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
  241. sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
  242. ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
  243. sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
  244. ath_opmode_init(sc);
  245. ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
  246. spin_unlock_bh(&sc->rx.rxbuflock);
  247. }
  248. static void ath_edma_stop_recv(struct ath_softc *sc)
  249. {
  250. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
  251. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
  252. }
  253. int ath_rx_init(struct ath_softc *sc, int nbufs)
  254. {
  255. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  256. struct sk_buff *skb;
  257. struct ath_buf *bf;
  258. int error = 0;
  259. spin_lock_init(&sc->sc_pcu_lock);
  260. sc->sc_flags &= ~SC_OP_RXFLUSH;
  261. spin_lock_init(&sc->rx.rxbuflock);
  262. common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
  263. sc->sc_ah->caps.rx_status_len;
  264. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  265. return ath_rx_edma_init(sc, nbufs);
  266. } else {
  267. ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
  268. common->cachelsz, common->rx_bufsize);
  269. /* Initialize rx descriptors */
  270. error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
  271. "rx", nbufs, 1, 0);
  272. if (error != 0) {
  273. ath_err(common,
  274. "failed to allocate rx descriptors: %d\n",
  275. error);
  276. goto err;
  277. }
  278. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  279. skb = ath_rxbuf_alloc(common, common->rx_bufsize,
  280. GFP_KERNEL);
  281. if (skb == NULL) {
  282. error = -ENOMEM;
  283. goto err;
  284. }
  285. bf->bf_mpdu = skb;
  286. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  287. common->rx_bufsize,
  288. DMA_FROM_DEVICE);
  289. if (unlikely(dma_mapping_error(sc->dev,
  290. bf->bf_buf_addr))) {
  291. dev_kfree_skb_any(skb);
  292. bf->bf_mpdu = NULL;
  293. bf->bf_buf_addr = 0;
  294. ath_err(common,
  295. "dma_mapping_error() on RX init\n");
  296. error = -ENOMEM;
  297. goto err;
  298. }
  299. }
  300. sc->rx.rxlink = NULL;
  301. }
  302. err:
  303. if (error)
  304. ath_rx_cleanup(sc);
  305. return error;
  306. }
  307. void ath_rx_cleanup(struct ath_softc *sc)
  308. {
  309. struct ath_hw *ah = sc->sc_ah;
  310. struct ath_common *common = ath9k_hw_common(ah);
  311. struct sk_buff *skb;
  312. struct ath_buf *bf;
  313. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  314. ath_rx_edma_cleanup(sc);
  315. return;
  316. } else {
  317. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  318. skb = bf->bf_mpdu;
  319. if (skb) {
  320. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  321. common->rx_bufsize,
  322. DMA_FROM_DEVICE);
  323. dev_kfree_skb(skb);
  324. bf->bf_buf_addr = 0;
  325. bf->bf_mpdu = NULL;
  326. }
  327. }
  328. if (sc->rx.rxdma.dd_desc_len != 0)
  329. ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
  330. }
  331. }
  332. /*
  333. * Calculate the receive filter according to the
  334. * operating mode and state:
  335. *
  336. * o always accept unicast, broadcast, and multicast traffic
  337. * o maintain current state of phy error reception (the hal
  338. * may enable phy error frames for noise immunity work)
  339. * o probe request frames are accepted only when operating in
  340. * hostap, adhoc, or monitor modes
  341. * o enable promiscuous mode according to the interface state
  342. * o accept beacons:
  343. * - when operating in adhoc mode so the 802.11 layer creates
  344. * node table entries for peers,
  345. * - when operating in station mode for collecting rssi data when
  346. * the station is otherwise quiet, or
  347. * - when operating as a repeater so we see repeater-sta beacons
  348. * - when scanning
  349. */
  350. u32 ath_calcrxfilter(struct ath_softc *sc)
  351. {
  352. #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
  353. u32 rfilt;
  354. rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
  355. | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
  356. | ATH9K_RX_FILTER_MCAST;
  357. if (sc->rx.rxfilter & FIF_PROBE_REQ)
  358. rfilt |= ATH9K_RX_FILTER_PROBEREQ;
  359. /*
  360. * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
  361. * mode interface or when in monitor mode. AP mode does not need this
  362. * since it receives all in-BSS frames anyway.
  363. */
  364. if (sc->sc_ah->is_monitoring)
  365. rfilt |= ATH9K_RX_FILTER_PROM;
  366. if (sc->rx.rxfilter & FIF_CONTROL)
  367. rfilt |= ATH9K_RX_FILTER_CONTROL;
  368. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  369. (sc->nvifs <= 1) &&
  370. !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
  371. rfilt |= ATH9K_RX_FILTER_MYBEACON;
  372. else
  373. rfilt |= ATH9K_RX_FILTER_BEACON;
  374. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  375. (sc->rx.rxfilter & FIF_PSPOLL))
  376. rfilt |= ATH9K_RX_FILTER_PSPOLL;
  377. if (conf_is_ht(&sc->hw->conf))
  378. rfilt |= ATH9K_RX_FILTER_COMP_BAR;
  379. if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
  380. /* The following may also be needed for other older chips */
  381. if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
  382. rfilt |= ATH9K_RX_FILTER_PROM;
  383. rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
  384. }
  385. return rfilt;
  386. #undef RX_FILTER_PRESERVE
  387. }
  388. int ath_startrecv(struct ath_softc *sc)
  389. {
  390. struct ath_hw *ah = sc->sc_ah;
  391. struct ath_buf *bf, *tbf;
  392. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  393. ath_edma_start_recv(sc);
  394. return 0;
  395. }
  396. spin_lock_bh(&sc->rx.rxbuflock);
  397. if (list_empty(&sc->rx.rxbuf))
  398. goto start_recv;
  399. sc->rx.rxlink = NULL;
  400. list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
  401. ath_rx_buf_link(sc, bf);
  402. }
  403. /* We could have deleted elements so the list may be empty now */
  404. if (list_empty(&sc->rx.rxbuf))
  405. goto start_recv;
  406. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  407. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  408. ath9k_hw_rxena(ah);
  409. start_recv:
  410. ath_opmode_init(sc);
  411. ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
  412. spin_unlock_bh(&sc->rx.rxbuflock);
  413. return 0;
  414. }
  415. bool ath_stoprecv(struct ath_softc *sc)
  416. {
  417. struct ath_hw *ah = sc->sc_ah;
  418. bool stopped, reset = false;
  419. spin_lock_bh(&sc->rx.rxbuflock);
  420. ath9k_hw_abortpcurecv(ah);
  421. ath9k_hw_setrxfilter(ah, 0);
  422. stopped = ath9k_hw_stopdmarecv(ah, &reset);
  423. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  424. ath_edma_stop_recv(sc);
  425. else
  426. sc->rx.rxlink = NULL;
  427. spin_unlock_bh(&sc->rx.rxbuflock);
  428. if (!(ah->ah_flags & AH_UNPLUGGED) &&
  429. unlikely(!stopped)) {
  430. ath_err(ath9k_hw_common(sc->sc_ah),
  431. "Could not stop RX, we could be "
  432. "confusing the DMA engine when we start RX up\n");
  433. ATH_DBG_WARN_ON_ONCE(!stopped);
  434. }
  435. return stopped && !reset;
  436. }
  437. void ath_flushrecv(struct ath_softc *sc)
  438. {
  439. sc->sc_flags |= SC_OP_RXFLUSH;
  440. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  441. ath_rx_tasklet(sc, 1, true);
  442. ath_rx_tasklet(sc, 1, false);
  443. sc->sc_flags &= ~SC_OP_RXFLUSH;
  444. }
  445. static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
  446. {
  447. /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
  448. struct ieee80211_mgmt *mgmt;
  449. u8 *pos, *end, id, elen;
  450. struct ieee80211_tim_ie *tim;
  451. mgmt = (struct ieee80211_mgmt *)skb->data;
  452. pos = mgmt->u.beacon.variable;
  453. end = skb->data + skb->len;
  454. while (pos + 2 < end) {
  455. id = *pos++;
  456. elen = *pos++;
  457. if (pos + elen > end)
  458. break;
  459. if (id == WLAN_EID_TIM) {
  460. if (elen < sizeof(*tim))
  461. break;
  462. tim = (struct ieee80211_tim_ie *) pos;
  463. if (tim->dtim_count != 0)
  464. break;
  465. return tim->bitmap_ctrl & 0x01;
  466. }
  467. pos += elen;
  468. }
  469. return false;
  470. }
  471. static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
  472. {
  473. struct ieee80211_mgmt *mgmt;
  474. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  475. if (skb->len < 24 + 8 + 2 + 2)
  476. return;
  477. mgmt = (struct ieee80211_mgmt *)skb->data;
  478. if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
  479. /* TODO: This doesn't work well if you have stations
  480. * associated to two different APs because curbssid
  481. * is just the last AP that any of the stations associated
  482. * with.
  483. */
  484. return; /* not from our current AP */
  485. }
  486. sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
  487. if (sc->ps_flags & PS_BEACON_SYNC) {
  488. sc->ps_flags &= ~PS_BEACON_SYNC;
  489. ath_dbg(common, ATH_DBG_PS,
  490. "Reconfigure Beacon timers based on timestamp from the AP\n");
  491. ath_set_beacon(sc);
  492. sc->ps_flags &= ~PS_TSFOOR_SYNC;
  493. }
  494. if (ath_beacon_dtim_pending_cab(skb)) {
  495. /*
  496. * Remain awake waiting for buffered broadcast/multicast
  497. * frames. If the last broadcast/multicast frame is not
  498. * received properly, the next beacon frame will work as
  499. * a backup trigger for returning into NETWORK SLEEP state,
  500. * so we are waiting for it as well.
  501. */
  502. ath_dbg(common, ATH_DBG_PS,
  503. "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
  504. sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
  505. return;
  506. }
  507. if (sc->ps_flags & PS_WAIT_FOR_CAB) {
  508. /*
  509. * This can happen if a broadcast frame is dropped or the AP
  510. * fails to send a frame indicating that all CAB frames have
  511. * been delivered.
  512. */
  513. sc->ps_flags &= ~PS_WAIT_FOR_CAB;
  514. ath_dbg(common, ATH_DBG_PS,
  515. "PS wait for CAB frames timed out\n");
  516. }
  517. }
  518. static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
  519. {
  520. struct ieee80211_hdr *hdr;
  521. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  522. hdr = (struct ieee80211_hdr *)skb->data;
  523. /* Process Beacon and CAB receive in PS state */
  524. if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
  525. && ieee80211_is_beacon(hdr->frame_control))
  526. ath_rx_ps_beacon(sc, skb);
  527. else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
  528. (ieee80211_is_data(hdr->frame_control) ||
  529. ieee80211_is_action(hdr->frame_control)) &&
  530. is_multicast_ether_addr(hdr->addr1) &&
  531. !ieee80211_has_moredata(hdr->frame_control)) {
  532. /*
  533. * No more broadcast/multicast frames to be received at this
  534. * point.
  535. */
  536. sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
  537. ath_dbg(common, ATH_DBG_PS,
  538. "All PS CAB frames received, back to sleep\n");
  539. } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
  540. !is_multicast_ether_addr(hdr->addr1) &&
  541. !ieee80211_has_morefrags(hdr->frame_control)) {
  542. sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
  543. ath_dbg(common, ATH_DBG_PS,
  544. "Going back to sleep after having received PS-Poll data (0x%lx)\n",
  545. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  546. PS_WAIT_FOR_CAB |
  547. PS_WAIT_FOR_PSPOLL_DATA |
  548. PS_WAIT_FOR_TX_ACK));
  549. }
  550. }
  551. static bool ath_edma_get_buffers(struct ath_softc *sc,
  552. enum ath9k_rx_qtype qtype)
  553. {
  554. struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
  555. struct ath_hw *ah = sc->sc_ah;
  556. struct ath_common *common = ath9k_hw_common(ah);
  557. struct sk_buff *skb;
  558. struct ath_buf *bf;
  559. int ret;
  560. skb = skb_peek(&rx_edma->rx_fifo);
  561. if (!skb)
  562. return false;
  563. bf = SKB_CB_ATHBUF(skb);
  564. BUG_ON(!bf);
  565. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  566. common->rx_bufsize, DMA_FROM_DEVICE);
  567. ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
  568. if (ret == -EINPROGRESS) {
  569. /*let device gain the buffer again*/
  570. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  571. common->rx_bufsize, DMA_FROM_DEVICE);
  572. return false;
  573. }
  574. __skb_unlink(skb, &rx_edma->rx_fifo);
  575. if (ret == -EINVAL) {
  576. /* corrupt descriptor, skip this one and the following one */
  577. list_add_tail(&bf->list, &sc->rx.rxbuf);
  578. ath_rx_edma_buf_link(sc, qtype);
  579. skb = skb_peek(&rx_edma->rx_fifo);
  580. if (!skb)
  581. return true;
  582. bf = SKB_CB_ATHBUF(skb);
  583. BUG_ON(!bf);
  584. __skb_unlink(skb, &rx_edma->rx_fifo);
  585. list_add_tail(&bf->list, &sc->rx.rxbuf);
  586. ath_rx_edma_buf_link(sc, qtype);
  587. return true;
  588. }
  589. skb_queue_tail(&rx_edma->rx_buffers, skb);
  590. return true;
  591. }
  592. static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
  593. struct ath_rx_status *rs,
  594. enum ath9k_rx_qtype qtype)
  595. {
  596. struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
  597. struct sk_buff *skb;
  598. struct ath_buf *bf;
  599. while (ath_edma_get_buffers(sc, qtype));
  600. skb = __skb_dequeue(&rx_edma->rx_buffers);
  601. if (!skb)
  602. return NULL;
  603. bf = SKB_CB_ATHBUF(skb);
  604. ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
  605. return bf;
  606. }
  607. static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
  608. struct ath_rx_status *rs)
  609. {
  610. struct ath_hw *ah = sc->sc_ah;
  611. struct ath_common *common = ath9k_hw_common(ah);
  612. struct ath_desc *ds;
  613. struct ath_buf *bf;
  614. int ret;
  615. if (list_empty(&sc->rx.rxbuf)) {
  616. sc->rx.rxlink = NULL;
  617. return NULL;
  618. }
  619. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  620. ds = bf->bf_desc;
  621. /*
  622. * Must provide the virtual address of the current
  623. * descriptor, the physical address, and the virtual
  624. * address of the next descriptor in the h/w chain.
  625. * This allows the HAL to look ahead to see if the
  626. * hardware is done with a descriptor by checking the
  627. * done bit in the following descriptor and the address
  628. * of the current descriptor the DMA engine is working
  629. * on. All this is necessary because of our use of
  630. * a self-linked list to avoid rx overruns.
  631. */
  632. ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
  633. if (ret == -EINPROGRESS) {
  634. struct ath_rx_status trs;
  635. struct ath_buf *tbf;
  636. struct ath_desc *tds;
  637. memset(&trs, 0, sizeof(trs));
  638. if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
  639. sc->rx.rxlink = NULL;
  640. return NULL;
  641. }
  642. tbf = list_entry(bf->list.next, struct ath_buf, list);
  643. /*
  644. * On some hardware the descriptor status words could
  645. * get corrupted, including the done bit. Because of
  646. * this, check if the next descriptor's done bit is
  647. * set or not.
  648. *
  649. * If the next descriptor's done bit is set, the current
  650. * descriptor has been corrupted. Force s/w to discard
  651. * this descriptor and continue...
  652. */
  653. tds = tbf->bf_desc;
  654. ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
  655. if (ret == -EINPROGRESS)
  656. return NULL;
  657. }
  658. if (!bf->bf_mpdu)
  659. return bf;
  660. /*
  661. * Synchronize the DMA transfer with CPU before
  662. * 1. accessing the frame
  663. * 2. requeueing the same buffer to h/w
  664. */
  665. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  666. common->rx_bufsize,
  667. DMA_FROM_DEVICE);
  668. return bf;
  669. }
  670. /* Assumes you've already done the endian to CPU conversion */
  671. static bool ath9k_rx_accept(struct ath_common *common,
  672. struct ieee80211_hdr *hdr,
  673. struct ieee80211_rx_status *rxs,
  674. struct ath_rx_status *rx_stats,
  675. bool *decrypt_error)
  676. {
  677. #define is_mc_or_valid_tkip_keyix ((is_mc || \
  678. (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
  679. test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
  680. struct ath_hw *ah = common->ah;
  681. __le16 fc;
  682. u8 rx_status_len = ah->caps.rx_status_len;
  683. fc = hdr->frame_control;
  684. if (!rx_stats->rs_datalen)
  685. return false;
  686. /*
  687. * rs_status follows rs_datalen so if rs_datalen is too large
  688. * we can take a hint that hardware corrupted it, so ignore
  689. * those frames.
  690. */
  691. if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
  692. return false;
  693. /* Only use error bits from the last fragment */
  694. if (rx_stats->rs_more)
  695. return true;
  696. /*
  697. * The rx_stats->rs_status will not be set until the end of the
  698. * chained descriptors so it can be ignored if rs_more is set. The
  699. * rs_more will be false at the last element of the chained
  700. * descriptors.
  701. */
  702. if (rx_stats->rs_status != 0) {
  703. if (rx_stats->rs_status & ATH9K_RXERR_CRC)
  704. rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
  705. if (rx_stats->rs_status & ATH9K_RXERR_PHY)
  706. return false;
  707. if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
  708. *decrypt_error = true;
  709. } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
  710. bool is_mc;
  711. /*
  712. * The MIC error bit is only valid if the frame
  713. * is not a control frame or fragment, and it was
  714. * decrypted using a valid TKIP key.
  715. */
  716. is_mc = !!is_multicast_ether_addr(hdr->addr1);
  717. if (!ieee80211_is_ctl(fc) &&
  718. !ieee80211_has_morefrags(fc) &&
  719. !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
  720. is_mc_or_valid_tkip_keyix)
  721. rxs->flag |= RX_FLAG_MMIC_ERROR;
  722. else
  723. rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
  724. }
  725. /*
  726. * Reject error frames with the exception of
  727. * decryption and MIC failures. For monitor mode,
  728. * we also ignore the CRC error.
  729. */
  730. if (ah->is_monitoring) {
  731. if (rx_stats->rs_status &
  732. ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
  733. ATH9K_RXERR_CRC))
  734. return false;
  735. } else {
  736. if (rx_stats->rs_status &
  737. ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
  738. return false;
  739. }
  740. }
  741. }
  742. return true;
  743. }
  744. static int ath9k_process_rate(struct ath_common *common,
  745. struct ieee80211_hw *hw,
  746. struct ath_rx_status *rx_stats,
  747. struct ieee80211_rx_status *rxs)
  748. {
  749. struct ieee80211_supported_band *sband;
  750. enum ieee80211_band band;
  751. unsigned int i = 0;
  752. band = hw->conf.channel->band;
  753. sband = hw->wiphy->bands[band];
  754. if (rx_stats->rs_rate & 0x80) {
  755. /* HT rate */
  756. rxs->flag |= RX_FLAG_HT;
  757. if (rx_stats->rs_flags & ATH9K_RX_2040)
  758. rxs->flag |= RX_FLAG_40MHZ;
  759. if (rx_stats->rs_flags & ATH9K_RX_GI)
  760. rxs->flag |= RX_FLAG_SHORT_GI;
  761. rxs->rate_idx = rx_stats->rs_rate & 0x7f;
  762. return 0;
  763. }
  764. for (i = 0; i < sband->n_bitrates; i++) {
  765. if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
  766. rxs->rate_idx = i;
  767. return 0;
  768. }
  769. if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
  770. rxs->flag |= RX_FLAG_SHORTPRE;
  771. rxs->rate_idx = i;
  772. return 0;
  773. }
  774. }
  775. /*
  776. * No valid hardware bitrate found -- we should not get here
  777. * because hardware has already validated this frame as OK.
  778. */
  779. ath_dbg(common, ATH_DBG_XMIT,
  780. "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
  781. rx_stats->rs_rate);
  782. return -EINVAL;
  783. }
  784. static void ath9k_process_rssi(struct ath_common *common,
  785. struct ieee80211_hw *hw,
  786. struct ieee80211_hdr *hdr,
  787. struct ath_rx_status *rx_stats)
  788. {
  789. struct ath_softc *sc = hw->priv;
  790. struct ath_hw *ah = common->ah;
  791. int last_rssi;
  792. __le16 fc;
  793. if ((ah->opmode != NL80211_IFTYPE_STATION) &&
  794. (ah->opmode != NL80211_IFTYPE_ADHOC))
  795. return;
  796. fc = hdr->frame_control;
  797. if (!ieee80211_is_beacon(fc) ||
  798. compare_ether_addr(hdr->addr3, common->curbssid)) {
  799. /* TODO: This doesn't work well if you have stations
  800. * associated to two different APs because curbssid
  801. * is just the last AP that any of the stations associated
  802. * with.
  803. */
  804. return;
  805. }
  806. if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
  807. ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
  808. last_rssi = sc->last_rssi;
  809. if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
  810. rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
  811. ATH_RSSI_EP_MULTIPLIER);
  812. if (rx_stats->rs_rssi < 0)
  813. rx_stats->rs_rssi = 0;
  814. /* Update Beacon RSSI, this is used by ANI. */
  815. ah->stats.avgbrssi = rx_stats->rs_rssi;
  816. }
  817. /*
  818. * For Decrypt or Demic errors, we only mark packet status here and always push
  819. * up the frame up to let mac80211 handle the actual error case, be it no
  820. * decryption key or real decryption error. This let us keep statistics there.
  821. */
  822. static int ath9k_rx_skb_preprocess(struct ath_common *common,
  823. struct ieee80211_hw *hw,
  824. struct ieee80211_hdr *hdr,
  825. struct ath_rx_status *rx_stats,
  826. struct ieee80211_rx_status *rx_status,
  827. bool *decrypt_error)
  828. {
  829. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  830. /*
  831. * everything but the rate is checked here, the rate check is done
  832. * separately to avoid doing two lookups for a rate for each frame.
  833. */
  834. if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
  835. return -EINVAL;
  836. /* Only use status info from the last fragment */
  837. if (rx_stats->rs_more)
  838. return 0;
  839. ath9k_process_rssi(common, hw, hdr, rx_stats);
  840. if (ath9k_process_rate(common, hw, rx_stats, rx_status))
  841. return -EINVAL;
  842. rx_status->band = hw->conf.channel->band;
  843. rx_status->freq = hw->conf.channel->center_freq;
  844. rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
  845. rx_status->antenna = rx_stats->rs_antenna;
  846. rx_status->flag |= RX_FLAG_MACTIME_MPDU;
  847. return 0;
  848. }
  849. static void ath9k_rx_skb_postprocess(struct ath_common *common,
  850. struct sk_buff *skb,
  851. struct ath_rx_status *rx_stats,
  852. struct ieee80211_rx_status *rxs,
  853. bool decrypt_error)
  854. {
  855. struct ath_hw *ah = common->ah;
  856. struct ieee80211_hdr *hdr;
  857. int hdrlen, padpos, padsize;
  858. u8 keyix;
  859. __le16 fc;
  860. /* see if any padding is done by the hw and remove it */
  861. hdr = (struct ieee80211_hdr *) skb->data;
  862. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  863. fc = hdr->frame_control;
  864. padpos = ath9k_cmn_padpos(hdr->frame_control);
  865. /* The MAC header is padded to have 32-bit boundary if the
  866. * packet payload is non-zero. The general calculation for
  867. * padsize would take into account odd header lengths:
  868. * padsize = (4 - padpos % 4) % 4; However, since only
  869. * even-length headers are used, padding can only be 0 or 2
  870. * bytes and we can optimize this a bit. In addition, we must
  871. * not try to remove padding from short control frames that do
  872. * not have payload. */
  873. padsize = padpos & 3;
  874. if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
  875. memmove(skb->data + padsize, skb->data, padpos);
  876. skb_pull(skb, padsize);
  877. }
  878. keyix = rx_stats->rs_keyix;
  879. if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
  880. ieee80211_has_protected(fc)) {
  881. rxs->flag |= RX_FLAG_DECRYPTED;
  882. } else if (ieee80211_has_protected(fc)
  883. && !decrypt_error && skb->len >= hdrlen + 4) {
  884. keyix = skb->data[hdrlen + 3] >> 6;
  885. if (test_bit(keyix, common->keymap))
  886. rxs->flag |= RX_FLAG_DECRYPTED;
  887. }
  888. if (ah->sw_mgmt_crypto &&
  889. (rxs->flag & RX_FLAG_DECRYPTED) &&
  890. ieee80211_is_mgmt(fc))
  891. /* Use software decrypt for management frames. */
  892. rxs->flag &= ~RX_FLAG_DECRYPTED;
  893. }
  894. static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
  895. struct ath_hw_antcomb_conf ant_conf,
  896. int main_rssi_avg)
  897. {
  898. antcomb->quick_scan_cnt = 0;
  899. if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
  900. antcomb->rssi_lna2 = main_rssi_avg;
  901. else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
  902. antcomb->rssi_lna1 = main_rssi_avg;
  903. switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
  904. case 0x10: /* LNA2 A-B */
  905. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  906. antcomb->first_quick_scan_conf =
  907. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  908. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
  909. break;
  910. case 0x20: /* LNA1 A-B */
  911. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  912. antcomb->first_quick_scan_conf =
  913. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  914. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
  915. break;
  916. case 0x21: /* LNA1 LNA2 */
  917. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
  918. antcomb->first_quick_scan_conf =
  919. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  920. antcomb->second_quick_scan_conf =
  921. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  922. break;
  923. case 0x12: /* LNA2 LNA1 */
  924. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
  925. antcomb->first_quick_scan_conf =
  926. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  927. antcomb->second_quick_scan_conf =
  928. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  929. break;
  930. case 0x13: /* LNA2 A+B */
  931. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  932. antcomb->first_quick_scan_conf =
  933. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  934. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
  935. break;
  936. case 0x23: /* LNA1 A+B */
  937. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  938. antcomb->first_quick_scan_conf =
  939. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  940. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
  941. break;
  942. default:
  943. break;
  944. }
  945. }
  946. static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
  947. struct ath_hw_antcomb_conf *div_ant_conf,
  948. int main_rssi_avg, int alt_rssi_avg,
  949. int alt_ratio)
  950. {
  951. /* alt_good */
  952. switch (antcomb->quick_scan_cnt) {
  953. case 0:
  954. /* set alt to main, and alt to first conf */
  955. div_ant_conf->main_lna_conf = antcomb->main_conf;
  956. div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
  957. break;
  958. case 1:
  959. /* set alt to main, and alt to first conf */
  960. div_ant_conf->main_lna_conf = antcomb->main_conf;
  961. div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
  962. antcomb->rssi_first = main_rssi_avg;
  963. antcomb->rssi_second = alt_rssi_avg;
  964. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
  965. /* main is LNA1 */
  966. if (ath_is_alt_ant_ratio_better(alt_ratio,
  967. ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
  968. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  969. main_rssi_avg, alt_rssi_avg,
  970. antcomb->total_pkt_count))
  971. antcomb->first_ratio = true;
  972. else
  973. antcomb->first_ratio = false;
  974. } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
  975. if (ath_is_alt_ant_ratio_better(alt_ratio,
  976. ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
  977. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  978. main_rssi_avg, alt_rssi_avg,
  979. antcomb->total_pkt_count))
  980. antcomb->first_ratio = true;
  981. else
  982. antcomb->first_ratio = false;
  983. } else {
  984. if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  985. (alt_rssi_avg > main_rssi_avg +
  986. ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
  987. (alt_rssi_avg > main_rssi_avg)) &&
  988. (antcomb->total_pkt_count > 50))
  989. antcomb->first_ratio = true;
  990. else
  991. antcomb->first_ratio = false;
  992. }
  993. break;
  994. case 2:
  995. antcomb->alt_good = false;
  996. antcomb->scan_not_start = false;
  997. antcomb->scan = false;
  998. antcomb->rssi_first = main_rssi_avg;
  999. antcomb->rssi_third = alt_rssi_avg;
  1000. if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
  1001. antcomb->rssi_lna1 = alt_rssi_avg;
  1002. else if (antcomb->second_quick_scan_conf ==
  1003. ATH_ANT_DIV_COMB_LNA2)
  1004. antcomb->rssi_lna2 = alt_rssi_avg;
  1005. else if (antcomb->second_quick_scan_conf ==
  1006. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
  1007. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
  1008. antcomb->rssi_lna2 = main_rssi_avg;
  1009. else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
  1010. antcomb->rssi_lna1 = main_rssi_avg;
  1011. }
  1012. if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
  1013. ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
  1014. div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
  1015. else
  1016. div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
  1017. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
  1018. if (ath_is_alt_ant_ratio_better(alt_ratio,
  1019. ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
  1020. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  1021. main_rssi_avg, alt_rssi_avg,
  1022. antcomb->total_pkt_count))
  1023. antcomb->second_ratio = true;
  1024. else
  1025. antcomb->second_ratio = false;
  1026. } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
  1027. if (ath_is_alt_ant_ratio_better(alt_ratio,
  1028. ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
  1029. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  1030. main_rssi_avg, alt_rssi_avg,
  1031. antcomb->total_pkt_count))
  1032. antcomb->second_ratio = true;
  1033. else
  1034. antcomb->second_ratio = false;
  1035. } else {
  1036. if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  1037. (alt_rssi_avg > main_rssi_avg +
  1038. ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
  1039. (alt_rssi_avg > main_rssi_avg)) &&
  1040. (antcomb->total_pkt_count > 50))
  1041. antcomb->second_ratio = true;
  1042. else
  1043. antcomb->second_ratio = false;
  1044. }
  1045. /* set alt to the conf with maximun ratio */
  1046. if (antcomb->first_ratio && antcomb->second_ratio) {
  1047. if (antcomb->rssi_second > antcomb->rssi_third) {
  1048. /* first alt*/
  1049. if ((antcomb->first_quick_scan_conf ==
  1050. ATH_ANT_DIV_COMB_LNA1) ||
  1051. (antcomb->first_quick_scan_conf ==
  1052. ATH_ANT_DIV_COMB_LNA2))
  1053. /* Set alt LNA1 or LNA2*/
  1054. if (div_ant_conf->main_lna_conf ==
  1055. ATH_ANT_DIV_COMB_LNA2)
  1056. div_ant_conf->alt_lna_conf =
  1057. ATH_ANT_DIV_COMB_LNA1;
  1058. else
  1059. div_ant_conf->alt_lna_conf =
  1060. ATH_ANT_DIV_COMB_LNA2;
  1061. else
  1062. /* Set alt to A+B or A-B */
  1063. div_ant_conf->alt_lna_conf =
  1064. antcomb->first_quick_scan_conf;
  1065. } else if ((antcomb->second_quick_scan_conf ==
  1066. ATH_ANT_DIV_COMB_LNA1) ||
  1067. (antcomb->second_quick_scan_conf ==
  1068. ATH_ANT_DIV_COMB_LNA2)) {
  1069. /* Set alt LNA1 or LNA2 */
  1070. if (div_ant_conf->main_lna_conf ==
  1071. ATH_ANT_DIV_COMB_LNA2)
  1072. div_ant_conf->alt_lna_conf =
  1073. ATH_ANT_DIV_COMB_LNA1;
  1074. else
  1075. div_ant_conf->alt_lna_conf =
  1076. ATH_ANT_DIV_COMB_LNA2;
  1077. } else {
  1078. /* Set alt to A+B or A-B */
  1079. div_ant_conf->alt_lna_conf =
  1080. antcomb->second_quick_scan_conf;
  1081. }
  1082. } else if (antcomb->first_ratio) {
  1083. /* first alt */
  1084. if ((antcomb->first_quick_scan_conf ==
  1085. ATH_ANT_DIV_COMB_LNA1) ||
  1086. (antcomb->first_quick_scan_conf ==
  1087. ATH_ANT_DIV_COMB_LNA2))
  1088. /* Set alt LNA1 or LNA2 */
  1089. if (div_ant_conf->main_lna_conf ==
  1090. ATH_ANT_DIV_COMB_LNA2)
  1091. div_ant_conf->alt_lna_conf =
  1092. ATH_ANT_DIV_COMB_LNA1;
  1093. else
  1094. div_ant_conf->alt_lna_conf =
  1095. ATH_ANT_DIV_COMB_LNA2;
  1096. else
  1097. /* Set alt to A+B or A-B */
  1098. div_ant_conf->alt_lna_conf =
  1099. antcomb->first_quick_scan_conf;
  1100. } else if (antcomb->second_ratio) {
  1101. /* second alt */
  1102. if ((antcomb->second_quick_scan_conf ==
  1103. ATH_ANT_DIV_COMB_LNA1) ||
  1104. (antcomb->second_quick_scan_conf ==
  1105. ATH_ANT_DIV_COMB_LNA2))
  1106. /* Set alt LNA1 or LNA2 */
  1107. if (div_ant_conf->main_lna_conf ==
  1108. ATH_ANT_DIV_COMB_LNA2)
  1109. div_ant_conf->alt_lna_conf =
  1110. ATH_ANT_DIV_COMB_LNA1;
  1111. else
  1112. div_ant_conf->alt_lna_conf =
  1113. ATH_ANT_DIV_COMB_LNA2;
  1114. else
  1115. /* Set alt to A+B or A-B */
  1116. div_ant_conf->alt_lna_conf =
  1117. antcomb->second_quick_scan_conf;
  1118. } else {
  1119. /* main is largest */
  1120. if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
  1121. (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
  1122. /* Set alt LNA1 or LNA2 */
  1123. if (div_ant_conf->main_lna_conf ==
  1124. ATH_ANT_DIV_COMB_LNA2)
  1125. div_ant_conf->alt_lna_conf =
  1126. ATH_ANT_DIV_COMB_LNA1;
  1127. else
  1128. div_ant_conf->alt_lna_conf =
  1129. ATH_ANT_DIV_COMB_LNA2;
  1130. else
  1131. /* Set alt to A+B or A-B */
  1132. div_ant_conf->alt_lna_conf = antcomb->main_conf;
  1133. }
  1134. break;
  1135. default:
  1136. break;
  1137. }
  1138. }
  1139. static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
  1140. struct ath_ant_comb *antcomb, int alt_ratio)
  1141. {
  1142. if (ant_conf->div_group == 0) {
  1143. /* Adjust the fast_div_bias based on main and alt lna conf */
  1144. switch ((ant_conf->main_lna_conf << 4) |
  1145. ant_conf->alt_lna_conf) {
  1146. case 0x01: /* A-B LNA2 */
  1147. ant_conf->fast_div_bias = 0x3b;
  1148. break;
  1149. case 0x02: /* A-B LNA1 */
  1150. ant_conf->fast_div_bias = 0x3d;
  1151. break;
  1152. case 0x03: /* A-B A+B */
  1153. ant_conf->fast_div_bias = 0x1;
  1154. break;
  1155. case 0x10: /* LNA2 A-B */
  1156. ant_conf->fast_div_bias = 0x7;
  1157. break;
  1158. case 0x12: /* LNA2 LNA1 */
  1159. ant_conf->fast_div_bias = 0x2;
  1160. break;
  1161. case 0x13: /* LNA2 A+B */
  1162. ant_conf->fast_div_bias = 0x7;
  1163. break;
  1164. case 0x20: /* LNA1 A-B */
  1165. ant_conf->fast_div_bias = 0x6;
  1166. break;
  1167. case 0x21: /* LNA1 LNA2 */
  1168. ant_conf->fast_div_bias = 0x0;
  1169. break;
  1170. case 0x23: /* LNA1 A+B */
  1171. ant_conf->fast_div_bias = 0x6;
  1172. break;
  1173. case 0x30: /* A+B A-B */
  1174. ant_conf->fast_div_bias = 0x1;
  1175. break;
  1176. case 0x31: /* A+B LNA2 */
  1177. ant_conf->fast_div_bias = 0x3b;
  1178. break;
  1179. case 0x32: /* A+B LNA1 */
  1180. ant_conf->fast_div_bias = 0x3d;
  1181. break;
  1182. default:
  1183. break;
  1184. }
  1185. } else if (ant_conf->div_group == 2) {
  1186. /* Adjust the fast_div_bias based on main and alt_lna_conf */
  1187. switch ((ant_conf->main_lna_conf << 4) |
  1188. ant_conf->alt_lna_conf) {
  1189. case 0x01: /* A-B LNA2 */
  1190. ant_conf->fast_div_bias = 0x1;
  1191. ant_conf->main_gaintb = 0;
  1192. ant_conf->alt_gaintb = 0;
  1193. break;
  1194. case 0x02: /* A-B LNA1 */
  1195. ant_conf->fast_div_bias = 0x1;
  1196. ant_conf->main_gaintb = 0;
  1197. ant_conf->alt_gaintb = 0;
  1198. break;
  1199. case 0x03: /* A-B A+B */
  1200. ant_conf->fast_div_bias = 0x1;
  1201. ant_conf->main_gaintb = 0;
  1202. ant_conf->alt_gaintb = 0;
  1203. break;
  1204. case 0x10: /* LNA2 A-B */
  1205. if (!(antcomb->scan) &&
  1206. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1207. ant_conf->fast_div_bias = 0x1;
  1208. else
  1209. ant_conf->fast_div_bias = 0x2;
  1210. ant_conf->main_gaintb = 0;
  1211. ant_conf->alt_gaintb = 0;
  1212. break;
  1213. case 0x12: /* LNA2 LNA1 */
  1214. ant_conf->fast_div_bias = 0x1;
  1215. ant_conf->main_gaintb = 0;
  1216. ant_conf->alt_gaintb = 0;
  1217. break;
  1218. case 0x13: /* LNA2 A+B */
  1219. if (!(antcomb->scan) &&
  1220. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1221. ant_conf->fast_div_bias = 0x1;
  1222. else
  1223. ant_conf->fast_div_bias = 0x2;
  1224. ant_conf->main_gaintb = 0;
  1225. ant_conf->alt_gaintb = 0;
  1226. break;
  1227. case 0x20: /* LNA1 A-B */
  1228. if (!(antcomb->scan) &&
  1229. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1230. ant_conf->fast_div_bias = 0x1;
  1231. else
  1232. ant_conf->fast_div_bias = 0x2;
  1233. ant_conf->main_gaintb = 0;
  1234. ant_conf->alt_gaintb = 0;
  1235. break;
  1236. case 0x21: /* LNA1 LNA2 */
  1237. ant_conf->fast_div_bias = 0x1;
  1238. ant_conf->main_gaintb = 0;
  1239. ant_conf->alt_gaintb = 0;
  1240. break;
  1241. case 0x23: /* LNA1 A+B */
  1242. if (!(antcomb->scan) &&
  1243. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1244. ant_conf->fast_div_bias = 0x1;
  1245. else
  1246. ant_conf->fast_div_bias = 0x2;
  1247. ant_conf->main_gaintb = 0;
  1248. ant_conf->alt_gaintb = 0;
  1249. break;
  1250. case 0x30: /* A+B A-B */
  1251. ant_conf->fast_div_bias = 0x1;
  1252. ant_conf->main_gaintb = 0;
  1253. ant_conf->alt_gaintb = 0;
  1254. break;
  1255. case 0x31: /* A+B LNA2 */
  1256. ant_conf->fast_div_bias = 0x1;
  1257. ant_conf->main_gaintb = 0;
  1258. ant_conf->alt_gaintb = 0;
  1259. break;
  1260. case 0x32: /* A+B LNA1 */
  1261. ant_conf->fast_div_bias = 0x1;
  1262. ant_conf->main_gaintb = 0;
  1263. ant_conf->alt_gaintb = 0;
  1264. break;
  1265. default:
  1266. break;
  1267. }
  1268. }
  1269. }
  1270. /* Antenna diversity and combining */
  1271. static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
  1272. {
  1273. struct ath_hw_antcomb_conf div_ant_conf;
  1274. struct ath_ant_comb *antcomb = &sc->ant_comb;
  1275. int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
  1276. int curr_main_set;
  1277. int main_rssi = rs->rs_rssi_ctl0;
  1278. int alt_rssi = rs->rs_rssi_ctl1;
  1279. int rx_ant_conf, main_ant_conf;
  1280. bool short_scan = false;
  1281. rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
  1282. ATH_ANT_RX_MASK;
  1283. main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
  1284. ATH_ANT_RX_MASK;
  1285. /* Record packet only when both main_rssi and alt_rssi is positive */
  1286. if (main_rssi > 0 && alt_rssi > 0) {
  1287. antcomb->total_pkt_count++;
  1288. antcomb->main_total_rssi += main_rssi;
  1289. antcomb->alt_total_rssi += alt_rssi;
  1290. if (main_ant_conf == rx_ant_conf)
  1291. antcomb->main_recv_cnt++;
  1292. else
  1293. antcomb->alt_recv_cnt++;
  1294. }
  1295. /* Short scan check */
  1296. if (antcomb->scan && antcomb->alt_good) {
  1297. if (time_after(jiffies, antcomb->scan_start_time +
  1298. msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
  1299. short_scan = true;
  1300. else
  1301. if (antcomb->total_pkt_count ==
  1302. ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
  1303. alt_ratio = ((antcomb->alt_recv_cnt * 100) /
  1304. antcomb->total_pkt_count);
  1305. if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
  1306. short_scan = true;
  1307. }
  1308. }
  1309. if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
  1310. rs->rs_moreaggr) && !short_scan)
  1311. return;
  1312. if (antcomb->total_pkt_count) {
  1313. alt_ratio = ((antcomb->alt_recv_cnt * 100) /
  1314. antcomb->total_pkt_count);
  1315. main_rssi_avg = (antcomb->main_total_rssi /
  1316. antcomb->total_pkt_count);
  1317. alt_rssi_avg = (antcomb->alt_total_rssi /
  1318. antcomb->total_pkt_count);
  1319. }
  1320. ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
  1321. curr_alt_set = div_ant_conf.alt_lna_conf;
  1322. curr_main_set = div_ant_conf.main_lna_conf;
  1323. antcomb->count++;
  1324. if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
  1325. if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
  1326. ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
  1327. main_rssi_avg);
  1328. antcomb->alt_good = true;
  1329. } else {
  1330. antcomb->alt_good = false;
  1331. }
  1332. antcomb->count = 0;
  1333. antcomb->scan = true;
  1334. antcomb->scan_not_start = true;
  1335. }
  1336. if (!antcomb->scan) {
  1337. if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
  1338. alt_ratio, curr_main_set, curr_alt_set,
  1339. alt_rssi_avg, main_rssi_avg)) {
  1340. if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
  1341. /* Switch main and alt LNA */
  1342. div_ant_conf.main_lna_conf =
  1343. ATH_ANT_DIV_COMB_LNA2;
  1344. div_ant_conf.alt_lna_conf =
  1345. ATH_ANT_DIV_COMB_LNA1;
  1346. } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
  1347. div_ant_conf.main_lna_conf =
  1348. ATH_ANT_DIV_COMB_LNA1;
  1349. div_ant_conf.alt_lna_conf =
  1350. ATH_ANT_DIV_COMB_LNA2;
  1351. }
  1352. goto div_comb_done;
  1353. } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
  1354. (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
  1355. /* Set alt to another LNA */
  1356. if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
  1357. div_ant_conf.alt_lna_conf =
  1358. ATH_ANT_DIV_COMB_LNA1;
  1359. else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
  1360. div_ant_conf.alt_lna_conf =
  1361. ATH_ANT_DIV_COMB_LNA2;
  1362. goto div_comb_done;
  1363. }
  1364. if ((alt_rssi_avg < (main_rssi_avg +
  1365. div_ant_conf.lna1_lna2_delta)))
  1366. goto div_comb_done;
  1367. }
  1368. if (!antcomb->scan_not_start) {
  1369. switch (curr_alt_set) {
  1370. case ATH_ANT_DIV_COMB_LNA2:
  1371. antcomb->rssi_lna2 = alt_rssi_avg;
  1372. antcomb->rssi_lna1 = main_rssi_avg;
  1373. antcomb->scan = true;
  1374. /* set to A+B */
  1375. div_ant_conf.main_lna_conf =
  1376. ATH_ANT_DIV_COMB_LNA1;
  1377. div_ant_conf.alt_lna_conf =
  1378. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1379. break;
  1380. case ATH_ANT_DIV_COMB_LNA1:
  1381. antcomb->rssi_lna1 = alt_rssi_avg;
  1382. antcomb->rssi_lna2 = main_rssi_avg;
  1383. antcomb->scan = true;
  1384. /* set to A+B */
  1385. div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
  1386. div_ant_conf.alt_lna_conf =
  1387. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1388. break;
  1389. case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
  1390. antcomb->rssi_add = alt_rssi_avg;
  1391. antcomb->scan = true;
  1392. /* set to A-B */
  1393. div_ant_conf.alt_lna_conf =
  1394. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1395. break;
  1396. case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
  1397. antcomb->rssi_sub = alt_rssi_avg;
  1398. antcomb->scan = false;
  1399. if (antcomb->rssi_lna2 >
  1400. (antcomb->rssi_lna1 +
  1401. ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
  1402. /* use LNA2 as main LNA */
  1403. if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
  1404. (antcomb->rssi_add > antcomb->rssi_sub)) {
  1405. /* set to A+B */
  1406. div_ant_conf.main_lna_conf =
  1407. ATH_ANT_DIV_COMB_LNA2;
  1408. div_ant_conf.alt_lna_conf =
  1409. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1410. } else if (antcomb->rssi_sub >
  1411. antcomb->rssi_lna1) {
  1412. /* set to A-B */
  1413. div_ant_conf.main_lna_conf =
  1414. ATH_ANT_DIV_COMB_LNA2;
  1415. div_ant_conf.alt_lna_conf =
  1416. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1417. } else {
  1418. /* set to LNA1 */
  1419. div_ant_conf.main_lna_conf =
  1420. ATH_ANT_DIV_COMB_LNA2;
  1421. div_ant_conf.alt_lna_conf =
  1422. ATH_ANT_DIV_COMB_LNA1;
  1423. }
  1424. } else {
  1425. /* use LNA1 as main LNA */
  1426. if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
  1427. (antcomb->rssi_add > antcomb->rssi_sub)) {
  1428. /* set to A+B */
  1429. div_ant_conf.main_lna_conf =
  1430. ATH_ANT_DIV_COMB_LNA1;
  1431. div_ant_conf.alt_lna_conf =
  1432. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1433. } else if (antcomb->rssi_sub >
  1434. antcomb->rssi_lna1) {
  1435. /* set to A-B */
  1436. div_ant_conf.main_lna_conf =
  1437. ATH_ANT_DIV_COMB_LNA1;
  1438. div_ant_conf.alt_lna_conf =
  1439. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1440. } else {
  1441. /* set to LNA2 */
  1442. div_ant_conf.main_lna_conf =
  1443. ATH_ANT_DIV_COMB_LNA1;
  1444. div_ant_conf.alt_lna_conf =
  1445. ATH_ANT_DIV_COMB_LNA2;
  1446. }
  1447. }
  1448. break;
  1449. default:
  1450. break;
  1451. }
  1452. } else {
  1453. if (!antcomb->alt_good) {
  1454. antcomb->scan_not_start = false;
  1455. /* Set alt to another LNA */
  1456. if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
  1457. div_ant_conf.main_lna_conf =
  1458. ATH_ANT_DIV_COMB_LNA2;
  1459. div_ant_conf.alt_lna_conf =
  1460. ATH_ANT_DIV_COMB_LNA1;
  1461. } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
  1462. div_ant_conf.main_lna_conf =
  1463. ATH_ANT_DIV_COMB_LNA1;
  1464. div_ant_conf.alt_lna_conf =
  1465. ATH_ANT_DIV_COMB_LNA2;
  1466. }
  1467. goto div_comb_done;
  1468. }
  1469. }
  1470. ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
  1471. main_rssi_avg, alt_rssi_avg,
  1472. alt_ratio);
  1473. antcomb->quick_scan_cnt++;
  1474. div_comb_done:
  1475. ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
  1476. ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
  1477. antcomb->scan_start_time = jiffies;
  1478. antcomb->total_pkt_count = 0;
  1479. antcomb->main_total_rssi = 0;
  1480. antcomb->alt_total_rssi = 0;
  1481. antcomb->main_recv_cnt = 0;
  1482. antcomb->alt_recv_cnt = 0;
  1483. }
  1484. int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
  1485. {
  1486. struct ath_buf *bf;
  1487. struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
  1488. struct ieee80211_rx_status *rxs;
  1489. struct ath_hw *ah = sc->sc_ah;
  1490. struct ath_common *common = ath9k_hw_common(ah);
  1491. /*
  1492. * The hw can technically differ from common->hw when using ath9k
  1493. * virtual wiphy so to account for that we iterate over the active
  1494. * wiphys and find the appropriate wiphy and therefore hw.
  1495. */
  1496. struct ieee80211_hw *hw = sc->hw;
  1497. struct ieee80211_hdr *hdr;
  1498. int retval;
  1499. bool decrypt_error = false;
  1500. struct ath_rx_status rs;
  1501. enum ath9k_rx_qtype qtype;
  1502. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1503. int dma_type;
  1504. u8 rx_status_len = ah->caps.rx_status_len;
  1505. u64 tsf = 0;
  1506. u32 tsf_lower = 0;
  1507. unsigned long flags;
  1508. if (edma)
  1509. dma_type = DMA_BIDIRECTIONAL;
  1510. else
  1511. dma_type = DMA_FROM_DEVICE;
  1512. qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
  1513. spin_lock_bh(&sc->rx.rxbuflock);
  1514. tsf = ath9k_hw_gettsf64(ah);
  1515. tsf_lower = tsf & 0xffffffff;
  1516. do {
  1517. /* If handling rx interrupt and flush is in progress => exit */
  1518. if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
  1519. break;
  1520. memset(&rs, 0, sizeof(rs));
  1521. if (edma)
  1522. bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
  1523. else
  1524. bf = ath_get_next_rx_buf(sc, &rs);
  1525. if (!bf)
  1526. break;
  1527. skb = bf->bf_mpdu;
  1528. if (!skb)
  1529. continue;
  1530. /*
  1531. * Take frame header from the first fragment and RX status from
  1532. * the last one.
  1533. */
  1534. if (sc->rx.frag)
  1535. hdr_skb = sc->rx.frag;
  1536. else
  1537. hdr_skb = skb;
  1538. hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
  1539. rxs = IEEE80211_SKB_RXCB(hdr_skb);
  1540. ath_debug_stat_rx(sc, &rs);
  1541. /*
  1542. * If we're asked to flush receive queue, directly
  1543. * chain it back at the queue without processing it.
  1544. */
  1545. if (flush)
  1546. goto requeue_drop_frag;
  1547. retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
  1548. rxs, &decrypt_error);
  1549. if (retval)
  1550. goto requeue_drop_frag;
  1551. rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
  1552. if (rs.rs_tstamp > tsf_lower &&
  1553. unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
  1554. rxs->mactime -= 0x100000000ULL;
  1555. if (rs.rs_tstamp < tsf_lower &&
  1556. unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
  1557. rxs->mactime += 0x100000000ULL;
  1558. /* Ensure we always have an skb to requeue once we are done
  1559. * processing the current buffer's skb */
  1560. requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
  1561. /* If there is no memory we ignore the current RX'd frame,
  1562. * tell hardware it can give us a new frame using the old
  1563. * skb and put it at the tail of the sc->rx.rxbuf list for
  1564. * processing. */
  1565. if (!requeue_skb)
  1566. goto requeue_drop_frag;
  1567. /* Unmap the frame */
  1568. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  1569. common->rx_bufsize,
  1570. dma_type);
  1571. skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
  1572. if (ah->caps.rx_status_len)
  1573. skb_pull(skb, ah->caps.rx_status_len);
  1574. if (!rs.rs_more)
  1575. ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
  1576. rxs, decrypt_error);
  1577. /* We will now give hardware our shiny new allocated skb */
  1578. bf->bf_mpdu = requeue_skb;
  1579. bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
  1580. common->rx_bufsize,
  1581. dma_type);
  1582. if (unlikely(dma_mapping_error(sc->dev,
  1583. bf->bf_buf_addr))) {
  1584. dev_kfree_skb_any(requeue_skb);
  1585. bf->bf_mpdu = NULL;
  1586. bf->bf_buf_addr = 0;
  1587. ath_err(common, "dma_mapping_error() on RX\n");
  1588. ieee80211_rx(hw, skb);
  1589. break;
  1590. }
  1591. if (rs.rs_more) {
  1592. /*
  1593. * rs_more indicates chained descriptors which can be
  1594. * used to link buffers together for a sort of
  1595. * scatter-gather operation.
  1596. */
  1597. if (sc->rx.frag) {
  1598. /* too many fragments - cannot handle frame */
  1599. dev_kfree_skb_any(sc->rx.frag);
  1600. dev_kfree_skb_any(skb);
  1601. skb = NULL;
  1602. }
  1603. sc->rx.frag = skb;
  1604. goto requeue;
  1605. }
  1606. if (sc->rx.frag) {
  1607. int space = skb->len - skb_tailroom(hdr_skb);
  1608. sc->rx.frag = NULL;
  1609. if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
  1610. dev_kfree_skb(skb);
  1611. goto requeue_drop_frag;
  1612. }
  1613. skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
  1614. skb->len);
  1615. dev_kfree_skb_any(skb);
  1616. skb = hdr_skb;
  1617. }
  1618. /*
  1619. * change the default rx antenna if rx diversity chooses the
  1620. * other antenna 3 times in a row.
  1621. */
  1622. if (sc->rx.defant != rs.rs_antenna) {
  1623. if (++sc->rx.rxotherant >= 3)
  1624. ath_setdefantenna(sc, rs.rs_antenna);
  1625. } else {
  1626. sc->rx.rxotherant = 0;
  1627. }
  1628. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1629. if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
  1630. PS_WAIT_FOR_CAB |
  1631. PS_WAIT_FOR_PSPOLL_DATA)) ||
  1632. ath9k_check_auto_sleep(sc))
  1633. ath_rx_ps(sc, skb);
  1634. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1635. if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
  1636. ath_ant_comb_scan(sc, &rs);
  1637. ieee80211_rx(hw, skb);
  1638. requeue_drop_frag:
  1639. if (sc->rx.frag) {
  1640. dev_kfree_skb_any(sc->rx.frag);
  1641. sc->rx.frag = NULL;
  1642. }
  1643. requeue:
  1644. if (edma) {
  1645. list_add_tail(&bf->list, &sc->rx.rxbuf);
  1646. ath_rx_edma_buf_link(sc, qtype);
  1647. } else {
  1648. list_move_tail(&bf->list, &sc->rx.rxbuf);
  1649. ath_rx_buf_link(sc, bf);
  1650. ath9k_hw_rxena(ah);
  1651. }
  1652. } while (1);
  1653. spin_unlock_bh(&sc->rx.rxbuflock);
  1654. return 0;
  1655. }