ab8500.h 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201
  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. */
  7. #ifndef MFD_AB8500_H
  8. #define MFD_AB8500_H
  9. #include <linux/device.h>
  10. /*
  11. * AB8500 bank addresses
  12. */
  13. #define AB8500_SYS_CTRL1_BLOCK 0x1
  14. #define AB8500_SYS_CTRL2_BLOCK 0x2
  15. #define AB8500_REGU_CTRL1 0x3
  16. #define AB8500_REGU_CTRL2 0x4
  17. #define AB8500_USB 0x5
  18. #define AB8500_TVOUT 0x6
  19. #define AB8500_DBI 0x7
  20. #define AB8500_ECI_AV_ACC 0x8
  21. #define AB8500_RESERVED 0x9
  22. #define AB8500_GPADC 0xA
  23. #define AB8500_CHARGER 0xB
  24. #define AB8500_GAS_GAUGE 0xC
  25. #define AB8500_AUDIO 0xD
  26. #define AB8500_INTERRUPT 0xE
  27. #define AB8500_RTC 0xF
  28. #define AB8500_MISC 0x10
  29. #define AB8500_DEVELOPMENT 0x11
  30. #define AB8500_DEBUG 0x12
  31. #define AB8500_PROD_TEST 0x13
  32. #define AB8500_OTP_EMUL 0x15
  33. /*
  34. * Interrupts
  35. */
  36. #define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
  37. #define AB8500_INT_UN_PLUG_TV_DET 1
  38. #define AB8500_INT_PLUG_TV_DET 2
  39. #define AB8500_INT_TEMP_WARM 3
  40. #define AB8500_INT_PON_KEY2DB_F 4
  41. #define AB8500_INT_PON_KEY2DB_R 5
  42. #define AB8500_INT_PON_KEY1DB_F 6
  43. #define AB8500_INT_PON_KEY1DB_R 7
  44. #define AB8500_INT_BATT_OVV 8
  45. #define AB8500_INT_MAIN_CH_UNPLUG_DET 10
  46. #define AB8500_INT_MAIN_CH_PLUG_DET 11
  47. #define AB8500_INT_USB_ID_DET_F 12
  48. #define AB8500_INT_USB_ID_DET_R 13
  49. #define AB8500_INT_VBUS_DET_F 14
  50. #define AB8500_INT_VBUS_DET_R 15
  51. #define AB8500_INT_VBUS_CH_DROP_END 16
  52. #define AB8500_INT_RTC_60S 17
  53. #define AB8500_INT_RTC_ALARM 18
  54. #define AB8500_INT_BAT_CTRL_INDB 20
  55. #define AB8500_INT_CH_WD_EXP 21
  56. #define AB8500_INT_VBUS_OVV 22
  57. #define AB8500_INT_MAIN_CH_DROP_END 23
  58. #define AB8500_INT_CCN_CONV_ACC 24
  59. #define AB8500_INT_INT_AUD 25
  60. #define AB8500_INT_CCEOC 26
  61. #define AB8500_INT_CC_INT_CALIB 27
  62. #define AB8500_INT_LOW_BAT_F 28
  63. #define AB8500_INT_LOW_BAT_R 29
  64. #define AB8500_INT_BUP_CHG_NOT_OK 30
  65. #define AB8500_INT_BUP_CHG_OK 31
  66. #define AB8500_INT_GP_HW_ADC_CONV_END 32
  67. #define AB8500_INT_ACC_DETECT_1DB_F 33
  68. #define AB8500_INT_ACC_DETECT_1DB_R 34
  69. #define AB8500_INT_ACC_DETECT_22DB_F 35
  70. #define AB8500_INT_ACC_DETECT_22DB_R 36
  71. #define AB8500_INT_ACC_DETECT_21DB_F 37
  72. #define AB8500_INT_ACC_DETECT_21DB_R 38
  73. #define AB8500_INT_GP_SW_ADC_CONV_END 39
  74. #define AB8500_INT_GPIO6R 40
  75. #define AB8500_INT_GPIO7R 41
  76. #define AB8500_INT_GPIO8R 42
  77. #define AB8500_INT_GPIO9R 43
  78. #define AB8500_INT_GPIO10R 44
  79. #define AB8500_INT_GPIO11R 45
  80. #define AB8500_INT_GPIO12R 46
  81. #define AB8500_INT_GPIO13R 47
  82. #define AB8500_INT_GPIO24R 48
  83. #define AB8500_INT_GPIO25R 49
  84. #define AB8500_INT_GPIO36R 50
  85. #define AB8500_INT_GPIO37R 51
  86. #define AB8500_INT_GPIO38R 52
  87. #define AB8500_INT_GPIO39R 53
  88. #define AB8500_INT_GPIO40R 54
  89. #define AB8500_INT_GPIO41R 55
  90. #define AB8500_INT_GPIO6F 56
  91. #define AB8500_INT_GPIO7F 57
  92. #define AB8500_INT_GPIO8F 58
  93. #define AB8500_INT_GPIO9F 59
  94. #define AB8500_INT_GPIO10F 60
  95. #define AB8500_INT_GPIO11F 61
  96. #define AB8500_INT_GPIO12F 62
  97. #define AB8500_INT_GPIO13F 63
  98. #define AB8500_INT_GPIO24F 64
  99. #define AB8500_INT_GPIO25F 65
  100. #define AB8500_INT_GPIO36F 66
  101. #define AB8500_INT_GPIO37F 67
  102. #define AB8500_INT_GPIO38F 68
  103. #define AB8500_INT_GPIO39F 69
  104. #define AB8500_INT_GPIO40F 70
  105. #define AB8500_INT_GPIO41F 71
  106. #define AB8500_INT_ADP_SOURCE_ERROR 72
  107. #define AB8500_INT_ADP_SINK_ERROR 73
  108. #define AB8500_INT_ADP_PROBE_PLUG 74
  109. #define AB8500_INT_ADP_PROBE_UNPLUG 75
  110. #define AB8500_INT_ADP_SENSE_OFF 76
  111. #define AB8500_INT_USB_PHY_POWER_ERR 78
  112. #define AB8500_INT_USB_LINK_STATUS 79
  113. #define AB8500_INT_BTEMP_LOW 80
  114. #define AB8500_INT_BTEMP_LOW_MEDIUM 81
  115. #define AB8500_INT_BTEMP_MEDIUM_HIGH 82
  116. #define AB8500_INT_BTEMP_HIGH 83
  117. #define AB8500_INT_USB_CHARGER_NOT_OK 89
  118. #define AB8500_INT_ID_WAKEUP_R 90
  119. #define AB8500_INT_ID_DET_R1R 92
  120. #define AB8500_INT_ID_DET_R2R 93
  121. #define AB8500_INT_ID_DET_R3R 94
  122. #define AB8500_INT_ID_DET_R4R 95
  123. #define AB8500_INT_ID_WAKEUP_F 96
  124. #define AB8500_INT_ID_DET_R1F 98
  125. #define AB8500_INT_ID_DET_R2F 99
  126. #define AB8500_INT_ID_DET_R3F 100
  127. #define AB8500_INT_ID_DET_R4F 101
  128. #define AB8500_INT_USB_CHG_DET_DONE 102
  129. #define AB8500_INT_USB_CH_TH_PROT_F 104
  130. #define AB8500_INT_USB_CH_TH_PROT_R 105
  131. #define AB8500_INT_MAIN_CH_TH_PROT_F 106
  132. #define AB8500_INT_MAIN_CH_TH_PROT_R 107
  133. #define AB8500_INT_USB_CHARGER_NOT_OKF 111
  134. #define AB8500_NR_IRQS 112
  135. #define AB8500_NUM_IRQ_REGS 14
  136. /**
  137. * struct ab8500 - ab8500 internal structure
  138. * @dev: parent device
  139. * @lock: read/write operations lock
  140. * @irq_lock: genirq bus lock
  141. * @irq: irq line
  142. * @chip_id: chip revision id
  143. * @write: register write
  144. * @read: register read
  145. * @rx_buf: rx buf for SPI
  146. * @tx_buf: tx buf for SPI
  147. * @mask: cache of IRQ regs for bus lock
  148. * @oldmask: cache of previous IRQ regs for bus lock
  149. */
  150. struct ab8500 {
  151. struct device *dev;
  152. struct mutex lock;
  153. struct mutex irq_lock;
  154. int irq_base;
  155. int irq;
  156. u8 chip_id;
  157. int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
  158. int (*read) (struct ab8500 *a8500, u16 addr);
  159. unsigned long tx_buf[4];
  160. unsigned long rx_buf[4];
  161. u8 mask[AB8500_NUM_IRQ_REGS];
  162. u8 oldmask[AB8500_NUM_IRQ_REGS];
  163. };
  164. struct regulator_reg_init;
  165. struct regulator_init_data;
  166. struct ab8500_gpio_platform_data;
  167. /**
  168. * struct ab8500_platform_data - AB8500 platform data
  169. * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
  170. * @init: board-specific initialization after detection of ab8500
  171. * @num_regulator_reg_init: number of regulator init registers
  172. * @regulator_reg_init: regulator init registers
  173. * @num_regulator: number of regulators
  174. * @regulator: machine-specific constraints for regulators
  175. */
  176. struct ab8500_platform_data {
  177. int irq_base;
  178. void (*init) (struct ab8500 *);
  179. int num_regulator_reg_init;
  180. struct ab8500_regulator_reg_init *regulator_reg_init;
  181. int num_regulator;
  182. struct regulator_init_data *regulator;
  183. struct ab8500_gpio_platform_data *gpio;
  184. };
  185. extern int __devinit ab8500_init(struct ab8500 *ab8500);
  186. extern int __devexit ab8500_exit(struct ab8500 *ab8500);
  187. #endif /* MFD_AB8500_H */